US20170033236A1 - Thin-film transistor structure - Google Patents

Thin-film transistor structure Download PDF

Info

Publication number
US20170033236A1
US20170033236A1 US14/932,215 US201514932215A US2017033236A1 US 20170033236 A1 US20170033236 A1 US 20170033236A1 US 201514932215 A US201514932215 A US 201514932215A US 2017033236 A1 US2017033236 A1 US 2017033236A1
Authority
US
United States
Prior art keywords
metal layer
thin
film transistor
present
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US14/932,215
Other languages
English (en)
Inventor
Kai-Ju Chou
Che-Yao WU
Ku-Huang Lai
I-Ta Jiang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Giantplus Technology Co Ltd
Original Assignee
Giantplus Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Giantplus Technology Co Ltd filed Critical Giantplus Technology Co Ltd
Assigned to GIANTPLUS TECHNOLOGY CO., LTD. reassignment GIANTPLUS TECHNOLOGY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHOU, KAI-JU, JIANG, I-TA, WU, CHE-YAO, LAI, KU-HUANG
Publication of US20170033236A1 publication Critical patent/US20170033236A1/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates generally to a thin-film transistor structure, and particularly to a thin-film transistor structure having double gates.
  • TFT-LCD thin-film transistor liquid crystal displays
  • thin-film transistors When a thin-film transistor is turned on, electrons will be conducted from the source to the drain.
  • thin-film transistors according to the material of the semiconductor layer, they can be further classified into polysilicon thin-film transistors and amorphous-silicon thin-film transistors.
  • Polysilicon thin-film transistors have the advantage of higher carrier mobility. Unfortunately, they also have the disadvantage of larger leakage current.
  • amorphous-silicon thin-film transistors have lower carrier mobility. This factor leads to higher resistivity in amorphous-silicon thin-film transistors and thereby limiting the conductivity of the devices. Consequently, the turn-on current of amorphous thin-film transistors indirectly lead to inferior driving efficiency.
  • the present invention provides a novel thin-film transistor with high driving efficiency for improving the drawbacks as described above.
  • An objective of the present invention is to provide a thin-film transistor structure, which includes a third metal layer for improving the driving characteristics of thin-film transistors.
  • Another objective of the present invention is to provide a thin-film transistor structure, which includes a third metal layer for optimizing the circuit layout.
  • the present invention provides a thin-film transistor structure, which comprises a substrate, a first metal layer, a first buffer layer, a semiconductor layer, a second metal layer, a second buffer layer, and a third metal layer.
  • the first metal layer is disposed on the substrate.
  • the first buffer layer covers the substrate and the first metal layer.
  • the semiconductor layer is disposed on the first buffer layer.
  • the second metal layer is disposed on the semiconductor layer and includes a gap region.
  • the second buffer layer covers the second metal layer and the semiconductor layer.
  • the third metal layer is disposed on the buffer layer.
  • the present invention uses the first and third metal layers located above and under the semiconductor layer to form double gates. Thereby, the turn-on current of the thin-film transistor can be enhanced and thus improving the driving efficiency as well as optimizing the circuit layout.
  • FIG. 1B shows a structural schematic diagram according to the first embodiment of the present invention
  • FIG. 1B shows a top view according to the first embodiment of the present invention
  • FIGS. 2A to 2F show process flowcharts according to the first embodiment of the present invention
  • FIG. 3A shows a structural schematic diagram according to the second embodiment of the present invention
  • FIG. 3B shows a top view according to the second embodiment of the present invention.
  • FIG. 4A shows a structural schematic diagram according to the third embodiment of the present invention.
  • FIG. 4B shows a top view according to the third embodiment of the present invention.
  • the present invention provides a thin-film transistor structure for increasing the turn-on current and thereby achieving improving the driving efficiency as well as optimizing the circuit layout.
  • FIG. 1A shows a structural schematic diagram according to the first embodiment of the present invention.
  • the present embodiment provides a thin-film transistor structure 1 , which comprises a substrate 11 , a first metal layer 12 , a first buffer layer 13 , a semiconductor layer 14 , a second metal layer 15 , a second buffer layer 16 , and a third metal layer 17 .
  • the semiconductor layer 14 according to the present embodiment includes a channel region 141 .
  • the second metal layer 15 includes a gap region 151 .
  • the second buffer layer 16 includes at least a recess 171 there above.
  • FIG. 1B shows a top view according to the first embodiment of the present invention.
  • the figure illustrates the relationship between the second and third metal layers 15 , 17 .
  • the second metal layer 15 includes a plurality of parts acting as the source and drain of the thin-film transistor.
  • the region enclosed by the dotted line is the location of the third metal layer 17 corresponding to the gap region 151 of the second metal layer 15 .
  • the third metal layer 17 according to the present embodiment covers the gap region 151 completely.
  • FIGS. 2A to 2F show process flowcharts according to the first embodiment of the present invention.
  • the connection among the components according to the present embodiment is illustrated.
  • the first metal layer 12 is disposed on the substrate 11 and used as a gate of the thin-film transistor.
  • the first buffer layer 13 covers the substrate 11 and the first metal layer 12 .
  • the semiconductor layer 14 is disposed on the first buffer layer 13 .
  • the material of the semiconductor layer 14 can be, but not limited to, amorphous silicon. For example, it also can be polysilicon.
  • FIG. 1 shows amorphous silicon.
  • the second metal layer 15 which include a gap region 151 is disposed on the semiconductor layer 14 .
  • the gap region 151 divides the second metal layer 15 into two parts used as the source and the drain of the thin-film transistor, respectively.
  • the second buffer layer 16 covers the second metal layer 15 and the semiconductor layer 14 .
  • the third metal layer 17 is disposed on the second buffer layer 16 .
  • the width of the third metal layer 17 is greater than the width of the gap region 151 .
  • the material of the third metal layer 17 can be metal elements, metal compounds, or metal oxides.
  • the third metal layer 17 can act as another gate of the thin-film transistor.
  • the width of the first metal layer 12 according to the present embodiment is close to the width of the gap region 151 .
  • the width of the first metal layer 12 can be greater than, equal to, and less than the width of the gap region 151 .
  • the width of the first metal layer 12 is greater than the width of the gap region 151 .
  • the width of the channel region 141 according to the present embodiment can be greater than, equal to, or less than the width of the third metal layer 17 according to the design requirements for adjusting the characteristics of the thin-film transistor structure.
  • the thin-film transistor structure 1 uses the third metal layer 17 to be another gate different from the one using the first metal layer 12 .
  • the semiconductor layer 15 is controlled by the gates located above and under using the first and third metal layers 12 , 17 , respectively, and thus forming a double-gate structure.
  • the channel region 141 is controlled by the double gates and hence enhancing the switching speed and turn-on current of the device. Consequently, the turn-on current and the discharge rate of the overall thin-film transistor structure 1 are improved, leading to enhancement in the driving performance.
  • FIG. 3A shows a structural schematic diagram according to the second embodiment of the present invention.
  • the components and their connection according to the present embodiment are illustrated.
  • the difference between the present embodiment and the previous one is that, according to the present embodiment, the width of the third metal layer 17 is equal to that of the gap region 151 .
  • the detailed components and their connection are identical to those in the previous embodiment. Hence, the details will not be described again.
  • FIG. 3B shows a top view according to the second embodiment of the present invention.
  • the figure illustrates the relationship between the second and third metal layers 15 , 17 .
  • the second metal layer 15 includes a plurality of parts acting as the source and drain of the thin-film transistor.
  • the region enclosed by the dotted line is the location of the third metal layer 17 corresponding to the gap region 151 of the second metal layer 15 .
  • the width of the third metal layer 17 according to the present embodiment is greater than the width of the gap region 151 .
  • the width of the channel region 141 according to the present invention further represents the distance by which the electrons travel from any terminal of the second metal layer 15 to the opposing terminal.
  • the width of the channel region 141 will be the width of the gap region 151 plus the widths on the both terminals of the second metal layer 15 .
  • the width of the channel region 141 will be slightly greater than that of the gap region 151 .
  • the difference between the present embodiment and the previous one is that, according to the present embodiment, the third metal layer 17 corresponds to the channel region 141 and covers the second buffer layer 16 .
  • FIG. 4A shows a structural schematic diagram according to the third embodiment of the present invention. As shown in the figure, the components and their connection according to the present embodiment are illustrated. The difference between the present embodiment and the previous embodiments is that, according to the present embodiment, the width of the third metal layer 17 is less than that of the gap region 151 . The detailed components and their connection are identical to those in the previous embodiment. Hence, the details will not be described again.
  • FIG. 4B shows a top view according to the third embodiment of the present invention.
  • the figure illustrates the relationship between the second and third metal layers 15 , 17 .
  • the second metal layer 15 includes a plurality of parts acting as the source and drain of the thin-film transistor.
  • the region enclosed by the dotted line is the location of the third metal layer 17 corresponding to the gap region 151 of the second metal layer 15 .
  • the difference between the present embodiment and the previous embodiments is that, according to the present embodiment, the third metal layer 17 is disposed within the range covered by the width of the channel region 141 or the gap region 151 .
  • the present invention provides a thin-film transistor structure, which comprises a substrate, a first metal layer, a first buffer layer, a semiconductor layer, a second metal layer, a second buffer layer, and a third metal layer.
  • the first metal layer is disposed on the substrate.
  • the first buffer layer covers the substrate and the first metal layer.
  • the semiconductor layer is disposed on the first buffer layer.
  • the second metal layer is disposed on the semiconductor layer and includes a gap region.
  • the second buffer layer covers the second metal layer and the semiconductor layer.
  • the third metal layer is disposed on the buffer layer.
  • the present invention uses the first and third metal layers located above and under the semiconductor layer to form double gates for improving the driving efficiency of the thin-film transistor as well as optimizing the circuit layout.
  • the present invention conforms to the legal requirements owing to its novelty, non-obviousness, and utility.
  • the foregoing description is only embodiments of the present invention, not used to limit the scope and range of the present invention. Those equivalent changes or modifications made according to the shape, structure, feature, or spirit described in the claims of the present invention are included in the appended claims of the present invention.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
US14/932,215 2015-07-31 2015-11-04 Thin-film transistor structure Abandoned US20170033236A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW104124874 2015-07-31
TW104124874A TW201704831A (zh) 2015-07-31 2015-07-31 薄膜電晶體結構

Publications (1)

Publication Number Publication Date
US20170033236A1 true US20170033236A1 (en) 2017-02-02

Family

ID=57886130

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/932,215 Abandoned US20170033236A1 (en) 2015-07-31 2015-11-04 Thin-film transistor structure

Country Status (3)

Country Link
US (1) US20170033236A1 (zh)
CN (1) CN106409916A (zh)
TW (1) TW201704831A (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170207642A1 (en) * 2016-01-15 2017-07-20 Renesas Electronics America Inc. E-fuse/switch by back end of line (beol) process

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107946189B (zh) * 2017-11-22 2020-07-31 深圳市华星光电半导体显示技术有限公司 一种薄膜晶体管及其制备方法
US10777662B2 (en) 2017-11-22 2020-09-15 Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Thin film transistor and manufacturing method thereof
CN108163840B (zh) * 2017-12-27 2020-02-07 深圳市华星光电半导体显示技术有限公司 碳纳米管提纯方法、薄膜晶体管及制备方法
CN109560141B (zh) * 2018-12-13 2020-09-25 合肥鑫晟光电科技有限公司 薄膜晶体管、发光装置及其制造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007200936A (ja) * 2006-01-23 2007-08-09 Nec Corp 薄膜トランジスタ及びその製造方法並びに液晶表示装置
TWI295855B (en) * 2006-03-03 2008-04-11 Ind Tech Res Inst Double gate thin-film transistor and method for forming the same
TWI316760B (en) * 2006-05-03 2009-11-01 Ind Tech Res Inst Circuit structure with doubl-gate organic thin film transistors and application thereof
JP5931573B2 (ja) * 2011-05-13 2016-06-08 株式会社半導体エネルギー研究所 半導体装置の作製方法
CA2845768A1 (en) * 2011-06-24 2012-12-27 Sharp Kabushiki Kaisha Display device and method for manufacturing same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170207642A1 (en) * 2016-01-15 2017-07-20 Renesas Electronics America Inc. E-fuse/switch by back end of line (beol) process

Also Published As

Publication number Publication date
CN106409916A (zh) 2017-02-15
TW201704831A (zh) 2017-02-01

Similar Documents

Publication Publication Date Title
US20170033236A1 (en) Thin-film transistor structure
US9825140B2 (en) Metal oxide thin film transistor
US8679930B2 (en) Semiconductor structure and manufacturing method for the same
US20140225117A1 (en) Thin Film Transistor with Increased Doping Regions
US20140217398A1 (en) Thin-film transistor device and thin-film transistor display apparatus
US9515191B2 (en) Thin-film field effect transistor, driving method thereof, array substrate, display device, and electronic product
US20180240821A1 (en) Integration of silicon thin-film transistors and metal-oxide thin film transistors
US8125028B2 (en) Semiconductor devices for high power application
US20190198080A1 (en) Ferroelectric memory device and method of programming same
WO2014115305A1 (ja) 半導体装置
US20070051956A1 (en) Thin film transistor
US9762226B2 (en) Semiconductor device having control conductors
KR102192083B1 (ko) 높은 온/오프 전류비를 가진 박막 트랜지스터
CN105140298A (zh) 薄膜晶体管和阵列基板
US10224406B2 (en) Array substrate including vertical TFT, and manufacturing method thereof
US11508761B2 (en) Inverter circuit structure, gate driving circuit and display panel
US20070023836A1 (en) Semiconductor device
CN100373633C (zh) 不对称的薄膜晶体管结构
TWI556430B (zh) 非對稱閘極的穿隧式電晶體
US10679899B2 (en) Semiconductor device including monolithically integrated PMOS and NMOS transistors
US20190319134A1 (en) Thin film transistor array substrate, low temperature poly-silicon thin film transistor, and method for manufacturing low temperature poly-silicon thin film transistor
US11699375B1 (en) Semiconductor device and display driver IC using the same
TWI806183B (zh) 具有不連續通道區的鰭式電晶體
CN108365004A (zh) 一种tft基板及显示装置
CN107980177B (zh) 薄膜晶体管及具有薄膜晶体管的设备

Legal Events

Date Code Title Description
AS Assignment

Owner name: GIANTPLUS TECHNOLOGY CO., LTD., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CHOU, KAI-JU;WU, CHE-YAO;LAI, KU-HUANG;AND OTHERS;SIGNING DATES FROM 20110815 TO 20150825;REEL/FRAME:036960/0382

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION