CN106252235A - 低成本超结功率场效应管的制备方法 - Google Patents
低成本超结功率场效应管的制备方法 Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
本发明实施例提供一种低成本超结功率场效应管的制备方法，该制备方法通过以下步骤实现：步骤一：在N+衬底上生长N‑外延层;步骤二：通过body光刻版注入体区，然后进行推阱;步骤三：深沟槽的刻蚀和p型EPI的回填，并进行CMP工艺将沟槽外的p型EPI去掉，形成p‑pillar;步骤四：进行栅氧、多晶硅栅极的生长和回刻;步骤五：Nsource注入并推阱；步骤六：进行层间介质（ILD）的淀积；步骤七：电极光刻，孔注；步骤八：源极金属的淀积和光刻，形成器件的最终结构。本发明省掉了有源区这块光刻版，不长厚场氧，同时器件击穿特性不受影响，因此降低了超结功率场效应管的制造成本。
Description
技术领域
本发明属于超结功率场效应管制造技术领域，具体涉及一种低成本超结功率场效应管的制备方法。
背景技术
前高压超结产品主要有两种工艺技术路径：1.以Infineon和ST为代表的多次外延和注入技术的技术。2.以Toshiba和华虹宏力为代表的沟槽刻蚀和回填技术。两种技术基本上都要长1-2um的热场氧，然后光刻有源区，进行后续的器件制备工艺；现有的超结技术制造工艺，都有厚场氧工艺，也都会用到有源区光刻版，制造工艺相对昂贵。
发明内容
有鉴于此，本发明的主要目的在于提供一种低成本超结功率场效应管的制备方法。
为达到上述目的，本发明的技术方案是这样实现的：
本发明实施例提供一种低成本超结功率场效应管的制备方法，该制备方法通过以下步骤实现：
步骤一：在N+衬底上生长N-外延层;
步骤二：通过body光刻版注入体区，然后进行推阱;
步骤三：深沟槽的刻蚀和p型EPI的回填，并进行CMP工艺将沟槽外的p型EPI去掉，形成p-pillar;
步骤四：进行栅氧、多晶硅栅极的生长和回刻;
步骤五：Nsource注入并推阱；
步骤六：进行层间介质（ILD）的淀积；
步骤七：电极光刻，孔注；
步骤八：源极金属的淀积和光刻，形成器件的最终结构。
上述方案中，所述步骤五中Nsource采用As或P注入并推阱。
上述方案中，所述步骤六中层间介质的厚度为1-3um。
与现有技术相比，本发明的有益效果：
本发明省掉了有源区这块光刻版，不长厚场氧，同时器件击穿特性不受影响，因此降低了超结功率场效应管的制造成本。
附图说明
图1为本发明步骤一的示意图；
图2为本发明步骤二的示意图；
图3为本发明步骤三的示意图；
图4为本发明步骤四的示意图；
图5为本发明步骤五的示意图；
图6为本发明步骤六的示意图；
图7为本发明步骤七的示意图；
图8为本发明步骤八的示意图；
图9为场氧和有源区光刻版的情况下和本发明情况下的器件终端的击穿电压情况图。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
本发明实施例提供一种低成本超结功率场效应管的制备方法，该制备方法通过以下步骤实现：
步骤一：在N+衬底上生长N-外延层，如图1所示;
步骤二：通过body光刻版注入体区，然后进行推阱，如图2所示;
步骤三：深沟槽的刻蚀和p型EPI的回填，并进行CMP工艺将沟槽外的p型EPI去掉，形成p-pillar，如图3所示;
步骤四：省去场氧过程，直接进行栅氧、多晶硅栅极的生长和回刻，如图4所示，这一步省去了长时间的场氧热过程，同时也节省了有源区光刻版;
步骤五：Nsource注入并推阱，如图5所示；
具体地，步骤五中Nsource采用As或P注入并推阱。
步骤六：进行层间介质（ILD）的淀积，如图6所示；
具体地，所述步骤六中层间介质的厚度为1-3um，足够厚的ILD是保证器件在省去场氧过程后，击穿电压不变的关键。
步骤七：电极光刻，孔注，如图7所示；
步骤八：源极金属的淀积和光刻，形成器件的最终结构，如图8所示。
通过器件仿真（Sentaurus），对比了在其他工艺条件基本相同的情况下，有场氧和有源区光刻版的情况下和本发明情况下，器件终端的击穿电压，发现两种情况的击穿电压基本相同，如图9所示。
以上所述，仅为本发明的较佳实施例而已，并非用于限定本发明的保护范围。
Claims (3)
1.一种低成本超结功率场效应管的制备方法，其特征在于，该制备方法通过以下步骤实现：
步骤一：在N+衬底上生长N-外延层;
步骤二：通过body光刻版注入体区，然后进行推阱;
步骤三：深沟槽的刻蚀和p型EPI的回填，并进行CMP工艺将沟槽外的p型EPI去掉，形成p-pillar;
步骤四：进行栅氧、多晶硅栅极的生长和回刻;
步骤五：Nsource注入并推阱；
步骤六：进行层间介质（ILD）的淀积；
步骤七：电极光刻，孔注；
步骤八：源极金属的淀积和光刻，形成器件的最终结构。
2.根据权利要求1所述的低成本超结功率场效应管的制备方法，其特征在于：所述步骤五中Nsource采用As或P注入并推阱。
3.根据权利要求1或2所述的低成本超结功率场效应管的制备方法，其特征在于：所述步骤六中层间介质的厚度为1-3um。
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050133859A1 (en) * | 2003-12-22 | 2005-06-23 | Denso Corporation | Semiconductor device and design-aiding program |
| CN103779415A (zh) * | 2014-01-20 | 2014-05-07 | 张家港凯思半导体有限公司 | 平面型功率mos器件及其制造方法 |
| CN104779298A (zh) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | 一种超结mosfet终端结构及其制作方法 |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050133859A1 (en) * | 2003-12-22 | 2005-06-23 | Denso Corporation | Semiconductor device and design-aiding program |
| CN103779415A (zh) * | 2014-01-20 | 2014-05-07 | 张家港凯思半导体有限公司 | 平面型功率mos器件及其制造方法 |
| CN104779298A (zh) * | 2015-04-24 | 2015-07-15 | 无锡同方微电子有限公司 | 一种超结mosfet终端结构及其制作方法 |
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