(3) summary of the invention:
A kind of tap water supply pipe network Automatic meter reading system, is used for recording user's water consumption.This is
System comprises many numbers of elements according to the water meter of output and controller and main controller, and measurement data is led to by each water meter
Cross electric lines of force half wave communication and send controller to, user's water usage data that each controller will gather
Sending main controller to also by electric lines of force half wave communication, main controller is periodically by user's water usage data
Collect to tap water supply administrative center through GSM net.Data output water meter such as: pulse is defeated
Going out water meter, ultrasonic water meter, electromagnetic flowmeter etc., every water meter is equipped with toggle switch, all
Being provided with numbering, the timing of each controller is scanned registration to each water meter, finds fault or by people
For moving apart system, report to the police by this accident record and to administrative center.Each water meter and controller thereof and
Main controller, is respectively mounted cycle discriminator circuit in its device, protect for producing the lock in time of system
Holding system acting consistent, in its telecommunication circuit, each one communications electronics of installation switchs, opens simultaneously
Close and drive module.Said apparatus is all connected on same electric power netting twine and arranges main switch, opens always
Sending into system through diode behind pass, system is in half wave communication half-wave power supply state.During communication,
I.e. connect communications electronics switch, otherwise, main controller sends switching to each water meter and controller thereof and refers to
Order, turns off communications electronics switch.
Communication is by controlling lock in time to keep keeping strokes, main controller and each water meter, control
The switch drive module of the communications electronics switch of device, is through resistance blood pressure lowering, dividing potential drop from electric power netting twine
It is followed by the CLK end of d type flip flop, the external interrupt mouth (INT0 of the Q termination single-chip microcomputer of d type flip flop
Or INT1), this external interrupt mouth is set to level triggers.The D end ground connection of d type flip flop, its S
End connects with the I/O mouth of single-chip microcomputer, and original state S end puts 1.When the positive square wave of CLK end is believed
Number arrive time, its rising edge makes d type flip flop set to 0, external interrupt mouth low level produce interrupt,
First making S end set to 0 in interrupt service routine, to make d type flip flop put 1 i.e. Q end be 1 to close interruption,
Then communicating, communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode,
And carry out signal condition, before sign off, S end puts 1 communication making out next cycle of interrupt latency,
So go round and begin again and realize half wave communication.
System is provided with SMS R-T unit, utilizes GSM network, to receive and dispatch note side
Formula communicates, and the SMS messaging service of current GSM remains the one that domestic popularity rate is the highest
The SMS of short message service GSM itself possesses data transport functions, and the transmission of a message is just constituted
Once communicating, the transmission of message is by the SMS service center (SMSC) being in outside GSM
Relay, the SMS service SMS of GSM it need not dial and can set up connection, user is wanting
The information sent out is sent to short message service center plus stay of two nights data, completes through short message service center
The final stay of two nights it is then forwarded to after storage.So information will not be lost when the no start of GSM terminal.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three and screens some realization to cycle
The identification decision of signal, recycling the cycle time set up lock in time, it is achieved each water meter in system
And controller and the synchronous operation of main controller.
Cycle discriminator circuit structural representation such as Fig. 2 institute of each water meter and controller and main controller
Show, be made up of three voltage comparators using hysteresis loop comparator, in each voltage comparator all
Comprising filter circuit, the reference voltage of its voltage comparator is provided by mu balanced circuit.System is arranged
Clock timer and synchrotimer.If be detected that adjacent two cycle signals are very,
Then take out the clock timer timing time between these two adjacent cycle signal zero passages, sequentially
It is stored in cycle time memory cell, when this cycle time memory cell can deposit 100 cycles
Between, often it is stored in a cycle time when being filled with, the most first removes the cycle time being stored at first,
And calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value to differentiate week to be identified
Ripple signal, to reduce the impact of power network frequency fluctuation, uses three to screen point simultaneously and reduces by mistake
Sentence probability.
Three comparators are respectively used to three and screen point, i.e. screen point 0, examination point 1, screen point 2,
As shown in Figure 1.At the cycle zero passage of cycle positive half cycle ascent stage, i.e. screen point 0 and electricity is set
Press through zero comparator, owing to power network cycle negative half period is rectified diode-isolated, in order to improve
Accuracy of detection, at the signal input part series diode again isolation negative half period of voltage zero-crossing comparator,
Its reference voltage brings up to 10mv to 100mv from zero, depending on the offset voltage of comparator, and should
Reference voltage may utilize diode drop and obtains through electric resistance partial pressure.Remaining two comparator sets respectively
Put in the cycle positive half cycle ascent stage, the examination point 1 and 50% at 35% to 50% place of crest voltage
Examination point 2 at 70%.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and opens
Beginning timing, when cycle voltage zero-cross, is arranged on voltage zero-crossing comparator V0 screening point 0
Output voltage upset, its voltage trailing edge produce interrupt, record its zero crossing break period
Th0 also closes interruption;Hereafter, voltage comparator V1 defeated at point 1 is screened in single-chip microcomputer scanning
Going out voltage, when week, wave voltage reached the threshold voltage of V1, output voltage turns over from high to low
Turning, scanning records its flip-flop transition of Th1;Voltage comparator at point 2 screened in same scanning record
V2 output voltage Th2 flip-flop transition.Defeated by Th0 and voltage zero-crossing comparator V0
Go out voltage setting value Ts0 flip-flop transition to make comparisons;The output of Th1 and voltage comparator V1
The output voltage of voltage setting value Ts1 flip-flop transition and Th2 and voltage comparator V2 turns over
Turn time setting value Ts2 to make comparisons respectively, if in the range of allowable error, then detect
This discriminator signal is true, is otherwise false.Above-mentioned judge that discriminator signal, as true time, calculates this week
Clock meter between ripple signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Time device timing time Tzu, it is made comparisons with meansigma methods Tz of cycle time, if be less than
Set cycle time error Tzv then cycle signal as true, at this moment preserve Tzu and take 20ms with
Synchrotimer timing time is added, and the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing is to 16ms to 18.5ms
Between open interruption, clock timer timing to 25ms to 27ms when opening break period setting value Tk
Between pass break period setting value Tn time close interrupt.
After system boot, clock timer starts timing, when first all wave voltage mistake being detected
When zero, it is arranged on the output voltage upset of voltage zero-crossing comparator V0 screening point 0, from
And producing interruption, the time T0 taking out cycle voltage over zero preserves, and is reset by clock timer
And start timing, at this moment cycle time voltage crosses zero Th0 is 0, and single-chip microcomputer is as stated above simultaneously
Scan and judge discriminator signal.Due to detection is first cycle, and clock timer is in week
Starting timing during wave voltage zero passage, the value of its Th0, Th1 and Th2 must add the cycle time
20ms deducts out the difference of break period setting value Tk, if three discriminator signals are true, takes
The time T0 of the cycle voltage over zero gone out is stored in synchrotimer as initial time, next
Secondary i.e. for the first time open the break period and take Tk.Being otherwise fictitious time, now the clock timer time must add
Upper T0, continues detection.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving inspection
Survey the cycle time, therefore the clock timer timing time between twice cycle signal zero passage be with
The cycle time, 20ms made comparisons, it is determined that cycle signal is true time, then be to take 20ms to subtract Th0
Difference be added with synchrotimer timing time, preserve the standard cycle time 20 i.e. for the first time
Ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all the most every time
Restart timing after being reset by clock timer when opening interruption, and be will when opening interruption
The standard cycle time counts in synchrotimer, and clock timer of having no progeny in opening resets, and otherwise judges
Cycle signal is fictitious time, and now the clock timer time must continue by upper plus T1=T0+Tk
Method of stating detects first cycle again.After first cycle signal of detection is very, recover with
Upper described cycle signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, open the break period all exists next time
After this opens the break period, when meansigma methods Tz of time delay cycle time, open interruption, and in opening
Have no progeny time delay Tns time close interrupt, arrange pass the break period be when cycle signal screen point 0 time
Do not produce interruption, at this moment must start to sweep more than the setting time point of Ts0 allowable error scope
Retouch, and when scanning is screened point 1 and screens point 2, voltage comparator output voltage does not produce
Upset, is all closing the interruption of break period Tns pass and is stopping scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all that timing is opened to Tks
Interrupt, and restart timing after clearing, close during timing to Tns and interrupt, so that synchrometer
Time the device time corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and this cycle judges
Time, discriminator signal is false, or the cycle time detected compares with meansigma methods Tz of cycle time
Exceed setting cycle time error Tzv, or clock timer timing is to closing break period setting value
During Tns, voltage zero-crossing comparator V0 output voltage does not overturns, and does not produce interruption, then
Close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores,
Open the break period is to open the break period in last time to open interruption, clock timer after Tz next time
Have no progeny in opening and reset and timing, close during timing to Tns and interrupt, judge that cycle is believed the most every time
Number true and false, though if false or this detection discriminator signal is true last time is false, then take N, by N
Restore in memorizer after+1.
When detecting that cycle signal is true time, then take out N in memorizer and preserve, and by memorizer
N zero setting, and recover to use setting value Tks, the value at this moment taking (N+1) × 20ms is added on same
In step timer.
The system synchronization time is the time of synchrotimer, adds current just at the clock meter of timing
Time device time.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by exporting with voltage comparator
Voltage setting value Ts0 flip-flop transition, Ts1, Ts2 make comparisons and see the most overproof, judge to screen
The point signal true and false, can select: Th0, Th1, Th2 are this cycle discriminator signal of true time and are
Very, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true
Time, this cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, owing to being
In system, each water meter and controller and main controller, its Tz value detected and N value thereof may be different, this
Time, power network frequency cumulative error, being likely to result in the synchrotimer time cannot be by detecting
Corrected during true cycle signal, when detecting that cycle signal is true time, at this moment used clock
The accumulative clocking value of timer is directly added in synchrotimer, during to reduce system asynchronous
Between, accumulative clocking value is N × Tz+20ms.In the case of power network normal operation, N is much smaller than
25。
The cycle time error Tzv allowed and the flip-flop transition of voltage comparator output voltage set
Value, is taken its meansigma methods by test assessment and obtains.
(5) detailed description of the invention:
Fig. 3 is the circuit structure block diagram of a kind of tap water supply pipe network Automatic meter reading system, including:
Main controller 10, communications electronics switch 11, switch drive module 12, mobile phone are short
Letter R-T unit 13, SIM 14, controller 15, cycle discriminator circuit
16, water meter 17.Wherein communications electronics switch 11, switch drive module 12,
In cycle discriminator circuit 16 and Fig. 2, single-chip microcomputer U0 is included in water meter respectively
17, in controller 15 and main controller 10.Wherein communications electronics switch 11
Use bidirectional triode thyristor as switch.
Fig. 2 is the structural representation of cycle discriminator circuit 16, by: input circuit S0,
Voltage zero-cross detection module V0, voltage comparator V1 and voltage comparator V2 structure
Become.Single-chip microcomputer U0 refers in water meter 17, controller 15 and main controller 10
Single-chip microcomputer.Input circuit S0 is for passing through resistance and diode by mains AC voltage
Dividing potential drop, be converted to the input voltage that voltage comparator is the most stable.Single-chip microcomputer U0 adopts
With 89C55WD, voltage zero-cross detection module V0, voltage comparator V1, voltage
Comparator V2 all uses special voltage comparator LM339, and its reference voltage is to use surely
The mu balanced circuit of pressure pipe carrys out the threshold voltage of burning voltage comparator.
When mains AC voltage cycle signal zero passage, voltage zero-cross detection module V0's is defeated
Going out voltage jump, single-chip microcomputer U0 produces interruption, records break period, simultaneously single-chip microcomputer
U0 is additionally operable to the output electricity of scanning voltage comparator V1 and voltage comparator V2
Pressure, when output voltage saltus step record bound-time, be used for judging power network cycle signal thus
Produce lock in time.
In SMS R-T unit, single chip computer89C51 realizes string by I2C bus with main controller
Row communication, this single chip computer89C51 is also by serial line interface integrated circuit MAX232 and gsm module
TC35i connection carries out data exchange, and gsm module chip TC35i is RS232 data port, supports
AT Command Set, wherein contains the control to SMS, and single chip computer89C51 is by gsm module
Send a series of AT instruction, complete the initialization to gsm module and receiving short message.The receipts of SMS
Sending out and use TEXT pattern, TEXT pattern is a kind of structural models based on ASCII character.