CN105990431A - 晶体管、集成电路及其制造方法 - Google Patents
晶体管、集成电路及其制造方法 Download PDFInfo
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- CN105990431A CN105990431A CN201510093042.9A CN201510093042A CN105990431A CN 105990431 A CN105990431 A CN 105990431A CN 201510093042 A CN201510093042 A CN 201510093042A CN 105990431 A CN105990431 A CN 105990431A
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- layer
- type transistor
- silicide
- drain electrode
- metal
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Classifications
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
本发明提供了晶体管、集成电路和制造集成电路的方法。在各个实施例中,晶体管包括源电极、至少一个半导体沟道、栅电极、漏电极和漏极焊盘。源电极设置在衬底中。半导体沟道基本垂直于源电极延伸。栅电极环绕半导体沟道。漏电极设置在半导体沟道的顶部上。漏极焊盘设置在漏电极上,其中,漏极焊盘包括多个导电层。
Description
技术领域
本发明总体涉及集成电路,更具体地,涉及具有垂直结构的晶体管、具有垂直结构的晶体管的集成电路以及它们的制造方法。
背景技术
随着集成电路的集成度的增大,做了许多努力来在有限的衬底区域内集成更多的器件(诸如,晶体管)。为了减小被一个晶体管所占用的衬底面积,已经提出了在衬底上设置具有垂直半导体沟道的各种垂直晶体管结构。
纳米线场效应晶体管(FET)是这些垂直晶体管结构中的一种。在纳米线FET中,信号电流流过设置在纳米FET的源电极和漏电极之间的多条垂直纳米线,并且多条垂直纳米线是源电极和漏电极之间的垂直半导体沟道。通过垂直栅电极(环绕多条垂直纳米线中的每一条)上的电压控制垂直半导体沟道。因此,纳米线FET也被称为垂直围栅(VGAA)场效应晶体管。在提出的各种垂直晶体管结构中,纳米线FET引起了更多的注意,并且被认为是增加下代集成电路的集成度的极具潜力的候选晶体管。
因此,提出了具有纳米线FET的各种集成电路。然而,具有纳米线FET的集成电路的结构设计的技术进步需要克服各种困难,因为在提供性能更好的集成电路的要求方面变得更加具有挑战性。因此,继续寻求集成电路及其制造方法的改进。
发明内容
根据本发明的一个方面,提供了一种晶体管,包括:源电极,设置在衬底中;至少一个半导体沟道,基本垂直于所述源电极而延伸;栅电极,环绕所述半导体沟道;漏电极,设置在所述半导体沟道的顶部上;以及漏极焊盘,设置在所述漏电极上,其中,所述漏极焊盘包括多个导电层。
优选地,所述漏极焊盘包括:硅化物层,与所述漏电极直接接触;覆盖层,设置在所述硅化物层上;以及接触金属层,设置在所述覆盖层上。
优选地,所述硅化物层包括硅化钛、硅化镍、硅化钴或它们的组合。
优选地,所述覆盖层包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。
优选地,所述接触金属层包括钨、铝、钴或它们的组合。
优选地,所述漏极焊盘还包括设置在所述硅化物层和所述覆盖层之间的金属层。
优选地,所述金属层包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。
优选地,该晶体管还包括:钝化层,封装所述漏极焊盘。
根据本发明的另一方面,提供了一种集成电路,包括:至少一个n型晶体管,设置在衬底上;至少一个p型晶体管,设置在所述衬底上并且与所述n型晶体管相邻;层间介电层,覆盖所述n型晶体管、所述p型晶体管和所述衬底;以及多个金属接触件,设置在所述层间介电层中,所述金属接触件分别与所述n型晶体管和所述p型晶体管的所述源电极、所述栅电极和所述漏极焊盘直接接触,其中,所述n型晶体管和所述p型晶体管分别包括:源电极,设置在所述衬底中;至少一个半导体沟道,基本垂直于所述源电极而延伸;栅电极,环绕所述半导体沟道;漏电极,设置在所述半导体沟道的顶部上;和漏极焊盘,设置在所述漏电极上,所述漏极焊盘包括多个导电层。
优选地,所述漏极焊盘包括:硅化物层,与所述漏电极直接接触;覆盖层,设置在所述硅化物层上;以及接触金属层,设置在所述覆盖层上。
优选地,所述硅化物层包括硅化钛、硅化镍、硅化钴或它们的组合。
优选地,所述覆盖层包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。
优选地,所述接触金属层包括钨、铝、钴或它们的组合。
优选地,所述n型晶体管和所述p型晶体管中每一个均还包括:钝化层,封装所述漏极焊盘。
优选地,该集成电路还包括:金属层,设置在所述硅化物层和所述覆盖层之间。
优选地,所述金属层包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。
根据本发明的又一方面,提供了一种方法,包括:接收具有至少一个n型晶体管和至少一个p型晶体管的衬底,其中,所述n型晶体管和所述p型晶体管中的每一个均包括设置在所述衬底中的源电极、基本垂直于所述源电极而延伸的至少一个半导体沟道、环绕所述半导体沟道的栅电极,以及设置在所述半导体沟道的顶部上的漏电极;形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的覆盖层和硅化物层,其中,所述覆盖层形成在所述硅化物层上;形成覆盖所述覆盖层的金属层;形成覆盖所述金属层的第一钝化层;形成穿过所述硅化物层、所述覆盖层、所述金属层和所述第一钝化层的开口以产生分别设置在所述n型晶体管和所述p型晶体管的所述漏电极上的漏极焊盘;形成覆盖所述漏极焊盘的侧壁的第二钝化层;形成第一氧化物层以填充所述漏极焊盘的侧壁之间的间隙并覆盖所述第一钝化层;抛光所述第一氧化物层,其中,所述抛光停止于所述第一钝化层处;形成覆盖所述n型晶体管、所述p型晶体管和所述衬底的层间介电层;以及形成设置在所述层间介电层中的多个金属接触件,并且所述金属接触件分别与所述n型晶体管和所述p型晶体管的所述源电极、所述栅电极和所述漏极焊盘直接接触。
优选地,形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的所述覆盖层和所述硅化物层包括:沉积覆盖所述n型晶体管和所述p型晶体管的所述漏电极的非晶硅层;沉积覆盖所述非晶硅层的第一金属层;对所述非晶硅层和所述第一金属层进行退火以将所述非晶硅层转化为所述硅化物层;以及在所述第一金属层上沉积覆盖层。
优选地,所述第一金属层也被转化为所述硅化物层。
优选地,形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的所述覆盖层和所述硅化物层包括:沉积覆盖所述n型晶体管和所述p型晶体管的所述漏电极的第一金属层;对所述第一金属层以及所述n型晶体管和所述p型晶体管的所述漏电极进行退火以将所述漏电极的一部分转化为所述硅化物层;以及在所述第一金属层上沉积覆盖层。
附图说明
当阅读附图时,根据以下详细的描述来更好地理解本发明的各个方面。注意,根据工业的标准实践,各个部件没有按比例绘制。实际上,为了讨论的清楚,可以任意地增加或减小各个部件的尺寸。
图1是根据本发明的各个实施例的集成电路的至少一部分的示意图。
图2是示出了根据本发明的各个实施例的制造集成电路的方法的流程图。
图3是根据本发明的各个实施例的处于制造集成电路的方法的中间阶段的衬底的至少一部分的示意图。
图4根据本发明的各个实施例的图3所示衬底在制造集成电路的方法的后续阶段的示意图。
图5根据本发明的各个实施例的图4所示衬底在制造集成电路的方法的后续阶段的示意图。
图6根据本发明的各个实施例的图5所示衬底在制造集成电路的方法的后续阶段的示意图。
图7根据本发明的各个实施例的图6所示衬底在制造集成电路的方法的后续阶段的示意图。
图8根据本发明的各个实施例的图7所示衬底在制造集成电路的方法的后续阶段的示意图。
图9根据本发明的各个实施例的图8所示衬底在制造集成电路的方法的后续阶段的示意图。
图10根据本发明的各个实施例的图9所示衬底在制造集成电路的方法的后续阶段的示意图。
图11根据本发明的各个实施例的图10所示衬底在制造集成电路的方法的后续阶段的示意图。
图12根据本发明的各个实施例的图11所示衬底在制造集成电路的方法的后续阶段的示意图。
图13根据本发明的各个实施例的图12所示衬底在制造集成电路的方法的后续阶段的示意图。
图14根据本发明的各个实施例的图13所示衬底在制造集成电路的方法的后续阶段的示意图。
图15是根据本发明各个实施例的集成电路的至少一部分的示意图。
具体实施方式
以下公开提供了许多不同的用于实施本发明主题的不同特征的实施例或实例。以下描述部件或配置的具体实例以简化本发明。当然,这些仅仅是实例而不用于限制。例如,在以下的描述中,在第二部件上方或之上形成第一部件可以包括第一部件和第二部件被形成为直接接触的实施例,并且也可以包括可以在第一部件和第二部件形成附件部件使得第一部件和第二部分没有直接接触的实施例。此外,本发明可以在各个实例中重复参考标号和/或字母。这些重复是为了简化和清楚,其本身并不表示所讨论的各个实施例和/或结构之间的关系。
本文所使用的单数形式“一个”和“该”包括复数个所指物,除非文中另有明确说明。因此,例如对衬垫层的引用包括具有两个或多个这种衬垫层的实施例,除非文中另有明确说明。在整个说明书中对“一个实施例”或“实施例”的引用是指结合实施例描述的特定部件、结构或特性包括在本发明的至少一个实施例中。因此,在整个说明书的各个地方出现的语句“在一个实施例中”或“在实施例中”不是必须均表示相同的实施例。此外,在一个或多个实施例中,可以以任何适当的方式组合特定的特征、结构或特性。应该理解,以下附图没有按比例绘制;而是,这些附图只是为了说明。
如前所述,对具有纳米线FET的集成电路的要求变得更具有挑战性。例如,不断要求改进具有纳米线FET的集成电路的电阻(诸如,漏极侧的接触电阻率和互连薄膜电阻)。此外,制造具有纳米线FET的集成电路的更好的工艺灵活性(诸如,在制造纳米线FET期间控制漏极消耗(drainconsumption)和硅化)对于制造具有纳米线FET的集成电路来说也是尤为关键的。关于这点,根据本发明的各种实施例提供了晶体管、集成电路和制造集成电路的方法。
图1是根据本发明的各个实施例的集成电路10的至少一部分的示意图。集成电路10包括至少一个n型晶体管100、至少一个p型晶体管200、层间介电层300以及多个金属接触件400。n型晶体管100设置在衬底15上。p型晶体管200设置在衬底15上,并且p型晶体管200与n型晶体管100相邻。n型晶体管100和p型晶体管200是诸如形成在衬底15上的纳米线FET的垂直金属氧化物半导体场效应晶体管(MOSFET),并且浅沟槽隔离(STI)116设置在n型晶体管100和p型晶体管200之间用于隔离。n型晶体管100和p型晶体管200分别包括源电极、至少一个半导体沟道、栅电极、漏电极和漏极焊盘。如图1所示,n型晶体管100包括源电极110、至少一个半导体沟道120、栅电极130、漏电极140和漏极焊盘150。源电极110设置在衬底15中。例如,如图1所示,源电极110可包括形成在衬底15中的掺杂区域112以及形成在掺杂区域112上且作为掺杂区域112的电阻(ohmic)接触件的硅化物114。作为电阻接触件的硅化物114通常通过在形成在衬底15中的掺杂区域112上沉积过渡金属以及通过退火形成硅化物来形成。作为电阻接触件的硅化物114还可通过直接溅射化合物来沉积或通过离子注入过渡金属然后退火来沉积。
半导体沟道120基本垂直于源电极110延伸。例如,如图1所示,半导体沟道120可包括外延层122、半导体柱124和隔离层126。外延层122形成在掺杂区域112上。半导体柱124形成在外延层122上并被隔离层126所环绕。栅电极130环绕半导体沟道120。例如,如图1所示,栅电极130可包括第一金属栅极132、第二金属栅极134和栅极介电层136。半导体沟道120被栅极介电层136所环绕。栅极介电层136被第二金属栅极134所环绕。用于栅极介电层136的适当材料的实例包括但不限于热生长的二氧化硅(SiO2)、沉积的SiO2或者通过溅射沉积或原子层沉积所沉积的高k介电质(诸如,氧化铪(HfO2))。如本文所使用的,术语“高k介电质”是指介电常数k大于约4.0(大于SiO2的k值)的介电质。栅极介电层136还可以包括高k介电材料。高k介电材料可定义为介电常数大于热氧化硅的介电常数约3.9的介电材料。例如,高k介电材料可包括氧化铪(HfO2),其介电常数在约18至约40的范围内。可选地,高k介电材料可包括ZrO2、Y2O3、La2O5、Gd2O5、TiO2、Ta2O5、HfErO、HfLaO、HfYO、HfGdO、HfAlO、HfZrO、HfTiO、HfTaO、SrTiO中的一种或它们的组合。第二金属栅极134被第一金属栅极132所环绕。漏电极140设置在半导体沟道120的顶部上。例如,漏电极140可以是形成在半导体沟道120的顶部上的外延层。
漏极焊盘150设置在漏电极140上。如图1所示,漏极焊盘150聚集对应于半导体沟道120的漏电极140,并且漏极焊盘150可通过一个金属接触件400电连接。应该注意,如图1所示,漏极焊盘150包括多个导电层。换句话说,漏极焊盘150不是单层物质(例如,单个硅化钛(TiSi)膜),而是如图1所示的多个导电层。因此,可以通过选择合适的材料和多个导电层中的材料的适当厚度来大大减小对应于n型晶体管100的漏极侧的接触电阻率和互连薄膜电阻。如图1所示,在本发明的各个实施例中,漏极焊盘150包括硅化物层152、覆盖层156和接触金属层158。硅化物层152与漏电极140直接接触。覆盖层156设置在硅化物层152上。接触金属层158设置在覆盖层156上。如前所述,硅化物层152可通过沉积过渡金属并对沉积的过渡金属进行退火来形成。此外,硅化物层152还可以通过直接溅射化合物来沉积或者通过直接溅射过渡金属然后进行退火来沉积。在本发明的各个实施例中,硅化物层152包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi)或它们的组合。设置在硅化物层152上的覆盖层156可保护硅化物层152并且还被认为是组合硅化物层152和接触金属层158的粘合层。覆盖层156可以是任何适当的导电材料。在本发明的各个实施例中,覆盖层156包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。接触金属层158是金属层,因此具有比硅化物层152的电阻小的电阻。在本发明的各个实施例中,接触金属层158包括钨(W)、铝(Al)、钴(Co)或它们的组合。如前所述,如图1所示,漏极焊盘150不是单层物质(诸如,单层硅化钛(TiSi)膜),而是多个导电层。因此,可以通过引入电阻低于硅化物152的电阻的接触金属层158来大大减小对应于n型晶体管100的漏极侧的接触电阻率和互连薄膜电阻。此外,在本发明的各个实施例中,漏极焊盘150还包括设置在硅化物层152和覆盖层156之间的金属层154。金属层154可以是任何适当的金属材料。在本发明的各个实施例中,金属层154包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。如图1所示,在本发明的各个实施例中,n型晶体管100还包括钝化层160。钝化层160封装漏极焊盘150。在本发明的各个实施例中,钝化层160包括氮化硅。因此,在随后的制造工艺期间可以保护漏极焊盘150,并且可以进一步提高n型晶体管100的可靠性。
还如图1所示,p型晶体管200包括源电极210、至少一个半导体沟道220、栅电极230、漏电极240和漏极焊盘250。源电极210也设置在衬底15中。如图1所示,源电极210可包括形成在衬底15中的掺杂区域212以及形成在掺杂区域212上作为掺杂区域212的电阻接触件的硅化物214。作为电阻接触件的硅化物214通常通过在形成在衬底15中的掺杂区域212上沉积过渡金属然后通过退火形成硅化物来形成。硅化物214也可以通过直接溅射化合物来沉积或通过离子注入过渡金属然后进行退火来沉积。半导体沟道220基本垂直于源电极210延伸。例如,如图1所示,半导体沟道220可包括外延层222、半导体柱224和隔离层226。外延层222形成在掺杂区域212上。半导体柱224形成在外延层222上并被隔离层226所环绕。栅电极230环绕半导体沟道220。例如,如图1所示,栅电极230可包括金属栅极232和栅极介电层236。半导体沟道220被栅极介电层236所环绕。栅极介电层236被金属栅极232所环绕。漏电极240设置在半导体沟道220的顶部上。例如,漏电极240可以是形成在半导体沟道220的顶部上的外延层。漏极焊盘250设置在漏电极240上。如图1所示,漏极焊盘250与对应于半导体沟道220的漏电极240接触,并且漏极焊盘250可通过一个金属接触件400电连接。如图1所示,漏极焊盘250包括多个导电层。换句话说,如图1所示,漏极焊盘250不是单层物质(例如,单层硅化钛(TiSi)膜),而是多个导电层。因此,可以通过选择适当的材料和多个导电层中的材料的适当厚度来大大减小对应于p型晶体管200的漏极侧的接触电阻率和互连薄膜电阻。如图1所示,在本发明的各个实施例中,漏极焊盘250包括硅化物层252、覆盖层256和接触金属层258。硅化物层252与漏电极240直接接触。覆盖层256设置在硅化物层252上。接触金属层258设置在覆盖层256上。如前所述,硅化物层252可通过沉积过渡金属并对沉积的过渡金属进行退火来形成。此外,硅化物层252还可以通过直接溅射化合物来沉积或者通过直接溅射过渡金属然后进行退火来沉积。在本发明的各个实施例中,硅化物层252包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi)或它们的组合。设置在硅化物层252上的覆盖层256可保护硅化物层252并且还被认为是组合硅化物层252和接触金属层258的粘合层。覆盖层256可以是任何适当的导电材料。在本发明的各个实施例中,覆盖层256包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。接触金属层258是金属层,因此其具有比硅化物层252的电阻小的电阻。在本发明的各个实施例中,接触金属层258包括钨(W)、铝(Al)、钴(Co)或它们的组合。如前所述,如图1所示,漏极焊盘250不是单层物质(诸如,单层硅化钛(TiSi)膜),而是多个导电层。因此,可以通过引入电阻低于硅化物252的电阻的接触金属层258来大大减小对应于p型晶体管200的漏极侧的接触电阻率和互连薄膜电阻。此外,在本发明的各个实施例中,漏极焊盘250还包括设置在硅化物层252和覆盖层256之间的金属层254。金属层254可以是任何适当的金属材料。在本发明的各个实施例中,金属层254包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。如图1所示,在本发明的各个实施例中,p型晶体管200还包括钝化层260。钝化层260封装漏极焊盘250。在本发明的各个实施例中,钝化层260包括氮化硅。因此,在随后的制造工艺期间可以保护漏极焊盘250,并且可以进一步提高p型晶体管200的可靠性。
如图1所示,层间介电层300覆盖n型晶体管100、p型晶体管200和衬底15。层间介电层300可以通过以任何适当的沉积工艺沉积氧化硅来形成,其中沉积工艺包括但不限于原子层沉积(ALD)、化学汽相沉积(CVD)、低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、高密度等离子体化学汽相沉积(HDPCVD)、次大气压化学汽相沉积(SACVD)、快速热化学汽相沉积(RTCVD)、高温氧化沉积(HTO)、低温氧化沉积(LTO)、限制反应CVD(LRPCVD)。多个金属接触件400设置在层间介电层300中,并且金属接触件400分别与n型晶体管100和p型晶体管200的源电极110、210、栅电极130、230以及漏极焊盘150、250直接接触。
图2是示出了根据本发明的各个实施例的制造集成电路的方法800的流程图。方法800开始于框802,其中,接收衬底。衬底可以是半导体衬底,其包括已略掺杂有n型或p型掺杂物的单晶硅。衬底具有至少一个n型晶体管和至少一个p型晶体管。n型晶体管和p型晶体管分别包括设置在衬底中的源电极、基本垂直于源电极延伸的至少一个半导体沟道、环绕半导体沟道的栅电极,以及设置在半导体沟道的顶部上的漏电极。方法800继续到框804,其中,形成覆盖层和硅化物层。硅化物层覆盖n型晶体管和p型晶体管的漏电极。覆盖层形成在硅化物层上。方法800继续到框806,其中,形成金属层。金属层覆盖了覆盖层。方法800继续到框808,其中,形成第一钝化层。第一钝化层覆盖金属层。如框810所示,方法800还包括形成穿过硅化物层、覆盖层、金属层和第一钝化层的开口以生成设置在n型晶体管和p型晶体管的漏电极上的各个漏极焊盘。如框812所示,方法800还包括形成覆盖漏极焊盘的侧壁的第二钝化层。如框814所示,方法800还包括形成第一氧化物层以填充漏极焊盘的侧壁之间的间隙并覆盖第一钝化层。方法800继续到框816,其中,抛光第一氧化物层。抛光停止于第一钝化层。方法800继续到框818,其中,形成层间介电层。层间介电层覆盖n型晶体管、p型晶体管和衬底。如框820所示,方法800还包括形成设置在层间介电层中的多个金属接触件,并且金属接触件分别与n型晶体管和p型晶体管的源电极、栅电极和漏极焊盘直接接触。方法800的细节进一步在图3至图13中示出并在以下段落中进行描述。
图3是根据本发明的各个实施例的处于制造集成电路的方法的中间阶段的衬底的至少一部分的示意图。参照图3,接收衬底15。衬底15具有至少一个n型晶体管100和至少一个p型晶体管200。n型晶体管100和p型晶体管200分别包括设置在衬底中的源电极、基本垂直于源电极延伸的至少一个半导体沟道、环绕半导体沟道的栅电极、以及设置在半导体沟道的顶部上的漏电极。如图3所示,n型晶体管100包括源电极110、至少一个半导体沟道120、栅电极130和漏电极140。n型晶体管100的源电极110、半导体沟道120、栅电极130和漏电极140的细节与上述相似,因此这里省略细节描述。p型晶体管200包括源电极210、至少一个半导体沟道220、栅电极230和漏电极240。p型晶体管200的源电极210、半导体沟道220、栅电极230和漏电极240的细节与上述相似,因此这里省略细节描述。如图3所示,诸如氮化硅的钝化膜610和诸如氧化硅的介电层310可共形地沉积以覆盖n型晶体管100和p型晶体管200,并且钝化膜610和介电层310可通过抛光来进行平坦化和/或被蚀刻,以露出n型晶体管100和p型晶体管200的各个漏电极140、240。
图4是根据本发明的各个实施例的图3所示衬底在制造集成电路的方法的后续阶段的示意图。图5是根据本发明的各个实施例的图4所示衬底在制造集成电路的方法的后续阶段的示意图。参照图4和图5,在接收具有至少一个n型晶体管100和至少一个p型晶体管200的衬底15操作之后,形成硅化物层540。硅化物层540覆盖n型晶体管100和p型晶体管的漏电极140、240。硅化物层540可通过直接沉积硅化物膜(诸如,硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi))形成,以覆盖n型晶体管100的漏电极140和p型晶体管200的漏电极240。可通过多个步骤形成硅化物层540。如图4所示,在本发明的各个实施例中,形成覆盖n型晶体管100和p型晶体管200的漏电极140、240的硅化物层540的操作包括:沉积覆盖n型晶体管100和p型晶体管200的漏电极140、240的非晶硅层510。接着,沉积第一金属层520以覆盖非晶硅层510。第一金属层520可以包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。对非晶硅层510和第一金属层520进行退火以将非晶硅层510转化为如图5所示的硅化物层540。可以执行诸如快速热退火(RTAA)的退火工艺来用于转化非晶硅层510。在本发明的各个实施例中,第一金属层520也被转化为硅化物层540。还如图5所示,在形成硅化物层540之后,形成覆盖层530。覆盖层530覆盖硅化物层540。覆盖层530可以包括氮化钛(TiN)。在一些实施例中,在对非晶硅层510退火之前,在第一金属层520上形成覆盖层530。
图6是根据本发明的各个实施例的图5所示衬底在制造集成电路的方法的后续阶段的示意图。图7是根据本发明的各个实施例的图6所示衬底在制造集成电路的方法的后续阶段的示意图。参照图6,在形成覆盖硅化物层540的覆盖层530的操作之后,形成金属层550以覆盖覆盖层530。金属层550可以包括钨(W)。如图6所示,在形成覆盖了覆盖层530的金属层550之后,形成第一钝化层610。第一钝化层610覆盖金属层550。第一钝化层610可包括氮化硅,并且用任何适当的沉积工艺形成,任何适当的沉积工艺包括但不限于原子层沉积(ALD)、化学汽相沉积(CVD)、低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、高密度等离子体化学汽相沉积(HDPCVD)、次大气压化学汽相沉积(SACVD)、快速热化学汽相沉积(RTCVD)、高温氧化沉积(HTO)、低温氧化沉积(LTO)和限制反应CVD(LRPCVD)。参照图7,在形成覆盖金属层550的第一钝化层610的操作之后,形成穿过硅化物层540、覆盖层530、金属层550和第一钝化层610的开口650,以生成设置在n型晶体管100和p型晶体管200的漏电极140、240上的相应的漏极焊盘150、250。换句话说,在前述操作中形成的硅化物层540、覆盖层530和金属层550被分离为分别设置在n型晶体管100和p型晶体管200的漏电极140、240上的漏极焊盘150、250。n型晶体管100的漏极焊盘150包括硅化物层152、覆盖层156和接触金属层158,以及p型晶体管200的漏极焊盘250包括硅化物层252、覆盖层256和导电金属层258。在本发明的各个实施例中,如图7所示,n型晶体管100的漏极焊盘150还包括金属层154,以及p型晶体管200的漏极焊盘250还包括金属层254。
图8是根据本发明的各个实施例的图7所示衬底在制造集成电路的方法的后续阶段的示意图。图9是根据本发明的各个实施例的图8所示衬底在制造集成电路的方法的后续阶段的示意图。参照图8,在形成穿过硅化物层540、覆盖层530、金属层550和第一钝化层610的开口650的操作之后,形成覆盖漏极焊盘150、250的侧壁的第二钝化层620。第二钝化层620可包括作为第一钝化层610的氮化硅,并且可用任何适当的沉积工艺形成,沉积工艺包括但不限于原子层沉积(ALD)、化学汽相沉积(CVD)、低压化学汽相沉积(LPCVD)、等离子体增强化学汽相沉积(PECVD)、高密度等离子体化学汽相沉积(HDPCVD)、次大气压化学汽相沉积(SACVD)、快速热化学汽相沉积(RTCVD)、高温氧化沉积(HTO)、低温氧化沉积(LTO)和限制反应CVD(LRPCVD)。因此,可进一步保护n型晶体管100的漏极焊盘150和p型晶体管200的漏极焊盘250,并且可进一步提高n型晶体管100和p型晶体管200的可靠性。参照图9,可进一步蚀刻第二钝化层620以进行平坦化,并且为了后续处理去除了部分第二钝化层620。
图10是根据本发明的各个实施例的图9所示衬底在制造集成电路的方法的后续阶段的示意图。图11是根据本发明各个实施例的图10所示衬底在制造集成电路的方法的后续阶段的示意图。参照图10,在形成覆盖漏极焊盘150、250的侧壁的第二钝化层620的操作之后,形成第一氧化物层630以填充漏极焊盘150、250的侧壁之间的间隙。第一氧化物层630可包括氧化硅,并且可用任何适当的沉积工艺形成。在本发明的各个实施例中,通过流动式CVD执行形成填充漏极焊盘150、250的侧壁之间的间隙的第一氧化物层630。因此,可填充漏极焊盘150、250的侧壁之间的间隙而没有空隙,并且可进一步提高n型晶体管100和p型晶体管200的可靠性。参照图11,在形成第一氧化物层630的操作之后,抛光第一氧化物层630。应该注意,抛光步骤停止于第一钝化层610处,因为第一钝化层610包括不同于第一氧化物层630的氮化硅。因此,增大了抛光的工艺窗,并且可以改善漏极焊盘150、250的厚度的均匀性。
图12是根据本发明的各个实施例的图11所示衬底在制造集成电路的方法的后续阶段的示意图。图13是根据本发明的各个实施例的图12所示衬底在制造集成电路的方法的后续阶段的示意图。参照图12,在抛光第一氧化物层630的操作之后,形成层间介电层640。层间介电层640覆盖n型晶体管100、p型晶体管200和衬底15。层间介电(ILD)层640可包括任何现在已知或之后开发的适合用于第一接触层的介电质,诸如但不限于氮化硅(Si3N4)、氧化硅(SiO2)、氟化SiO2(FSG)、氢化碳氧化硅(SiCOH)、多孔SiCOH、硼磷硅酸盐玻璃(BPSG)、倍半硅氧烷、包括硅(Si)原子、碳(C)原子、氧(O)原子和/或氢(H)原子的掺碳(C)氧化物(即,有机硅酸盐)、热固性聚亚芳基醚、旋涂含硅碳的聚合物材料、其他低介电常数材料或它们的层。在本发明的各个实施例中,ILD层230可包括诸如金属氧化物(诸如,氧化钽(Ta2O5)、氧化钡钛(BaTiO3)、氧化铪(HfO2)、氧化锆(ZrO2)、氧化铝(Al2O3))的高介电常数(高k)电介质。在形成层间介电层640的操作之后,形成多个金属接触件400。参照图13,可通过光刻-蚀刻工艺来形成多个开口以露出n型晶体管100和p型晶体管200的源电极110、210、栅电极130、230以及漏极焊盘150、250。然后,如图13所示,可以在层间介电层300(包括第一氧化物层630和层间介电层640)上形成接触金属层410。如图13所示,接触金属膜410设置在层间介电层300上,并且金属接触件400分别与n型晶体管100和p型晶体管200的源电极110、210、栅电极130、230以及漏极焊盘150、250直接接触。抛光接触金属膜410以产生如图1所示的多个金属接触件400。因此,制造了根据本发明的各个实施例的图1所示的集成电路10。多个金属接触件400还可以包括钨、铝、铜或其他适当的材料。
图14是示出了根据各个实施例的如方法800的框804所示的形成覆盖n型晶体管和p型晶体管的漏电极的覆盖层和硅化物层。图14是根据本发明的各个实施例的图13所示衬底在制造集成电路的方法的后续阶段的示意图。参照图14,在接收具有至少一个n型晶体管100和至少一个p型晶体管200的衬底15的操作之后,形成硅化物层710和覆盖层730。硅化物层710覆盖n型晶体管100和p型晶体管200的漏电极140、240。硅化物层710可包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi)或它们的组合以覆盖n型晶体管100的漏电极140和p型晶体管200的漏电极240。通过多个步骤可形成硅化物层710。如图14所示,在本发明的各个实施例中,形成覆盖n型晶体管100和p型晶体管200的漏电极140、240的覆盖层730和硅化物层710的操作包括:沉积覆盖n型晶体管100和p型晶体管200的漏电极140、240的第一金属层720。第一金属层720可以包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。接着,对n型晶体管100和p型晶体管200的漏电极140、240以及第一金属层720进行退火以将漏电极140、240的一部分转化为如图14所示的硅化物层710。在形成硅化物层710之后,漏电极140、240的体积因此减少。可执行诸如快速热退火(RTA)的退火工艺来用于形成硅化物层710。然后,在第一金属层720上形成覆盖层730。覆盖层730覆盖第一金属层720。覆盖层730可包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。在一些实施例中,可在退火工艺之前形成覆盖层730。例如,形成覆盖n型晶体管100和p型晶体管200的漏电极140、240的覆盖层730和硅化物层710的操作可包括:沉积覆盖n型晶体管100和p型晶体管200的漏电极140、240的第一金属层720。接着,在第一金属层720上形成覆盖层730。然后,对n型晶体管100和p型晶体管200的漏电极140、240以及第一金属层710进行退火以将漏电极140、240的一部分转化为如图14所示的硅化物层710。
图15是根据本发明的各个实施例的集成电路的至少一部分的示意图。参照图1、图2和图15,图15所示衬底是在执行方法800中的框808至框822的步骤之后的图14所示的衬底。图15和图1中的集成电路10之间的差别包括:n型晶体管100的漏电极141、n型晶体管100的漏极焊盘151、p型晶体管200的漏电极241以及p型晶体管200的漏极焊盘251。n型晶体管100的漏极焊盘151包括硅化物层153、金属层155、覆盖层157和接触金属层159。硅化物层153与漏电极141直接接触。金属层155设置在硅化物层153上。覆盖层157设置在硅化物层153上。接触金属层159设置在覆盖层157上。p型晶体管200的漏极焊盘251包括硅化物层253、金属层255、覆盖层257和接触金属层259。硅化物层253与漏电极241直接接触。金属层255设置在硅化物层253上。覆盖层257设置在硅化物层253上。接触金属层259设置在覆盖层257上。在本发明的各个实施例中,硅化物层153、253包括硅化钛(TiSi)、硅化镍(NiSi)、硅化钴(CoSi)或它们的组合。在本发明的各个实施例中,金属层155、255包括钛(Ti)、镍(Ni)、钴(Co)或它们的组合。在本发明的各个实施例中,覆盖层157、257包括氮化钛(TiN)、氮化钽(TaN)或它们的组合。根据本发明的各个实施例,接触金属层159、259包括钨(W)、铝(Al)、钴(Co)或它们的组合。
根据本发明的各个实施例,由于漏极焊盘具有多个导电层的特殊设计,显著减小了具有晶体管的集成电路的电阻,诸如,漏极侧的接触电阻率和互连薄膜电阻。如上所述,晶体管的漏极焊盘不是单层物质(诸如,单层硅化物膜)而是多个导电层。因此,通过引入电阻小于硅化物层的电阻的接触金属层,可大大减小了与晶体管相关的漏极侧的接触电阻率和互连薄膜电阻。此外,也改善了在制造晶体管期间的制造具有晶体管的集成电路的工艺灵活性,诸如,对漏极消耗和硅化的控制,因此增强了根据本发明的各个实施例的具有晶体管的集成电路的性能。
根据本发明的各个实施例,一种晶体管包括源电极、至少一个半导体沟道、栅电极、漏电极和漏极焊盘。源电极设置在衬底中。半导体沟道基本垂直于源电极延伸。栅电极环绕半导体沟道。漏电极设置在半导体沟道的顶部上。漏极焊盘设置在漏电极上,其中,漏极焊盘包括多个导电层。
根据本发明的其他各个实施例,一种集成电路包括至少一个n型晶体管、至少一个p型晶体管、层间介电层和多个金属接触件。n型晶体管设置在衬底上。p型晶体管设置在衬底上并与n型晶体管相邻。n型晶体管和p型晶体管分别包括:设置在衬底中的源电极;基本垂直于源电极延伸的至少一个半导体沟道;环绕半导体沟道的栅电极;设置在半导体沟道的顶部上的漏电极;以及设置在漏电极上的漏极焊盘。漏极焊盘包括多个导电层。层间介电层覆盖n型晶体管、p型晶体管和衬底。多个金属接触件设置在层间介电层中,金属接触件分别与n型晶体管和p型晶体管的源电极、栅电极和漏极焊盘直接接触。
根据本发明的各个实施例,一种制造集成电路的方法包括:接收具有至少一个n型晶体管和至少一个p型晶体管的衬底,其中,n型晶体管和p型晶体管的每一个均包括设置在衬底中的源电极、基本垂直于源电极延伸的至少一个半导体沟道、环绕半导体沟道的栅电极、以及设置在半导体沟道的顶部上的漏电极。该方法还包括:形成覆盖n型晶体管和p型晶体管的漏电极的覆盖层和硅化物层,其中,覆盖层形成在硅化物层上。该方法还包括:形成覆盖该覆盖层的金属层。该方法还包括:形成覆盖金属层的第一钝化层。该方法还包括:形成穿过硅化物层、覆盖层、金属层和第一钝化层的开口以产生设置在n型晶体管和p型晶体管的漏电极上的各个漏极焊盘。该方法还包括:形成覆盖漏极焊盘的侧壁的第二钝化层。该方法还包括:形成第一氧化物层以填充漏极焊盘的侧壁之间的间隙并覆盖第一钝化层。该方法还包括:抛光第一氧化物层,其中,抛光停止于第一钝化层。该方法还包括:形成覆盖n型晶体管、p型晶体管和衬底的层间介电层。该方法还包括:形成设置在层间介电层中的多个金属接触件,并且金属接触件分别与n型晶体管和p型晶体管的源电极、栅电极和漏极焊盘直接接触。
上面论述了多个实施例的特征使得本领域技术人员能够更好地理解本发明的各个方面。本领域技术人员应该理解,他们可以容易地以本公开为基础设计或修改用于执行与本文所述实施例相同的目的和/或实现相同优点的其他工艺和结构。本领域技术人员还应该意识到,这些等效结构不背离本发明的精神和范围,并且可以在不背离本发明的精神和范围的情况下做出各种变化、替换和改变。
Claims (10)
1.一种晶体管,包括:
源电极,设置在衬底中;
至少一个半导体沟道,基本垂直于所述源电极而延伸;
栅电极,环绕所述半导体沟道;
漏电极,设置在所述半导体沟道的顶部上;以及
漏极焊盘,设置在所述漏电极上,其中,所述漏极焊盘包括多个导电层。
2.根据权利要求1所述的晶体管,其中,所述漏极焊盘包括:
硅化物层,与所述漏电极直接接触;
覆盖层,设置在所述硅化物层上;以及
接触金属层,设置在所述覆盖层上。
3.根据权利要求2所述的晶体管,其中,所述硅化物层包括硅化钛、硅化镍、硅化钴或它们的组合。
4.一种集成电路,包括:
至少一个n型晶体管,设置在衬底上;
至少一个p型晶体管,设置在所述衬底上并且与所述n型晶体管相邻,其中,所述n型晶体管和所述p型晶体管分别包括:
源电极,设置在所述衬底中;
至少一个半导体沟道,基本垂直于所述源电极而延伸;
栅电极,环绕所述半导体沟道;
漏电极,设置在所述半导体沟道的顶部上;和
漏极焊盘,设置在所述漏电极上,所述漏极焊盘包括多个导电层;
层间介电层,覆盖所述n型晶体管、所述p型晶体管和所述衬底;以及
多个金属接触件,设置在所述层间介电层中,所述金属接触件分别与所述n型晶体管和所述p型晶体管的所述源电极、所述栅电极和所述漏极焊盘直接接触。
5.根据权利要求4所述的集成电路,其中,所述漏极焊盘包括:
硅化物层,与所述漏电极直接接触;
覆盖层,设置在所述硅化物层上;以及
接触金属层,设置在所述覆盖层上。
6.根据权利要求5所述的集成电路,其中,所述硅化物层包括硅化钛、硅化镍、硅化钴或它们的组合。
7.一种方法,包括:
接收具有至少一个n型晶体管和至少一个p型晶体管的衬底,其中,所述n型晶体管和所述p型晶体管中的每一个均包括设置在所述衬底中的源电极、基本垂直于所述源电极而延伸的至少一个半导体沟道、环绕所述半导体沟道的栅电极,以及设置在所述半导体沟道的顶部上的漏电极;
形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的覆盖层和硅化物层,其中,所述覆盖层形成在所述硅化物层上;
形成覆盖所述覆盖层的金属层;
形成覆盖所述金属层的第一钝化层;
形成穿过所述硅化物层、所述覆盖层、所述金属层和所述第一钝化层的开口以产生分别设置在所述n型晶体管和所述p型晶体管的所述漏电极上的漏极焊盘;
形成覆盖所述漏极焊盘的侧壁的第二钝化层;
形成第一氧化物层以填充所述漏极焊盘的侧壁之间的间隙并覆盖所述第一钝化层;
抛光所述第一氧化物层,其中,所述抛光停止于所述第一钝化层处;
形成覆盖所述n型晶体管、所述p型晶体管和所述衬底的层间介电层;以及
形成设置在所述层间介电层中的多个金属接触件,并且所述金属接触件分别与所述n型晶体管和所述p型晶体管的所述源电极、所述栅电极和所述漏极焊盘直接接触。
8.根据权利要求7所述的方法,其中,形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的所述覆盖层和所述硅化物层包括:
沉积覆盖所述n型晶体管和所述p型晶体管的所述漏电极的非晶硅层;
沉积覆盖所述非晶硅层的第一金属层;
对所述非晶硅层和所述第一金属层进行退火以将所述非晶硅层转化为所述硅化物层;以及
在所述第一金属层上沉积覆盖层。
9.根据权利要求8所述的方法,其中,所述第一金属层也被转化为所述硅化物层。
10.根据权利要求7所述的方法,其中,形成覆盖所述n型晶体管和所述p型晶体管的所述漏电极的所述覆盖层和所述硅化物层包括:
沉积覆盖所述n型晶体管和所述p型晶体管的所述漏电极的第一金属层;
对所述第一金属层以及所述n型晶体管和所述p型晶体管的所述漏电极进行退火以将所述漏电极的一部分转化为所述硅化物层;以及
在所述第一金属层上沉积覆盖层。
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