CN105977235A - Novel three-dimensional microwave multi-chip module structure - Google Patents
Novel three-dimensional microwave multi-chip module structure Download PDFInfo
- Publication number
- CN105977235A CN105977235A CN201610499834.0A CN201610499834A CN105977235A CN 105977235 A CN105977235 A CN 105977235A CN 201610499834 A CN201610499834 A CN 201610499834A CN 105977235 A CN105977235 A CN 105977235A
- Authority
- CN
- China
- Prior art keywords
- chip
- silicon chip
- top layer
- solder mask
- mmic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
- H01L25/165—Containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/24137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
Abstract
The invention discloses a novel three-dimensional microwave multi-chip module structure, and relates to the field of microwave microelectronic packaging. The structure comprises a bottom silicon chip, an MMIC chip, a top silicon chip and an ASIC chip from the bottom to the top. The bottom silicon chip is provided with a chip installation groove through etching, and the surface of the bottom silicon chip is plated with a first metal layer. The MMIC chip is bound at the bottom of the chip installation groove through a conductive glue layer, and the upper surface of the MMIC chip and the upper surface of the bottom silicon chip are sequentially provided with a sealed protection layer, a second metal layer and a first solder mask layer. A part, corresponding to the chip installation groove of the bottom silicon chip, of the bottom of the top silicon chip is provided with a bottom groove in an etching manner. The corresponding parts of the bottom and top silicon chips are respectively provided with a welding ball convex point pole in an etching manner. A third solder mask layer of the top silicon chip is provided with a metal electrode in an etching manner, and the ASIC chip is welded on the metal electrode of the top silicon chip. The technological production of a three-dimensional microwave multi-chip module is completed in a mode of wafer level through employing a silicon cavity structure and benzocyclobutene secondary wiring, and the production efficiency is improved.
Description
Technical field
The present invention relates to microwave microelectronics Packaging field.
Background technology
Along with the development of microwave and millimeter wave technology, miniaturization, the integrated and multi-functional developing direction becoming frequency microwave assembly.Miniaturization, integrated development are mainly reflected in following two aspect: (1) develops multifunction chip, microwave function unit such as including low-noise amplifier, driving amplifier, frequency mixer, wave filter, switch, numerical-control attenuator, digital phase shifter can be integrated on a microwave monolithic integrated circuit (MMIC), realize the miniaturization of system, but the function which can not realize unlike material chip is integrated.(2) use three dimension system Integrated Solution, the MMIC etc. of the large scale integrated circuit (ASIC) in assembly and unlike material is placed on different layers, then use the mode of vertical interconnection to realize three-dimensional microwave multi-chip module.
Current three-dimensional microwave Mcm Technique be first by the chips such as MMIC and ASIC and other slice component High Density Packaging on LTCC multilager base plate or thin-film multilayer microwave interconnecting substrate, form 2D multi-chip module, use the interconnection techniques such as hair button or insulator again, in the Z-axis direction the multi-chip module stacking of difference in functionality is interconnected, realize the vertical interconnection architecture of multilamellar, form three-dimensional microwave multi-chip module.There is following inferior position in this three-dimensional microwave multi-chip module:
(1) need a large amount of hair buttons are positioned accurately and interconnected, bring the biggest difficulty to assembling.
(2) needing to be assembled in metal case, use the mode of stannum envelope or Laser seal welding to reach sealing effectiveness, structure and the technological parameter of this sealing cap mode butt welded seam are very sensitive, and sealing cap difficulty is big.
(3) current three-dimensional microwave multi-chip module needs individually to assemble each assembly individuality, and production efficiency is low, is not suitable for mass production.
(4) current three-dimensional microwave multi-chip module uses metallic partition to solve plus and blowup link and the electromagnetic compatibility problem of multichannel assembly, and technical difficulty is big, increases assembly volume.
Summary of the invention
The technical problem to be solved is to provide a kind of novel three-dimensional Microwave Multichip Module structure, uses silica-based cover plate with groove and metal salient point to realize micro-cavity structure, it is possible to microwave chip is carried out single electromagnetic shielding；Using silicon cavity configuration and the wiring of benzocyclobutene secondary, the technique completing three-dimensional microwave multi-chip module in wafer level mode produces, and on the basis of solving assembly assembly difficulty and sealing problem, improves production efficiency.
For solving above-mentioned technical problem, the technical solution used in the present invention is: a kind of novel three-dimensional Microwave Multichip Module structure, includes base silicon wafer, mmic chip, top layer silicon chip, asic chip from bottom to top；In described base silicon wafer, corrosion has chip mounting groove; and at electroplating surface the first metal layer; mmic chip is bonded in bottom chip mounting groove by conductive adhesive layer; and the upper surface of the upper surface of mmic chip and base silicon wafer is at same plane; on the upper surface of mmic chip with the upper surface of base silicon wafer, growth has seal protection layer, the second metal level, the first solder mask successively; bottom described top layer silicon chip, the chip mounting groove correspondence position corrosion with base silicon wafer has bottom groove, described top layer silicon chip lower surface to grow successively and have the 3rd metal level, the second solder mask；Top layer silicon chip upper surface grows successively and has the 4th metal level, the 3rd solder mask；Connection the 4th metal level and the silicon through hole of the 3rd metal level it is etched with in described top layer silicon chip, described base silicon wafer and top layer silicon chip correspondence position are all etched with solder bumps electrode, and are connected by the solder bumps electrode welding of base silicon wafer and top layer silicon chip correspondence position by solder；3rd solder mask of described top layer silicon chip is etched with metal electrode, and asic chip is welded on the metal electrode of top layer silicon chip.
The corrosion depth that technical scheme is described chip mounting groove optimized further is 100 μm, and the corrosion depth of described top layer silicon chip bottom groove is 250 μm.
The material that technical scheme is described seal protection layer, the first solder mask, the second solder mask and the 3rd solder mask optimized further is benzocyclobutene or polyimides.
The thickness that technical scheme is described seal protection layer optimized further is 20 ~ 30 μm, and the thickness of described first solder mask, the second solder mask and the 3rd solder mask is 5 μm.
Use and have the beneficial effects that produced by technique scheme: the present invention is by using silicon cavity configuration and benzocyclobutene secondary Wiring technique, the technique completing three-dimensional microwave multi-chip module in wafer level mode produces, on the basis of solving assembly assembly difficulty and sealing problem, improve production efficiency.By using silica-based cover plate with groove and metal salient point to realize micro-cavity structure, it is possible to microwave chip is carried out single electromagnetic shielding, solves HGL high gain link and an interchannel electromagnetic compatibility difficult problem in multi-chip module.This structure can use semiconductor technology and full-automatic microwave assembly technology to produce, and improves production efficiency and the yield rate of complex assemblies.Meanwhile, use three-dimensional stacked mode to carry out integrated control chip and microwave chip, improve level of integrated system, reduce assembly volume.
Accompanying drawing explanation
Fig. 1 is the integrally-built sectional view of the present invention；
Fig. 2 is the circuit layout schematic diagram in base silicon wafer of the present invention；
Fig. 3 is the sectional view of top layer silicon chip architecture；
Wherein, 1 base silicon wafer, 2 mmic chips; 3 solder bumps electrodes, 4 top layer silicon chips, 5 silicon through holes; 6 asic chips, 7 first solder masks, 8 second metal levels; 9 seal protection layers, 10 conductive adhesive layers, 11 the first metal layers; 12 the 3rd metal levels, 13 second solder masks, 14 the 4th metal levels; 15 the 3rd solder masks, 16 bottom grooves, 17 metal electrodes.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, it is clear that described embodiment is only a part of embodiment of the present invention rather than whole embodiments.Based on the embodiment in the present invention, the every other embodiment that those of ordinary skill in the art are obtained under not making creative work premise, broadly fall into the scope of protection of the invention.
As it is shown in figure 1, the invention discloses a kind of novel three-dimensional Microwave Multichip Module structure, include base silicon wafer 1, mmic chip 2, top layer silicon chip 4, asic chip 6 from bottom to top；In described base silicon wafer 1, corrosion has chip mounting groove, and at electroplating surface the first metal layer 11, mmic chip 2 is bonded in bottom chip mounting groove by conductive adhesive layer 10, and the upper surface of the upper surface of mmic chip 2 and base silicon wafer 1 is at same plane, on the upper surface of mmic chip 2 with the upper surface of base silicon wafer 1, growth has seal protection layer 9 successively, second metal level 8, first solder mask 7, bottom described top layer silicon chip 4, the chip mounting groove correspondence position corrosion with base silicon wafer 1 has bottom groove 16, described top layer silicon chip 4 lower surface grows successively and has the 3rd metal level 12, second solder mask 13；Top layer silicon chip 4 upper surface grows successively the 4th metal level the 14, the 3rd solder mask 15；Connection the 4th metal level 14 and the silicon through hole 5 of the 3rd metal level 12 it is etched with in described top layer silicon chip 4, described base silicon wafer 1 and top layer silicon chip 4 correspondence position are all etched with solder bumps electrode 3, and are welded to connect by the solder bumps electrode 3 of base silicon wafer 1 and top layer silicon chip 4 correspondence position by solder；3rd solder mask 15 of described top layer silicon chip 4 is etched with metal electrode 17, and asic chip 6 is welded on the metal electrode 17 of top layer silicon chip 4.
The corrosion depth that embodiment is described chip mounting groove optimized further is 100 μm, and the corrosion depth of described top layer silicon chip 4 bottom groove 16 is 250 μm.
The material that embodiment is described seal protection layer the 9, first solder mask the 7, second solder mask 13 and the 3rd solder mask 15 optimized further is benzocyclobutene or polyimides.
The thickness that embodiment is described seal protection layer 9 optimized further is 20 ~ 30 μm, and the thickness of described first solder mask the 7, second solder mask 13 and the 3rd solder mask 15 is 5 μm.
As it is shown in figure 1, the structure of the present invention is mainly made up of two-layer silicon chip, benzocyclobutene medium and solder bumps electrode, wherein, base silicon wafer 1 uses MEMS bulk silicon technological to process chip mounting groove, groove depth 100 μm, provides for microwave and millimeter wave mmic chip 2 and supports；Top layer silicon chip 4 is correspondence position corrosion bottom groove above microwave and millimeter wave chip 2, groove depth 250 μm, processing silicon through hole 5 simultaneously, surface localized metallic, welded by the metallization pattern of solder bumps electrode 3 and benzocyclobutene top layer, realizing vertical interconnection and electromagnetic shielding, top layer silicon chip 4 is arranged above the asic chip 6 of BGA package or wafer-level packaging.
As in figure 2 it is shown, the circuit layout schematic diagram in base silicon wafer of the present invention, microwave monolithic integrated circuit is bonded on base silicon wafer 1 substrate by conducting resinl 10, and after bonding, microwave and millimeter wave monolithic integrated optical circuit upper surface and base silicon wafer 1 upper surface of base plate flush；It is then coated with benzocyclobutene; thickness is 20 ~ 30 μm, forms bare chip and seals protection, by etching through hole on benzocyclobutene; expose the I/O port of microwave and millimeter wave monolithic integrated optical circuit, form side metallization by metallization and complete secondary wiring；It is coated with one layer of benzocyclobutene to realize welding resistance, is exposed the electrode of solder bumps by etching.
As it is shown on figure 3, top layer silicon chip base cover plate uses MEMS bulk silicon technological corrosion bottom groove 16 above corresponding microwave and millimeter wave chip 2, to eliminate the cover plate impact on bottom microwave chip performance；Etching TSV through hole after erosion grooves, then positive and negative carries out metalized, forms metallization pattern.After completing the processing of silicon chip, two faces positive and negative to silicon chip carry out secondary wiring process respectively, and wherein first top layer coats one layer of benzocyclobutene or polyimides, and dielectric thickness is 5 μm, then by etch media layer, form secondary wiring pattern after metallization；First bottom coats one layer of benzocyclobutene or polyimides, and dielectric thickness is 5 μm, etches solder bumps electrode, carries out planting ball backflow, form solder bumps on solder bumps electrode, and bump solder is PbSn.
The base silicon wafer of present configuration is the supporting layer of microwave chip, top layer silicon chip is cover plate, top layer cover plate and PbSn soldered ball constitute miniature cavities structure, and microwave and millimeter wave chip is formed electromagnetic shielding, and the control chip for top layer provides and supports and and the interconnection of base silicon wafer simultaneously.Operation comprises the main flow such as MEMS bulk silicon technological, microwave assembly technology and semiconductor lithography process, and technological process is mutually compatible with conventional semiconductor process, uses fully-automatic equipment to carry out burst after completing wafer scale assembling, and complete batches of assembly produces.Technical process design is as follows:
1, the manufacturing process steps of base silicon wafer:
2, the manufacturing process steps of top layer silicon chip:
3, the manufacturing process steps that base silicon wafer assembles with top layer silicon chip:
。
Claims (4)
1. a novel three-dimensional Microwave Multichip Module structure, it is characterised in that: include base silicon wafer (1), mmic chip (2), top layer silicon chip (4), asic chip (6) from bottom to top；The upper corrosion of described base silicon wafer (1) has chip mounting groove, and in electroplating surface the first metal layer (11), mmic chip (2) is bonded in bottom chip mounting groove by conductive adhesive layer (10), and the upper surface of the upper surface of mmic chip (2) and base silicon wafer (1) is at same plane, on the upper surface of mmic chip (2) with the upper surface of base silicon wafer (1), growth has seal protection layer (9) successively, second metal level (8), first solder mask (7), there is bottom groove (16) described top layer silicon chip (4) bottom with the chip mounting groove correspondence position corrosion of base silicon wafer (1), described top layer silicon chip (4) lower surface grows successively and has the 3rd metal level (12), second solder mask (13)；Top layer silicon chip (4) upper surface grows successively the 4th metal level (14), the 3rd solder mask (15)；Connection the 4th metal level (14) and the silicon through hole (5) of the 3rd metal level (12) it is etched with in described top layer silicon chip (4), described base silicon wafer (1) and top layer silicon chip (4) correspondence position are all etched with solder bumps electrode (3), and are welded to connect by the solder bumps electrode (3) of base silicon wafer (1) and top layer silicon chip (4) correspondence position by solder；3rd solder mask (15) of described top layer silicon chip (4) is etched with metal electrode (17), and asic chip (6) is welded on the metal electrode (17) of top layer silicon chip (4).
A kind of novel three-dimensional Microwave Multichip Module structure the most according to claim 1, it is characterised in that: the corrosion depth of described chip mounting groove is 100 μm, and the corrosion depth of described top layer silicon chip (4) bottom groove (16) is 250 μm.
A kind of novel three-dimensional Microwave Multichip Module structure the most according to claim 1, it is characterised in that: the material of described seal protection layer (9), the first solder mask (7), the second solder mask (13) and the 3rd solder mask (15) is benzocyclobutene or polyimides.
A kind of novel three-dimensional Microwave Multichip Module structure the most according to claim 3; it is characterized in that: the thickness of described seal protection layer (9) is 20 ~ 30 μm, the thickness of described first solder mask (7), the second solder mask (13) and the 3rd solder mask (15) is 5 μm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610499834.0A CN105977235B (en) | 2016-06-30 | 2016-06-30 | A kind of novel three-dimensional Microwave Multichip Module structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610499834.0A CN105977235B (en) | 2016-06-30 | 2016-06-30 | A kind of novel three-dimensional Microwave Multichip Module structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105977235A true CN105977235A (en) | 2016-09-28 |
| CN105977235B CN105977235B (en) | 2019-04-09 |
Family
ID=56953913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610499834.0A Active CN105977235B (en) | 2016-06-30 | 2016-06-30 | A kind of novel three-dimensional Microwave Multichip Module structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105977235B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107285270A (en) * | 2017-05-31 | 2017-10-24 | 中国电子科技集团公司第十三研究所 | Integrated micro-system three-dimensional stacking structure of silicon substrate and preparation method thereof |
| CN109037170A (en) * | 2018-07-13 | 2018-12-18 | 中国电子科技集团公司第五十八研究所 | A kind of radio frequency micro-system integration packaging antenna |
| CN109904128A (en) * | 2019-03-13 | 2019-06-18 | 中国科学院微电子研究所 | Three-dimensionally integrated T/R assembly encapsulation structure and packaging method based on silicon substrate support plate |
| CN110634842A (en) * | 2019-08-22 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure with electromagnetic shielding function and preparation method |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656244A (en) * | 2009-07-10 | 2010-02-24 | 中国科学院上海微系统与信息技术研究所 | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method |
| CN102110673A (en) * | 2010-10-27 | 2011-06-29 | 中国科学院上海微系统与信息技术研究所 | Wafer level MMCM (microwave multichip module) packaging structure using photosensitive BCB (benzocyclobutene) as dielectric layer and method |
| CN102723306A (en) * | 2012-06-28 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof |
| US20130307095A1 (en) * | 2010-08-27 | 2013-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite Wafer Semiconductor |
| CN204714514U (en) * | 2015-05-28 | 2015-10-21 | 华天科技（昆山）电子有限公司 | Three-dimensional stacked MEMS package structure |
| US20150325553A1 (en) * | 2011-04-30 | 2015-11-12 | Stats Chippac, Ltd. | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP |
| CN103818874B (en) * | 2014-02-12 | 2016-02-10 | 北京时代民芯科技有限公司 | The method for packing of MEMS structure and treatment circuit integrated system |
| CN205187842U (en) * | 2015-11-13 | 2016-04-27 | 华天科技（昆山）电子有限公司 | MEMS chip package structure |
| CN205723525U (en) * | 2016-06-30 | 2016-11-23 | 中国电子科技集团公司第十三研究所 | A kind of novel three-dimensional Microwave Multichip Module structure |
-
2016
- 2016-06-30 CN CN201610499834.0A patent/CN105977235B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101656244A (en) * | 2009-07-10 | 2010-02-24 | 中国科学院上海微系统与信息技术研究所 | Multilayer interconnection packaging structure of silica-based embedded microwave multi chip module and manufacturing method |
| US20130307095A1 (en) * | 2010-08-27 | 2013-11-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite Wafer Semiconductor |
| CN102110673A (en) * | 2010-10-27 | 2011-06-29 | 中国科学院上海微系统与信息技术研究所 | Wafer level MMCM (microwave multichip module) packaging structure using photosensitive BCB (benzocyclobutene) as dielectric layer and method |
| US20150325553A1 (en) * | 2011-04-30 | 2015-11-12 | Stats Chippac, Ltd. | Semiconductor Device and Method of Embedding TSV Semiconductor Die Within Substrate for Vertical Interconnect in POP |
| CN102723306A (en) * | 2012-06-28 | 2012-10-10 | 中国科学院上海微系统与信息技术研究所 | Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof |
| CN103818874B (en) * | 2014-02-12 | 2016-02-10 | 北京时代民芯科技有限公司 | The method for packing of MEMS structure and treatment circuit integrated system |
| CN204714514U (en) * | 2015-05-28 | 2015-10-21 | 华天科技（昆山）电子有限公司 | Three-dimensional stacked MEMS package structure |
| CN205187842U (en) * | 2015-11-13 | 2016-04-27 | 华天科技（昆山）电子有限公司 | MEMS chip package structure |
| CN205723525U (en) * | 2016-06-30 | 2016-11-23 | 中国电子科技集团公司第十三研究所 | A kind of novel three-dimensional Microwave Multichip Module structure |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107285270A (en) * | 2017-05-31 | 2017-10-24 | 中国电子科技集团公司第十三研究所 | Integrated micro-system three-dimensional stacking structure of silicon substrate and preparation method thereof |
| CN109037170A (en) * | 2018-07-13 | 2018-12-18 | 中国电子科技集团公司第五十八研究所 | A kind of radio frequency micro-system integration packaging antenna |
| CN109904128A (en) * | 2019-03-13 | 2019-06-18 | 中国科学院微电子研究所 | Three-dimensionally integrated T/R assembly encapsulation structure and packaging method based on silicon substrate support plate |
| CN109904128B (en) * | 2019-03-13 | 2020-12-11 | 中国科学院微电子研究所 | Three-dimensional integrated T/R assembly packaging structure and packaging method based on silicon-based carrier plate |
| CN110634842A (en) * | 2019-08-22 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure with electromagnetic shielding function and preparation method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105977235B (en) | 2019-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7683459B2 (en) | Bonding method for through-silicon-via based 3D wafer stacking | |
| JP5621155B2 (en) | Method for vertically interconnecting 3D electronic modules by vias | |
| KR20150068495A (en) | Wafer level packaging using flip chip mounting | |
| JP5643880B2 (en) | MEMS device and manufacturing method thereof | |
| TWI446509B (en) | Microelectronic elements having metallic pads overlying vias | |
| CN105977235A (en) | Novel three-dimensional microwave multi-chip module structure | |
| WO2009146587A1 (en) | Bongding method for through-silicon-via based 3d wafer stacking | |
| KR20010018694A (en) | Manufacturing method for three demensional stack chip package | |
| JP2008135763A (en) | Semiconductor module, and method for manufacturing electronic equipment and semiconductor module | |
| US20040124513A1 (en) | High-density multichip module package | |
| CN112928035B (en) | Board-level flip chip packaging structure with electromagnetic shielding function and preparation method thereof | |
| CN205723525U (en) | A kind of novel three-dimensional Microwave Multichip Module structure | |
| CN112768364A (en) | Board-level three-dimensional chip packaging structure and preparation method thereof | |
| CN109150134B (en) | Acoustic meter chip packaging method and acoustic meter device | |
| CN105347288B (en) | A kind of many device closed structures and its manufacture method for wafer-level packaging | |
| WO2023098004A1 (en) | Three-dimensional integrated airtight packaging interconnect structure and manufacturing method therefor | |
| CN107230684B (en) | The encapsulating structure and its manufacturing method of wafer scale image sensing chip | |
| CN208580738U (en) | Stack type chip packaging structure | |
| WO2021114140A1 (en) | Packaging method for filter chip, and packaging structure | |
| CN208580737U (en) | Stack type chip packaging structure | |
| CN214588747U (en) | Board-level three-dimensional chip packaging structure | |
| CN112687638B (en) | Vertical interconnected metal ceramic packaging shell, device and preparation method | |
| CN116666232B (en) | All-glass stacked packaging structure and preparation method thereof | |
| CN116193972B (en) | Sensor preparation method and structure | |
| CN113819899B (en) | Heterogeneous integrated surface-mounted gyroscope |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |