CN105977235B - A kind of novel three-dimensional Microwave Multichip Module structure - Google Patents

A kind of novel three-dimensional Microwave Multichip Module structure Download PDF

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CN105977235B
CN105977235B CN201610499834.0A CN201610499834A CN105977235B CN 105977235 B CN105977235 B CN 105977235B CN 201610499834 A CN201610499834 A CN 201610499834A CN 105977235 B CN105977235 B CN 105977235B
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silicon wafer
chip
top layer
solder mask
solder
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CN105977235A (en
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赵永志
王绍东
王志强
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CETC 13 Research Institute
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20Structure, shape, material or disposition of high density interconnect preforms
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device

Abstract

The invention discloses a kind of novel three-dimensional Microwave Multichip Module structures, are related to microwave microelectronics Packaging field.It from bottom to top include base silicon wafer, mmic chip, top layer silicon wafer, asic chip;Corrosion has chip mounting groove in base silicon wafer, and in electroplating surface the first metal layer, mmic chip is bonded in chip by conductive adhesive layer and installs trench bottom, successively growth has seal protection layer on the upper surface of mmic chip and the upper surface of base silicon wafer, second metal layer, first solder mask, the corrosion of the chip mounting groove corresponding position of top layer silicon wafer bottom and base silicon wafer has bottom groove, base silicon wafer and top layer silicon wafer corresponding position are etched with solder bumps electrode, the third solder mask of top layer silicon wafer is etched with metal electrode, asic chip is welded on the metal electrode of top layer silicon wafer.By using silicon cavity configuration and the secondary wiring of benzocyclobutene, the technique production of three-dimensional microwave multi-chip module is completed in a manner of wafer level, improves production efficiency.

Description

A kind of novel three-dimensional Microwave Multichip Module structure
Technical field
The present invention relates to microwave microelectronics Packaging fields.
Background technique
With the development of microwave and millimeter wave technology, miniaturization, the integrated and multi-functional development as frequency microwave component Direction.In terms of miniaturization, integrated development are mainly reflected in following two: (1) developing multifunction chip, can will include low The microwave functions unit such as noise amplifier, driving amplifier, frequency mixer, filter, switch, numerical-control attenuator, digital phase shifter It is integrated on a microwave monolithic integrated circuit (MMIC), the miniaturization of Lai Shixian system, but which can not achieve different materials The function of matter chip is integrated.(2) three dimension system Integrated Solution is used, by the large scale integrated circuit (ASIC) and difference in component The MMIC etc. of material is placed on different layers, and three-dimensional microwave multi-chip module is then realized by the way of vertical interconnection.
Current three-dimensional microwave Mcm Technique is first that the chips such as MMIC and ASIC and other slice components are highly dense Degree is assembled on LTCC multilager base plate or thin-film multilayer microwave interconnecting substrate, forms 2D multi-chip module, then using hair button or In the Z-axis direction interconnection is laminated in the multi-chip module of different function by the interconnection techniques such as insulator, realizes multilayer vertical interconnection knot Structure forms three-dimensional microwave multi-chip module.There are following disadvantages for this three-dimensional microwave multi-chip module:
(1) it needs that a large amount of maos of buttons are accurately positioned and interconnected, brings very big difficulty to assembly.
(2) it needs to be assembled in metal case, reaches sealing effect, this sealing cap by the way of tin envelope or Laser seal welding Mode is very sensitive to the structure and technological parameter of weld seam, and sealing cap difficulty is big.
(3) current three-dimensional microwave multi-chip module needs individually assemble each component individual, and production efficiency is low Under, be not suitable for mass production.
(4) current three-dimensional microwave multi-chip module solves plus and blowup link and multichannel component using metallic partition Electromagnetic compatibility problem, technical difficulty is big, increase assembly volume.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of novel three-dimensional Microwave Multichip Module structures, using with recessed The silicon substrate cover board and metal salient point of slot realize micro-cavity structure, can be individually electromagnetically shielded to microwave chip;Using silicon chamber Structure and the secondary wiring of benzocyclobutene are completed the technique production of three-dimensional microwave multi-chip module in a manner of wafer level, solved On the basis of component assembly difficulty and sealing problem, production efficiency is improved.
In order to solve the above technical problems, the technical solution used in the present invention is: a kind of novel three-dimensional microwave multi chip piece group Part structure includes base silicon wafer, mmic chip, top layer silicon wafer, asic chip from bottom to top;Corrosion has core in the base silicon wafer Piece mounting groove, and in electroplating surface the first metal layer, mmic chip is bonded in chip by conductive adhesive layer and installs trench bottom, and The upper surface of mmic chip and the upper surface of base silicon wafer in same plane, mmic chip upper surface and base silicon wafer it is upper Successively growth has seal protection layer, second metal layer, the first solder mask on surface, top layer silicon wafer bottom and base silicon wafer The corrosion of chip mounting groove corresponding position has bottom groove, and top layer silicon wafer lower surface, which is successively grown, third metal layer, second Solder mask;Top layer silicon piece upper surface, which is successively grown, the 4th metal layer, third solder mask;Connection is etched in the top layer silicon wafer The through silicon via of 4th metal layer and third metal layer, the base silicon wafer and top layer silicon wafer corresponding position are etched with solder bumps Electrode, and connected base silicon wafer with the solder bumps electrode welding of top layer silicon wafer corresponding position by solder;The top layer silicon The third solder mask of piece is etched with metal electrode, and asic chip is welded on the metal electrode of top layer silicon wafer.
The technical solution advanced optimized is that the corrosion depth of the chip mounting groove is 100 μm, top layer silicon wafer bottom The corrosion depth of portion's groove is 250 μm.
The technical solution advanced optimized is the seal protection layer, the first solder mask, the second solder mask and third welding resistance The material of layer is benzocyclobutene or polyimides.
The technical solution advanced optimized is the seal protection layer with a thickness of 20 ~ 30 μm, first solder mask, the The thickness of two solder masks and third solder mask is 5 μm.
The beneficial effects of adopting the technical scheme are that the present invention is by using silicon cavity configuration and benzo ring The secondary wiring technique of butylene completes the technique production of three-dimensional microwave multi-chip module in a manner of wafer level, is solving component assembly On the basis of difficulty and sealing problem, production efficiency is improved.It is realized by using silicon substrate cover board with groove and metal salient point Micro-cavity structure can individually be electromagnetically shielded microwave chip, solve HGL high gain link and interchannel in multi-chip module Electromagnetic compatibility problem.Semiconductor technology can be used in this structure and full-automatic microwave assembly technology is produced, and improves complex assemblies Production efficiency and yield rate.Meanwhile integrating control chip and microwave chip by the way of three-dimensional stacked, improve system System integrated level, reduces assembly volume.
Detailed description of the invention
Fig. 1 is the integrally-built cross-sectional view of the present invention;
Fig. 2 is the circuit layout schematic diagram in base silicon wafer of the present invention;
Fig. 3 is the cross-sectional view of top layer silicon chip architecture;
Wherein, 1 base silicon wafer, 2 mmic chips, 3 solder bumps electrodes, 4 top layer silicon wafers, 5 through silicon vias, 6 asic chips, 7 first solder masks, 8 second metal layers, 9 seal protection layers, 10 conductive adhesive layers, 11 the first metal layers, 12 third metal layers, 13 Two solder masks, 14 the 4th metal layers, 15 third solder masks, 16 bottom grooves, 17 metal electrodes.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other Embodiment shall fall within the protection scope of the present invention.
As shown in Figure 1, the invention discloses a kind of novel three-dimensional Microwave Multichip Module structures, it from bottom to top include bottom Silicon wafer 1, mmic chip 2, top layer silicon wafer 4, asic chip 6;Corrosion has chip mounting groove in the base silicon wafer 1, and on surface The first metal layer 11 is electroplated, mmic chip 2 is bonded in chip by conductive adhesive layer 10 and installs trench bottom, and mmic chip 2 is upper The upper surface of surface and base silicon wafer 1 in same plane, on the upper surface of mmic chip 2 and the upper surface of base silicon wafer 1 according to It is secondary with seal protection layer 9, second metal layer 8, the first solder mask 7, the core of top layer silicon wafer 4 bottom and base silicon wafer 1 The corrosion of piece mounting groove corresponding position has a bottom groove 16, and 4 lower surface of top layer silicon wafer, which is successively grown, third metal layer 12, the Two solder masks 13;4 upper surface of top layer silicon wafer, which is successively grown, the 4th metal layer 14, third solder mask 15;In the top layer silicon wafer 4 It is etched with the through silicon via 5 of connection the 4th metal layer 14 and third metal layer 12, the base silicon wafer 1 and the corresponding position of top layer silicon wafer 4 It sets and is etched with solder bumps electrode 3, and is by solder that the solder bumps of 4 corresponding position of base silicon wafer 1 and top layer silicon wafer are electric Pole 3 is welded to connect;The third solder mask 15 of the top layer silicon wafer 4 is etched with metal electrode 17, and asic chip 6 is welded on top layer silicon On the metal electrode 17 of piece 4.
The embodiment advanced optimized is that the corrosion depth of the chip mounting groove is 100 μm, 4 bottom of top layer silicon wafer The corrosion depth of groove 16 is 250 μm.
The embodiment advanced optimized is the seal protection layer 9, the first solder mask 7, the second solder mask 13 and third resistance The material of layer 15 is benzocyclobutene or polyimides.
The embodiment advanced optimized is the seal protection layer 9 with a thickness of 20 ~ 30 μm, first solder mask 7, the The thickness of two solder masks 13 and third solder mask 15 is 5 μm.
As shown in Figure 1, structure of the invention is mainly by two layers of silicon wafer, benzocyclobutene medium and solder bumps electrode structure At, wherein base silicon wafer 1 processes chip mounting groove using MEMS bulk silicon technological, and 100 μm of groove depth, be microwave and millimeter wave MMIC core Piece 2 provides support;The corresponding position corrosion bottom groove above microwave and millimeter wave chip 2 of top layer silicon wafer 4,250 μm of groove depth, simultaneously Through silicon via 5 is processed, surface localized metallic is carried out by the metallization pattern of solder bumps electrode 3 and benzocyclobutene top layer Welding, realizes vertical interconnection and electromagnetic shielding, is the asic chip 6 of BGA package or wafer-level packaging above top layer silicon wafer 4.
As shown in Fig. 2, the circuit layout schematic diagram in base silicon wafer of the present invention, microwave monolithic integrated circuit pass through conducting resinl 10 are bonded on 1 substrate of base silicon wafer, table on 1 substrate of microwave and millimeter wave monolithic integrated optical circuit upper surface and base silicon wafer after bonding Face flushes;It is then coated with benzocyclobutene, with a thickness of 20 ~ 30 μm, seal protection is formed to bare chip, by benzocyclobutene On etch through-hole, expose the port I/O of microwave and millimeter wave monolithic integrated optical circuit, by metallization form side metallization Complete secondary wiring;One layer of benzocyclobutene is coated with to realize welding resistance, the electrode of solder bumps is exposed by etching.
As shown in figure 3, top layer silicon chip base cover board is rotten using MEMS bulk silicon technological in the top of corresponding microwave and millimeter wave chip 2 Bottom groove 16 is lost, to eliminate influence of the cover board to bottom microwave chip performance;TSV through hole is etched after erosion grooves, so Front and back sides carry out metalized afterwards, form metallization pattern.After the processing for completing silicon chip, to silicon chip front and back sides point Secondary wiring processing is not carried out, and wherein top layer coats one layer of benzocyclobutene or polyimides first, and dielectric thickness is 5 μm, so Afterwards by etch media layer, secondary wiring pattern is formed after metallization;Bottom coats one layer of benzocyclobutene first or polyamides is sub- Amine, dielectric thickness are 5 μm, etch solder bumps electrode, carry out planting ball reflux on solder bumps electrode, it is convex to form soldered ball Point, bump solder PbSn.
The base silicon wafer of structure of the invention is the supporting layer of microwave chip, and top layer silicon wafer is cover board, top layer cover board and PbSn Soldered ball constitutes miniature cavities structure, is formed and is electromagnetically shielded to microwave and millimeter wave chip, while providing branch for the control chip of top layer Support and the interconnection with base silicon wafer.Process includes the main stream such as MEMS bulk silicon technological, microwave assembly technology and semiconductor lithography process Journey, process flow and conventional semiconductor process are mutually compatible with, and are carried out fragment after completing wafer scale assembly using fully-automatic equipment, are completed The component of batch produces.Technical process design is as follows:
1, the manufacturing process steps of base silicon wafer:
2, the manufacturing process steps of top layer silicon wafer:
3, the manufacturing process steps of base silicon wafer and the assembling of top layer silicon wafer:

Claims (4)

1. a kind of novel three-dimensional Microwave Multichip Module structure, it is characterised in that: from bottom to top include base silicon wafer (1), MMIC Chip (2), top layer silicon wafer (4), asic chip (6);Corrosion has chip mounting groove on the base silicon wafer (1), and in surface electricity It plates the first metal layer (11), mmic chip (2) is bonded in chip by conductive adhesive layer (10) and installs trench bottom, and mmic chip (2) upper surface of upper surface and base silicon wafer (1) is in same plane, in the upper surface and base silicon wafer (1) of mmic chip (2) Upper surface on successively growth have seal protection layer (9), second metal layer (8), the first solder mask (7), the top layer silicon wafer (4) The corrosion of the chip mounting groove corresponding position of bottom and base silicon wafer (1) has bottom groove (16), top layer silicon wafer (4) lower surface Successively growth has third metal layer (12), the second solder mask (13);Top layer silicon wafer (4) upper surface, which is successively grown, the 4th metal layer (14), third solder mask (15);The 4th metal layer (14) of connection and third metal layer (12) are etched in the top layer silicon wafer (4) Through silicon via (5), the base silicon wafer (1) and top layer silicon wafer (4) corresponding position are etched with solder bumps electrode (3), and lead to Solder is crossed to be welded to connect the solder bumps electrode (3) of base silicon wafer (1) and top layer silicon wafer (4) corresponding position;The top layer silicon Piece (4) and the solder bumps electrode (3) surround can be to the microcavity that the mmic chip (2) are individually electromagnetically shielded, institute The third solder mask (15) for stating top layer silicon wafer (4) is etched with metal electrode (17), and asic chip (6) is welded on top layer silicon wafer (4) Metal electrode (17) on.
2. a kind of novel three-dimensional Microwave Multichip Module structure according to claim 1, it is characterised in that: the chip peace The corrosion depth of tankage is 100 μm, and the corrosion depth of top layer silicon wafer (4) bottom groove (16) is 250 μm.
3. a kind of novel three-dimensional Microwave Multichip Module structure according to claim 1, it is characterised in that: the sealing is protected Sheath (9), the first solder mask (7), the second solder mask (13) and third solder mask (15) material be benzocyclobutene or poly- Acid imide.
4. a kind of novel three-dimensional Microwave Multichip Module structure according to claim 3, it is characterised in that: the sealing is protected Sheath (9) with a thickness of 20~30 μm, first solder mask (7), the second solder mask (13) and third solder mask (15) thickness Degree is 5 μm.
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CN109037170A (en) * 2018-07-13 2018-12-18 中国电子科技集团公司第五十八研究所 A kind of radio frequency micro-system integration packaging antenna
CN109904128B (en) * 2019-03-13 2020-12-11 中国科学院微电子研究所 Three-dimensional integrated T/R assembly packaging structure and packaging method based on silicon-based carrier plate
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CN102110673A (en) * 2010-10-27 2011-06-29 中国科学院上海微系统与信息技术研究所 Wafer level MMCM (microwave multichip module) packaging structure using photosensitive BCB (benzocyclobutene) as dielectric layer and method
CN102723306A (en) * 2012-06-28 2012-10-10 中国科学院上海微系统与信息技术研究所 Microwave multi-chip packaging structure using silicon through hole and manufacture method thereof
CN103818874A (en) * 2014-02-12 2014-05-28 北京时代民芯科技有限公司 Novel packaging method of MEMS (Micro-electromechanical Systems) structure and processing circuit integrated system
CN204714514U (en) * 2015-05-28 2015-10-21 华天科技(昆山)电子有限公司 Three-dimensional stacked MEMS package structure
CN205187842U (en) * 2015-11-13 2016-04-27 华天科技(昆山)电子有限公司 MEMS chip package structure
CN205723525U (en) * 2016-06-30 2016-11-23 中国电子科技集团公司第十三研究所 A kind of novel three-dimensional Microwave Multichip Module structure

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