CN105932016A - Dynamic and static current-sharing and multi-chip paralleled power module - Google Patents

Abstract

The invention provides a dynamic and static current-sharing and multi-chip paralleled power module. The dynamic and static current-sharing and multi-chip paralleled power module comprises ceramic copper-clad plates and multiple power chips; various power chips are arranged on the ceramic copper-clad plates having the same structures in one-to-one correspondence; and the ceramic copper-clad plates are arranged in the circumferential direction in an axially symmetrical manner. According to the dynamic and static current-sharing and multi-chip paralleled power module disclosed by the invention, the symmetry of electrical parameters is realized through circular physical symmetrical structure; due to the optimized layout design, various branch parasitic parameters of the multi-chip paralleled power module are minimized; furthermore, distribution of various branch parasitic parameters is basically same; the non-uniform current distribution problem of the multi-chip paralleled module is solved easily; the multi-chip module design method disclosed by the invention can be used for realizing dynamic current-sharing and static current-sharing of the power module better; the capacity utilization rate of the power module is increased; and furthermore, the dynamic and static current-sharing and multi-chip paralleled power module is adaptive to a fast switching process and a high-frequency power electronic converter by reducing the side effects of a parasitic inductance.

Description

The power model of the multi-chip parallel connection of dynamic Current for paralleled

Technical field

The present invention relates to field of power electronics, particularly relate to the power model that the multi-chip of a kind of dynamic Current for paralleled is in parallel.

Background technology

In recent years, power electronic devices is in grid-connected power generation system, and motor drives and Electrified Transmission aspect obtains extensively Application.Along with industrial quarters proposes the highest demand to power electronics, the switching frequency of power electronic devices is increasingly High with hoisting power density, but power model switching rate based on Si (silicon) device has basically reached physics limit, because of This, industrial quarters starts eye is invested the broad stopband device such as SiC (carborundum), GaN (gallium nitride).Compare with Si device, wide taboo Carrying material electric, thermal characteristic is more excellent, SiC MOSFET (mos field effect transistor) relatively Si IGBT has higher thermal conductivity factor, blocking voltage and working junction temperature, and, SiC MOSFET does not exist in turn off process and drags Tail current, can substantially reduce switching loss, improves switching speed.The characteristic of these excellences makes the use model of SiC MOSFET Enclose increasingly wider, but, due to manufacturing process and the restriction of cost, the through-current capability of single SiC MOSFET chip is only 50- 100A, thus in the high-power applications occasion such as Electrified Transmission, new-energy grid-connected, generally require multiple discrete device in parallel, or Use the power model of multi-chip parallel-connection structure, PCB circuit during existing discrete device parallel connection and multi-chip parallel module DBC substrate be typically all asymmetrical physical arrangement, inevitably cause loop parasitic parameter inconsistent, thus not The problem causing current-unbalance on same device or chip, the switching frequency of SiC device is higher in addition, the rate of change of electric current Bigger, the difference of parasitic parameter may bring the current-unbalance bigger than Si device, including the quiescent current after conducting not Equilibrium, and the dynamic current in switching process is unbalanced.Unbalanced electric current can make device produce the most reciprocity loss, hold Closing speed, voltage and current stress, cross the maximum device of blow stress or chip is in the link that whole system is the weakest, electric current is not The service life reduction and crash rate that easily cause whole module are risen by equalization problem.

For current-unbalance problem present in multiple SiC MOSFET and other device parallel process, existing document Start with from the dispersiveness of device itself, have studied different parameters to the impact of parallel current-sharing and countermeasure thereof.Existing document Analysis show: the static state of device, dynamic current equilibrium can be had directly by the parameters such as device on-resistance Ron, threshold voltage vt h Impact.Additionally, the pin of device encapsulation can introduce drain electrode and source electrode stray inductance Ld and Ls equally, the dispersiveness of these parameters is same Sample influences whether the current balance of devices in parallel.Due to the asymmetric layout between multiple devices, also result in main loop of power circuit In electric parameter inconsistent, influence whether that the static state between multiple device and dynamic current are unbalanced equally.

The parameter unbalance of power device is determined by production technology, is inevitable, and the parameter of loop of power circuit is not Unanimously cause, by optimizing layout, so that the parasitic parameter of main loop of power circuit to the greatest extent may be used often caused by layout is unreasonable Can equiblibrium mass distribution.Being found by Finite Element Simulation Analysis in prior art: in multi-chip parallel module, different chips are to module The parasitic parameter difference of each output electrode is relatively big, can form serious static state and dynamic current deviation.Ask to solve this Topic, has research to reduce the parasitic parameter inhomogeneities between different current branch by the method that source inductance compensates, promotes The current-sharing effect of module, but this way have also been introduced extra stray inductance, be likely to result in the increase of switching loss.Pin Deficiency to existing layout, also has some technology to propose some novel DBC layout methods to reduce between parasitic parameter Lack of uniformity, but these novel layouts do not ensure that between each branch road it is full symmetric, thus still can not keep away The meeting exempted from produces equal flow problem.

Summary of the invention

In view of this, the present invention provides the power model of the multi-chip parallel connection of a kind of dynamic Current for paralleled, to solve above-mentioned asking Topic.

The power model that the multi-chip of the dynamic Current for paralleled that the present invention provides is in parallel, including ceramic copper-clad plate and power core Sheet, described power chip quantity is multiple, each power chip one_to_one corresponding is arranged on the ceramic copper-clad plate that structure is identical, Ceramic copper-clad plate is peripherally disposed in axial symmetry mode.

Further, described ceramic copper-clad plate is circular configuration, and the power chip of each current branch of upper and lower half-bridge respectively occupies One sector region, the plurality of power chip is parallel-connection structure, and the chip that each brachium pontis is connected in parallel is driven by same Dynamic device drives.

Further, the DC side of power model and the structure of AC terminal are laminated bus bar structure.

Further, described ceramic copper-clad plate is the ceramic insulating material close with power chip thermal coefficient of expansion, bonding line For aluminum steel.

Further, the surface structure of described ceramic copper-clad plate is reduced to rectangular configuration, and obtains letter by equation below The conductor parasitic inductance of structure after change:

$L=\frac{{\mathrm{\μ}}_{0}a}{2\mathrm{\π}}(ln\frac{2a}{b+d}+0.5)$

$R=\mathrm{\ρ}\frac{a}{bd}$

Wherein, L is conductor inductance, and a is conductor length, and b is the width of conductor, and d is the thickness of conductor, and ρ is the electricity of conductor Resistance rate, μ₀=4 π × 10^-7H/m, space permeability.

Further, the not closed-loop path of arbitrary shape is equivalent to by a closed-loop path contrary with a sense of current Endless long straight conductor forms, by equation below acquisition stray inductance estimate:

$L=\frac{{\mathrm{\μ}}_0}{2\mathrm{\π}}\[Cln\left(S\right)-l\left(ln\right(2l)-1)\]\×{10}^{-3}$

Wherein, L is stray inductance, and l is conductor length, and r is wire radius, and C is the girth in loop, and S is the area in loop；

Exact value by the stray inductance of Finite Element Method acquisition module.

Further, in power model, each switch connects one group of power chip, and often group includes three power being connected in parallel Chip, the power chip of different groups is with the most alternate setting of axial symmetry mode, and described power chip is SiC MOSFET Chip or IGBT.

Further, the symmetry of power model is judged by equation below:

$U_L=\frac{\sqrt{\underset{j=1}{\overset{3}{\Σ}}{(L_j-\stackrel{\‾}{L})}^2}}{\stackrel{\‾}{L}},$

Wherein, U_LShow that the most greatly the distribution of module parasitic parameter is the most uneven, work as U_LWhen=0, module is full symmetric；L_jFor not With the inductance value of branch road,For overall inductance mean value

Beneficial effects of the present invention: the present invention realizes the symmetry of electric parameter by circular physical symmetry structure, utilizes Analytic method and Finite Element Method have carried out the extraction of parasitic parameter, and in each parallel branch, electric parameter is symmetrical, it is possible to more The good dynamic current equalizing realizing power model and Current for paralleled, make multi-chip power model each branch road parasitic parameter in parallel and CURRENT DISTRIBUTION is basically identical, contributes to solving the equal flow problem of multi-chip parallel module, it is possible to preferably realize power model Dynamic current equalizing and Current for paralleled, with the utilization rate of hoisting power module capacity.And it is by reducing the side effect of stray inductance, suitable Answer high-speed switch process and high-frequency power electronic converter.

Accompanying drawing explanation

The invention will be further described with embodiment below in conjunction with the accompanying drawings:

Fig. 1 is the multi-chip parallel module equivalent schematic diagram of the present invention.

Fig. 2 is the multi-chip parallel module cross sectional representation of the present invention.

Fig. 3 is the multi-chip parallel module DBC symmetric configuration schematic diagram of the present invention.

Fig. 4 is that power model of the present invention comprises the structural representation driven with power terminal.

Fig. 5 is the example schematic diagram that the multi-chip parallel module analytic method of the present invention seeks stray inductance.

Dynamic characteristic test schematic diagram when Fig. 6 is the three chip parallel connection of the present invention.

Fig. 7 is dynamic current equalizing effect and the contrast of the asymmetric module of traditional parameters of the three chip parallel modules of the present invention Figure, a is the dynamic current equalizing effect of the asymmetric module of traditional parameters, and b is the dynamic current equalizing effect of the three chip parallel modules of the present invention Really.

Fig. 8 is Current for paralleled effect and the contrast of the asymmetric module of traditional parameters of the three chip parallel modules of the present invention Figure, a is the Current for paralleled effect of the asymmetric module of traditional parameters, and b is the Current for paralleled effect of the three chip parallel modules of the present invention Really.

Detailed description of the invention

The invention will be further described with embodiment below in conjunction with the accompanying drawings: Fig. 1 is the multi-chip parallel module of the present invention Equivalent circuit diagram.Fig. 2 is the multi-chip parallel module cross sectional representation of the present invention.Fig. 3 is multi-chip the gang mould of the present invention Block DBC symmetric configuration schematic diagram.Fig. 4 is that power model of the present invention drives and power terminal structural representation.Fig. 5 is the present invention Multi-chip parallel module analytic method seeks the example schematic diagram of stray inductance.Dynamic characteristic when Fig. 6 is the three chip parallel connection of the present invention Test philosophy figure.Fig. 7 is the right of the dynamic current equalizing effect of the three chip parallel modules of the present invention and the asymmetric module of traditional parameters Than figure, a is the dynamic current equalizing effect of the asymmetric module of traditional parameters, and b is the dynamic current equalizing of the three chip parallel modules of the present invention Effect.Fig. 8 is Current for paralleled effect and the comparison diagram of the asymmetric module of traditional parameters, a of the three chip parallel modules of the present invention For the Current for paralleled effect of the asymmetric module of traditional parameters, b is the Current for paralleled effect of the three chip parallel modules of the present invention.

As in figure 2 it is shown, the power model that the multi-chip of dynamic Current for paralleled in the present embodiment is in parallel, including ceramic copper-clad plate And chip, drive terminal and power terminal, each chip one_to_one corresponding is arranged on the ceramic copper-clad plate that structure is identical, and pottery covers Copper coin is peripherally disposed in axial symmetry mode.As it is shown on figure 3, the present embodiment uses the multi-chip of novel physical symmetry also The power model of connection, is realized the symmetry of electric parameter, utilizes analytic method and finite element side by circular physical symmetry structure Method has carried out the extraction of parasitic parameter.When the present embodiment is by setting up multi-chip parallel connection, the asymmetric simulation model of parasitic parameter, Analyzing the parsing relation of CURRENT DISTRIBUTION and parasitic parameter, analysis result shows that the present embodiment can make electrically to join in parallel branch Number symmetry, it is possible to preferably realize dynamic current equalizing and the Current for paralleled of power model.

Ceramic copper-clad plate in the present embodiment is sector structure, and the plurality of chip is parallel-connection structure, and (chip is SiC MOSFET, GaN HEMT, Si IGBT, Si IGCT or other device for power switching) and be connected with same driver respectively, merit The DC side of rate module and the structure of AC terminal are laminated bus bar structure.The present embodiment as a example by SiC MOSFET, module In each brachium pontis constitute be three SiC MOSFET (1200V, 40A, Cree CPM2-1200-0040B) and three SiC Xiao Te Based diode (1200V, 20A, Cree CPW4-1200-S020B) is in parallel, as shown in Figure 4, and the SiC MOSFET being connected in parallel Triggered by same driving signal.

In the present embodiment, ceramic copper-clad plate is the aluminium nitride ceramics insulating materials close with SiC thermal coefficient of expansion, bonding Line is aluminum steel, and the present embodiment uses a and that SiC thermal coefficient of expansion is close direct copper plate (DBC), the DBC's of current main flow Ceramic insulating material has aluminum oxide (Al₂O₃), aluminium nitride (AlN) beryllium oxide (BeO) and silicon nitride (Si₃N₄).Their main property Can be as shown in table 1.In above-mentioned four kinds of materials, Al₂O₃It is that price is generally the least expensive, is also that current commercialization module uses at most Ceramic insulating material, but its physical property is relatively poor.In all candidate materials, the heat conductivility of beryllium oxide is best, But owing to it is poisonous to human body, typically not in use by it as ceramic insulating material.The heat conductivility of AlN is the 5-of aluminum oxide 6 times, and thermal coefficient of expansion is also more nearly SiC (thermal coefficient of expansion of SiC is 3ppm/K), is a kind of well selection.Institute Have in material, Si₃N₄Thermal coefficient of expansion closest to SiC, and shear strength is the most maximum, under the same terms, it is contemplated that the life-span also can The longest, but Si₃N₄Price is far above other materials, and thermal conductivity factor is also much lower than other materials and AlN.Therefore, Considering price, performance etc., the present embodiment selection AlN is as ceramic insulating material, due to radius and the current capacity of aluminum steel More much higher than gold thread, and aluminum steel has a longer thermal cycle life than gold thread, the present embodiment uses aluminum steel as bonding line.

Table 1

In the present embodiment, DBC copper base is a sector, it is impossible to is directly suitable for formula and calculates its stray inductance, this Embodiment is simplified to its stray inductance of calculating that then a rectangle utilizes the stray inductance formula approximation of Guan Bi conductor. After being simplified to rectangle, formula is utilized to calculate inductance.

$\begin{array}{cc}L=\frac{{\mathrm{\μ}}_{0}a}{2\mathrm{\π}}(ln\frac{2a}{b+d}+0.5)& R=\mathrm{\ρ}\frac{a}{bd}\end{array}---\left(1\right)$

Wherein, L: conductor inductance [H], a: conductor length [m], the width [m] of b: conductor, the thickness [m] of d: conductor, ρ: lead The resistivity [Ω m] of body, μ₀=4 π × 10^-7H/m, space permeability.

As a example by an irregular DBC copper base, if its a size of one internal diameter 35mm, external diameter 50mm, 54 ° of angle of circumference Sector, thickness is 0.635mm.Just it can be equivalent to long 40mm, the rectangle of wide 15mm, utilize formula (1) to calculate its electricity Inductance value is:

$L=\frac{{\mathrm{\μ}}_{0}l}{2\mathrm{\π}}(ln\frac{2l}{b+c}+0.5)=\frac{4\mathrm{\π}\×{10}^{-7}\×40\×{10}^{-3}}{2\mathrm{\π}}\×(\ln \frac{2\×40\×{10}^{-3}}{15.6\×{10}^{-3}}+0.5)=17.08nH$

There is certain error between method for simplifying and the inductance value of reality, especially calculate the shape of object and rectangular Shape has when significantly distinguish, so that method is sought in the parsing seeking a kind of stray inductance.

In the present embodiment, the not closed-loop path of arbitrary shape is equivalent to by a closed-loop path and a sense of current Contrary endless long straight conductor composition, the inductance computing formula of Guan Bi rectangular coil is as follows:

$L=\frac{{\mathrm{\μ}}_{0}l}{\mathrm{\π}}\[-2(a+b)+2\sqrt{a^2+b^2}+aln\left(\frac{b}{d}\right)+bln\left(\frac{a}{d}\right)+a\left(ln\frac{b}{a+\sqrt{a^2+b^2}}\right)+b\left(ln\frac{a}{b+\sqrt{a^2+b^2}}\right)\]\×{10}^{-3}---\left(2\right)$

Wherein, L: conductor inductance [H], a, b: the rectangular length of side [mm], d: conductor thickness [mm].

The inductance value calculation formula of long straight conductor without line length is:

$L=\frac{{\mathrm{\μ}}_{0}l}{2\mathrm{\π}}(ln\frac{2l}{r}-1)\×{10}^{-3}---\left(3\right)$

Wherein, L: lead inductance [H], l: conductor length [mm], r: wire radius [mm].

By formula (2), it is assumed that d < < a, b, then the self-induction closing rectangular coil is:

$L\&ap;\frac{{\mathrm{\&mu;}}_0}{\mathrm{\&pi;}}(w+h)ln\left(wh\right)=\frac{{\mathrm{\&mu;}}_0}{2\mathrm{\&pi;}}Cln\left(S\right)\&times;{10}^{-3}---\left(4\right)$

Wherein, C=2 (w+h), unit mm, is the girth in loop.S=wh, for square measure mm in loop².Loop is always posted Raw inductance and variable Cln (S) linear correlation.

By the inductance computing formula of endless long straight conductor, it is assumed that r < < l, unit mm, the then self-induction of endless long straight conductor Computing formula is:

$L=\frac{{\mathrm{\&mu;}}_{0}l}{2\mathrm{\&pi;}}\&lsqb;ln\left(2l\right)-1\&rsqb;\&times;{10}^{-3}---\left(5\right)$

Thus the stray inductance value that can finally try to achieve the not closed-loop path of an arbitrary shape is:

$L=\frac{{\mathrm{\&mu;}}_0}{2\mathrm{\&pi;}}\&lsqb;Cln\left(S\right)-l\left(ln\right(2l)-1)\&rsqb;\&times;{10}^{-3}---\left(6\right)$

An example schematic diagram as shown in Figure 5, in the present embodiment, module be one by parallel single-phase of three core assembly sheets Bridge module, different according to the distance with lead-out terminal, 3 loops, respectively loop 1, loop 2 and loop 3, root can be divided into According to formula (6)

The parameter in loop 1 is: w=11.18mm, h=17.36mm, l=17.36mm

It is calculated:

C=2 (w+h)=57.08mm, S=wh=194.08mm²

$L=\frac{{\mathrm{\&mu;}}_0}{2\mathrm{\&pi;}}\&lsqb;Cln\left(S\right)-l\left(ln\right(2l)-1)\&rsqb;\&times;{10}^{-3}=\&lsqb;57.08\&times;ln\left(194.08\right)-17.36\&times;\left(ln\right(34.72)-1)\&rsqb;\&times;\frac{4\mathrm{\&pi;}\&times;{10}^{-7}}{2\mathrm{\&pi;}}\&times;{10}^{-3}=51.30nH$

The parameter in loop 2 is: w=23.04mm, h=17.36mm, l=17.36mm.

The parameter in loop 3 is w=32.96mm, h=17.36mm, l=17.36mm.

Calculate the stray inductance in loop 2 is 87.66nH, the stray inductance in loop 3 is 122.40nH

The present embodiment uses solder technology, and the welding material of current main flow is as shown in table 2.Although the solder of lead base compares auri Solder stability more preferable, it is contemplated that the harm that human body may be produced by lead, used the power model of solder containing pb Fewer and feweri, consider performance and price, the present embodiment uses gold-tin alloy (Au80-Sn20) as solder.

Table 2

Multi-chip parallel module electrical characteristic includes the symmetry of each current branch, SiC higher for switching frequency MOSFET, the symmetry between different current branch is more important, but existing SiC module major part or the tradition used The layout method of Si, bring the asymmetry of parameter,

The symmetry of SiC MOSFET chip is judged by equation below:

U_LShow that the most greatly the distribution of module parasitic parameter is the most uneven, work as U_LWhen=0, module is the most right Claim；

Wherein, L_jFor the inductance value of different branch, L is overall inductance mean value.

The present embodiment takes the round-shaped placement scheme as DBC, and the merit of the traditional structure of equal-wattage grade Rate module is compared, and the use of circular symmetric structure is greatly improved the parameter consistency between different branch, and parasitic parameter is maximum Gap between value and minimum of a value is only 2%.Consider to drive the modular structure of signal and power output terminal as shown in Figure 4, directly The structure of stream side and AC terminal all uses the structure of laminated bus bar to reduce total stray inductance value in loop, demonstrate,proves through experiment Different current branch in bright the present embodiment are also physical symmetry, and its parasitic parameter is the most basically identical.

As shown in Figure 6, three MOSFET in parallel are triggered by same driving signal, and they corresponding source inductance are respectively For L_s1、L_s2And L_s3。

During MOSFET turns on, there is a following relation:

i_D=g_fs(v_GS-V_th) (7)

$v_{GS}=V_{driver}-i_G{R}_G-L_S\frac{{\mathrm{di}}_S}{dt}---\left(8\right)$

In formula, g_fsFor the mutual conductance of power device, v_GSFor the voltage being applied between gate pole and source electrode, V_thFor MOSFET's Threshold voltage.V_driverFor driving output voltage, i_G、R_GFor driving electric current and driving resistance, L_S、i_SFor source inductance and flow through source The electric current of pole inductance.

L_sBy to the voltage v being applied between device gate pole and source electrode_GSNegative-feedback affect the switching characteristic of system.By The least, in this case in the electric current of gate pole, it is believed that source current i_sWith drain current i_DIt is consistent.By formula (7), (8) Can obtain:

$i_{Dj}-i_{Dk}=g_{fs}(L_{sk}-L_{sj})\frac{{\mathrm{di}}_L}{2dt}---\left(9\right)$

Formula (9) shows, distribution and the source inductance of dynamic current are closely related, and along with the increasing of source inductance gap Greatly, the distribution gap of electric current also will increase accordingly.Source inductance is in drive circuit, and its asymmetric meeting is by driving electricity Pressure v_GSImpact show on the skewness of dynamic current.

Source inductance is owing to having negative feedback to gate voltage signal, so transient current is distributed the biggest shadow Ringing, drain electrode inductance is then more and affects the distribution of quiescent current.

$\left\{\begin{array}{c}{i}_{D1}+i_{D2}+i_{D3}=i_L\\ L_{d1}\frac{{\mathrm{di}}_{D1}}{dt}+R_{on1}{i}_{D1}=L_{d2}\frac{{\mathrm{di}}_{D2}}{dt}+R_{on2}{i}_{D2}\end{array}\right.---\left(10\right)$

In formula (10), R_onFor the conducting resistance of power device, L_d、i_dFor drain electrode inductance and the electric current flowing through source inductance. The parameter assuming all chips is all consistent, so having:

R_on1=R_on2=R_on3=R_on

$i_{D1}-i_{D2}\&ap;\frac{L_{d2}-L_{d1}}{2R_{on}}\frac{U_{DC}}{L}$

In the present embodiment, in power model, each switch connects one group of SiC MOSFET chip, and often group includes three also The SiC MOSFET chip that connection connects, the SiC MOSFET chips of different groups with the most alternate setting of axial symmetry mode, A three chips dipulse test circuit in parallel has been built under SiMetrix platform, as it is shown in figure 5, to each different branch On electric current i_D1,i_D2,i_D3Have:

$\left[\begin{array}{c}{i}_{D1}\\ i_{D2}\\ i_{D3}\end{array}\right]=g_{fs}\left[\begin{array}{c}{V}_{driver}-i_G{R}_G-V_{th}-L_{s1}\frac{{\mathrm{di}}_{D1}}{dt}-L\frac{{\mathrm{di}}_L}{dt}\\ V_{driver}-i_G{R}_G-V_{th}-L_{s2}\frac{{\mathrm{di}}_{D2}}{dt}-L\frac{{\mathrm{di}}_L}{dt}\\ V_{driver}-i_G{R}_G-V_{th}-L_{s3}\frac{{\mathrm{di}}_{D3}}{dt}-L\frac{{\mathrm{di}}_L}{dt}\end{array}\right]---\left(11\right)$

$\left\{\begin{array}{c}{i}_{D1}-i_{D2}=g_{fs}\&lsqb;L_{s2}\frac{{\mathrm{di}}_{D2}}{dt}-L_{s1}\frac{{\mathrm{di}}_{D1}}{dt}\&rsqb;\\ i_{D2}-i_{D3}=g_{fs}\&lsqb;L_{s3}\frac{{\mathrm{di}}_{D3}}{dt}-L_{s2}\frac{{\mathrm{di}}_{D2}}{dt}\&rsqb;\\ i_{D1}-i_{D3}=g_{fs}\&lsqb;L_{s3}\frac{{\mathrm{di}}_{D3}}{dt}-L_{s1}\frac{{\mathrm{di}}_{D1}}{dt}\&rsqb;\end{array}\right.---\left(12\right)$

By formula (11), (12) it can be seen that the distribution of electric current and stray inductance between multi-chip parallel module different branch Size have much relations, the present embodiment uses symmetric form power model, have employed after symmetrical structure carries out DBC layout, Power model each branch road parasitic parameter and CURRENT DISTRIBUTION that multi-chip is in parallel are substantially coincident, solve multi-chip gang mould The equal flow problem of block difference current branch.

Finally illustrating, above example is only in order to illustrate technical scheme and unrestricted, although with reference to relatively The present invention has been described in detail by good embodiment, it will be understood by those within the art that, can be to the skill of the present invention Art scheme is modified or equivalent, and without deviating from objective and the scope of technical solution of the present invention, it all should be contained at this In the middle of the right of invention.

Claims (8)

1. the power model that the multi-chip of a dynamic Current for paralleled is in parallel, it is characterised in that: include ceramic copper-clad plate and power core Sheet, described power chip quantity is multiple, and each power chip one_to_one corresponding is arranged on the ceramic copper-clad plate that structure is identical, pottery Porcelain copper-clad plate is peripherally disposed in axial symmetry mode.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 1 is in parallel, it is characterised in that: described pottery Copper-clad plate is circular configuration, and the power chip of each current branch of upper and lower half-bridge respectively occupies a sector region, the plurality of merit Rate chip is parallel-connection structure, and the chip that each brachium pontis is connected in parallel is by same driver drives.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 2 is in parallel, it is characterised in that: power model DC side and the structure of AC terminal be laminated bus bar structure.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 1 is in parallel, it is characterised in that: described pottery Copper-clad plate is the ceramic insulating material close with power chip thermal coefficient of expansion, and bonding line is aluminum steel.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 1 is in parallel, it is characterised in that: by described pottery The surface structure of porcelain copper-clad plate is reduced to rectangular configuration, and by the conductor parasitic inductance of structure after equation below acquisition simplification:

$L=\frac{{\mathrm{\&mu;}}_{0}a}{2\mathrm{\&pi;}}(ln\frac{2a}{b+d}+0.5)$

$R=\mathrm{\&rho;}\frac{a}{bd}$

Wherein, L is conductor inductance, and a is conductor length, and b is the width of conductor, and d is the thickness of conductor, and ρ is the resistivity of conductor, μ₀=4 π × 10^-7H/m, space permeability.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 5 is in parallel, it is characterised in that: by arbitrary shape The endless long straight conductor that the not closed-loop path of shape is equivalent to by a closed-loop path is contrary with sense of current forms, and passes through Equation below acquisition stray inductance estimate:

$L=\frac{{\mathrm{\&mu;}}_0}{2\mathrm{\&pi;}}\&lsqb;Cln\left(S\right)-l\left(ln\right(2l)-1)\&rsqb;\&times;{10}^{-3}$

Wherein, L is stray inductance, and l is conductor length, and r is wire radius, and C is the girth in loop, and S is the area in loop；

Exact value by the stray inductance of Finite Element Method acquisition module.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 1 is in parallel, it is characterised in that: power model In each switch connect one group of power chip, often group includes three power chips being connected in parallel, the power chips of different groups with The most alternate setting of axial symmetry mode, described power chip is SiCMOSFET chip or IGBT.

The power model that the multi-chip of dynamic Current for paralleled the most according to claim 1 is in parallel, it is characterised in that: by as follows Formula judges the symmetry of power model:

$U_L=\frac{\sqrt{\underset{j=1}{\overset{3}{\&Sigma;}}{(L_j-\stackrel{\&OverBar;}{L})}^2}}{\stackrel{\&OverBar;}{L}},$

Wherein, U_LShow that the most greatly the distribution of module parasitic parameter is the most uneven, work as U_LWhen=0, module is full symmetric；L_jProp up for difference The inductance value on road,For overall inductance mean value.