CN107768340A - A kind of power model ceramic lining plate - Google Patents
A kind of power model ceramic lining plate Download PDFInfo
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- CN107768340A CN107768340A CN201710827140.XA CN201710827140A CN107768340A CN 107768340 A CN107768340 A CN 107768340A CN 201710827140 A CN201710827140 A CN 201710827140A CN 107768340 A CN107768340 A CN 107768340A
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/495—Lead-frames or other flat leads
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Abstract
The invention discloses a kind of power model ceramic lining plate, including：The first metal layer, second metal layer and the 3rd metal level being sequentially arranged from top to bottom.The first ceramic layer is disposed between the first metal layer and second metal layer, the second ceramic layer is disposed between second metal layer and the 3rd metal level.The first metal layer is arranged to the emitter region being isolated from each other and control signal terminal region, and second metal layer is arranged to collector area.Second metal layer can also further extend to the upper surface of the first ceramic layer by the through hole being arranged in the first ceramic layer.In liner plate upper surface, through-thickness offers the groove for being respectively used to install the first power chip and the second power chip, and groove extends to second metal layer from the first metal layer.The present invention can solve the problem that existing power model ceramic lining plate circuits interconnection structure stray inductance is big, and chip welding needs to use welding tooling, and liner plate front metal layer is the binder course of forceful electric power and light current, and more complicated technical problem is interconnected between liner plate.
Description
Technical field
The present invention relates to power semiconductor manufacturing field, more particularly, to a kind of power model ceramic lining plate structure.
Background technology
Liner plate 10 be power semiconductor modular (such as：IGBT module) basic cell structure, play electric interconnection, electrically
The multiple actions such as insulation, heat dissipation channel.As shown in Figure 1, ceramic lining plate uses 3 layers to traditional IGBT module liner plate vertical structure
Structure, i.e. 1 layer of ceramic layer (ceramic layer 12) and 2 layers of metal level (front metal layer 11 and metal layer on back 13), pass through ceramic layer
Metal level is isolated.The effect of ceramic layer is insulation, prevents high-voltage breakdown, while also function to thermolysis.Front metal
The effect of layer is to realize that circuit interconnects, and usual second power chip and the first power chip are positioned over the front metal layer of liner plate 10
On 11, the electric interconnection of chip chamber is completed by way of wire bonding.Metal layer on back 13 is generally connected with heat sink, and
Matching because the thermal linear expansion coefficient between heat sink and ceramics is inconsistent and caused by stress.The front metal on the two sides of ceramic layer 12
Layer 11 and metal layer on back 13 realize close connection by the techniques such as sintering, active soldering, sputtering and ceramic layer 12.
Traditional IGBT module generally comprises multiple liner plates 10, and the current path of liner plate 10 all concentrates on front metal
On layer 11, the access lane of electric current can not possibly be overlapping, causes stray inductance not cancel out each other, so cause stray inductance compared with
Greatly.Stray inductance influences overvoltage of the IGBT module in switching process, bigger according to U=L*di/dt principle, stray inductance
Then overvoltage is just big.Stray inductance can also cause the uneven stream of chip between liner plate 10, cause chip current path stray inductance big
Chip distribution electric current it is small, and chip current path stray inductance it is small chip distribution electric current it is big.Chip is because of size of current
The inconsistent temperature difference that will produce chip chamber, so as to influence the uniformity of chip performance.
Meanwhile traditional power semiconductor modular carry out liner plate 10 welding when, it is necessary to using positioning tool, by weld tabs
It is fixed on chip on liner plate 10.Weld tabs links together chip and front metal layer 11 by the process melted and cooled down,
Then welding tooling is removed again, therefore welding efficiency is extremely low.The top of layer is connected with chip, and bottom connects with front metal layer 11
Touch, i.e., chip layer is protruded from front metal layer 11, because the thermal linear expansion coefficient of storeroom is inconsistent, causes layer all
The stress on side is larger.
The content of the invention
In view of this, it is an object of the invention to provide a kind of power model ceramic lining plate, to solve existing power model
Ceramic lining plate circuits interconnection structure stray inductance is big, and chip welding needs to use welding tooling, and liner plate front metal layer is forceful electric power
With the binder course of light current, more complicated technical problem is interconnected between liner plate.
In order to realize foregoing invention purpose, the present invention specifically provides a kind of technology realization side of power model ceramic lining plate
Case, a kind of power model ceramic lining plate, the liner plate include：The first metal layer that is sequentially arranged from top to bottom, second metal layer
With the 3rd metal level, the first ceramic layer, second metal are disposed between the first metal layer and the second metal layer
The second ceramic layer is disposed between layer and the 3rd metal level.The first metal layer is arranged to the emitter region being isolated from each other
With control signal terminal region, the second metal layer is arranged to collector area.In the liner plate upper surface, through-thickness opens up
There is the groove for being respectively used to install the first power chip and the second power chip, the groove extends to from the first metal layer
The second metal layer.
The present invention also specifically provides the technic relization scheme of another power model ceramic lining plate, a kind of power model pottery
Ceramic liner plate, the liner plate include：The first metal layer, second metal layer and the 3rd metal level being sequentially arranged from top to bottom, it is described
The first ceramic layer, the second metal layer and the 3rd metal level are disposed between the first metal layer and the second metal layer
Between be disposed with the second ceramic layer.The first metal layer is arranged to the emitter region being isolated from each other and control signal terminal region.
The second metal layer is arranged to collector area, through hole of the second metal layer also by being arranged in first ceramic layer
Extend to the upper surface of first ceramic layer.In the liner plate upper surface, through-thickness, which offers, is respectively used to installation first
The groove of power chip and the second power chip, the groove extend to the second metal layer from the first metal layer.
Preferably, when the first power chip on the liner plate and the second power chip work, described first
Form current path between metal level and the second metal layer, the current direction in the first metal layer and second gold medal
Belong to the current direction in layer on the contrary, with by mutual inductance effect offset the first metal layer with it is spuious in the second metal layer
Inductance, so as to realize the low sense of the liner plate.
Preferably, the bottom of the groove is second metal layer, the size of the groove in first power chip or
Unilateral 0.1~the 1mm that stretches out on the basis of second power chip size.
Preferably, the control signal terminal region includes emitter stage control terminal sub-district and the gate pole control terminal being isolated from each other
Area, the emitter stage control terminal sub-district are connected to the emitter region by lead, and the gate pole control terminal sub-district passes through lead
It is connected to the First Transition area.
Preferably, the first metal layer is additionally operable to realize the interconnection between multiple liner plates.
Preferably, the first metal layer is arranged to emitter region, control signal terminal region and the first mistake being isolated from each other
Area is crossed, the gate pole of second power chip is connected to the First Transition area by lead.
Preferably, the first metal layer is arranged to emitter region, control signal terminal region, the First Transition being isolated from each other
Area and the second transition region, realize lead in the First Transition area and the gate pole control terminal sub-district by second transition region
Between transition connection.
Preferably, the liner plate includes two control signal terminal regions and two the second transition regions, the emitter region, collection
Electrode district, control signal terminal region, First Transition area and the second transition region axisymmetricly structure distribution on the liner plate.
Preferably, first power chip is FRD chips, and second power chip is igbt chip.
Preferably, first power chip is SBD chips, and second power chip is MOSFET chips.
Preferably, the groove that two or more is used to install first power chip, and two are offered on the liner plate
The groove for being used to install second power chip corresponding with the first power chip quantity more than individual.The bottom of the groove
Portion is second metal layer, and the groove realizes first power chip, the second power chip and second gold medal for placement
Belong to the weld tabs of layer welding.The technical scheme of the power model ceramic lining plate provided by implementing the invention described above, have has as follows
Beneficial effect：
(1) ceramic lining plate realizes the connection of upper and lower metal layer region in the present invention, current path structure in a ring, current collection
The metal level of pole and emitter stage forms mutual inductance, can greatly reduce the stray inductance of liner plate；
(2) there is groove structure on liner plate in the present invention, the welding positioning as chip weld tabs technique, is advantageous to batch
Intellectualized operation, and process efficiency is high, chip will not produce drift, and the chip that can be applied to different sizes welds；
(3) in the present invention liner plate thickness increase, do not influence the heat dissipation path of chip, deflection is small in technical process, has
The uniformity of stability and properties of product beneficial to technique；
(4) the control terminal wiring of liner plate is flexible in the present invention, and position can adjust, and the first metal layer (removes colelctor electrode
Welding region) use can be interconnected as the PCB in module encapsulation, packaging efficiency is substantially increased, reliability further improves.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
There is the required accompanying drawing used in technology description to be briefly described.It should be evident that drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other embodiments are obtained according to these accompanying drawings.
Fig. 1 is the structural representation of power semiconductor modular ceramic lining plate in the prior art；
Fig. 2 is a kind of structural representation of specific embodiment of power model ceramic lining plate of the present invention；
Fig. 3 be in Fig. 2 A-A to cross-sectional view；
Fig. 4 is a kind of circuits interconnection structure schematic diagram of specific embodiment of power model ceramic lining plate of the present invention；
Fig. 5 is the structure cut-away view of B-B direction in Fig. 4；
Fig. 6 is the structure cut-away view of power model ceramic lining plate another kind specific embodiment of the present invention；
In figure：1- the first metal layers, 2- second metal layers, the metal levels of 3- the 3rd, the ceramic layers of 4- first, the ceramics of 5- second
Layer, 6- grooves, 7- leads, 8- gate poles, 9- weld tabs, 10- liner plates, 11- front metal layers, 12- ceramic layers, 13- metal layer on back,
14- emitter stage control terminal sub-districts, 15- gate pole control terminal sub-districts, 16- through holes, the power chips of 20- first, 30- the second power cores
Piece, A- emitter regions, B- collector areas, C- controls polar region, D- First Transitions area, the transition regions of E- second.
Embodiment
For the sake of quoting and understanding, by the technical term hereinafter used, write a Chinese character in simplified form or abridge and be described below：
FRD：Fast Recovery Diode, the abbreviation of fast recovery diode；
IGBT：Insulated Gate Bipolar Transistor, a kind of full-control type power switch semi-conductor device,
The abbreviation of insulated gate bipolar transistor；
SBD：SchottkyBarrierDiode, the abbreviation of Schottky-barrier diode；
MOSFET：Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide
The abbreviation of semiconductor field effect transistor；
PCB：Printed Circuit Board, the abbreviation of printed substrate；
To make the purpose, technical scheme and advantage of the embodiment of the present invention clearer, below in conjunction with the embodiment of the present invention
In accompanying drawing, clear, complete description is carried out to the technical scheme in the embodiment of the present invention.Obviously, described embodiment is only
Only it is the part of the embodiment of the present invention, rather than whole embodiments.Based on the embodiment in the present invention, the common skill in this area
All other embodiment that art personnel are obtained under the premise of creative work is not made, belong to the model that the present invention protects
Enclose.
As shown in accompanying drawing 2 to accompanying drawing 6, the specific embodiment of power model ceramic lining plate of the present invention is given, with reference to
The invention will be further described for the drawings and specific embodiments.
Embodiment 1
As shown in Figure 3, a kind of specific embodiment of power model ceramic lining plate, liner plate 10 use three-layer metal layer and two
The layer spaced apart multiple-level stack type structure of ceramic layer, and specifically include：The first metal layer 1 that is sequentially arranged from top to bottom,
Two metal levels 2 and the 3rd metal level 3.The first ceramic layer 4, the second metal are disposed between the first metal layer 1 and second metal layer 2
The second ceramic layer 5 is disposed between the metal level 3 of layer 2 and the 3rd.Wherein, metal level is using the materials such as copper, aluminium, gold, molybdenum, ceramic layer
Using AlN, Al2O3、Si3N4Deng material.As shown in Figure 2, the first metal layer 1 is arranged to the emitter region A (hairs being isolated from each other
Emitter region A is also welded with emitter stage busbar) and control signal terminal region C.Second metal layer 2 is arranged to collector area B (colelctor electrodes
Area B is also welded with colelctor electrode busbar), second metal layer 2 also extends to first by the through hole 16 being arranged in the first ceramic layer 4
The upper surface of ceramic layer 4.Offered in the upper surface through-thickness of liner plate 10 and be respectively used to that the first power chip 20 and the are installed
The groove 6 of two power chips 30, groove 6 extend to second metal layer 2 from the first metal layer 1.In fig. 3, groove 6 from first
Metal level 1 passes through the first ceramic layer 4, and extends to the upper surface of second metal layer 2, to realize the first power chip 20, second
Power chip 30 and the electrical connection of second metal layer 2.As a kind of typical specific embodiment of the present invention, the first power chip 20
For FRD chips, the second power chip 30 is igbt chip.It should be strongly noted that the first power chip 20 can also be SBD
The types such as chip, the second power chip 30 can also be the types such as MOSFET chips.
As shown in Figure 4, the first metal layer 1 is further arranged to emitter region A, the control signal terminal region being isolated from each other
C, First Transition area D and the second transition region E.Control signal terminal region C further comprises the emitter stage control terminal being isolated from each other
Area 14 and gate pole control terminal sub-district 15, emitter stage control terminal sub-district 14 are connected to emitter region A, gate pole control terminal by lead 7
Sub-district 15 is connected to First Transition area D by lead 7.The gate pole 8 of second power chip 30 is connected to First Transition by lead 7
Area D, realize that transition of the lead 7 between First Transition area D and gate pole control terminal sub-district 15 connects by the second transition region E.Control
Signal end sub-district C processed is mainly used in access chip control signal, and control signal includes gate pole and emitter stage control signal, main to make
With the switch for being the second power chip 30 on control liner plate 10.
As a kind of typical specific embodiment of the present invention, liner plate 10 further comprise two control signal terminal region C and
Two the second transition region E, emitter region A, collector area B, control signal terminal region C, First Transition area D and the second transition region E
The axisymmetricly structure distribution on liner plate 10.Offered on liner plate 10 two or more be used for install the first power chip 20 groove
6, and two or more (such as accompanying drawing 2 of groove 6 for being used to install the second power chip 30 corresponding with the quantity of the first power chip 20
In shown embodiment, offered on liner plate 10 three be used for install the first power chip 20 groove 6, and three for pacifying
Fill the groove 6 of the second power chip 30).The bottom of groove 6 is second metal layer 2, and groove 6 realizes the first power core for placement
The weld tabs 9 that piece 20, the second power chip 30 weld with second metal layer 2.Weld tabs 9 can form layer after melting and fill groove 6
Bottom, layer is connected with the first ceramic layer 4 and second metal layer 2, can effectively reduce the stress of chip layer corner, is lifted
The reliability of layer long-term work.Liner plate 10 includes two ceramic layers (ceramic layer primarily serves the effect of insulation and radiating) and three
Layer metal level.The first metal layer 1 is emitter stage and gate signal layer, and second metal layer 2 is collector layer, and the 3rd metal level 3 is
The bottom, main function are and the substrate welding for carrying liner plate and the material thermal mismatching between buffer substrate and liner plate ceramic layer.
The front of liner plate 10 is distributed a number of groove 6 as needed, and groove 6 plays fixed chip (the first power core
The power chip 30 of piece 20 and second) and weld tabs 9 effect.Welding tooling need not be additionally loaded and unloaded in chip bonding process, letter
Change the packaging technology step of IGBT module, improve production efficiency.The layer of chip is located in second metal layer 2, periphery point
The first ceramic layer 4 is furnished with, reduces the stress on layer periphery.Remove the welding region of colelctor electrode busbar, the first gold medal of liner plate 10
It is emitter stage and gate signal layer to belong to layer 1, and the first metal layer 1 is additionally operable to realize the interconnection between multiple liner plates 10, equivalent to PCB
Plate is directly placed on liner plate 10 that (existing IGBT module needs to realize between multiple liner plates 10 by outside special pcb board
Interconnection).The liner plate 10 that embodiment 1 describes is by the way that the first power chip 20 and the second power chip 30 to be positioned over to the position of groove 6
Put and form circuits interconnection structure.In welding procedure, weld tabs 9, the He of the first power chip 20 are placed in the region in groove 6
Second power chip 30 is respectively placed on weld tabs 9, and the experience of weld tabs 9 is melted and cooling procedure, and chip and second metal layer 2 is tight
It is close to link together.The size of groove 6 inhibits the drift of chip, it is only necessary to which the size for adjusting groove 6 is suitable for different sizes
Chip installation.Groove 6 on liner plate 10 not only serves the effect of welding tooling, and technique is realized and is also relatively easy to, and ten
Divide and be beneficial to intelligent manufacturing process.
As shown in Figure 4, the power model ceramic lining plate structure using bonding wire connected mode is given.Second metal
Layer 2 extends to the upper surface of liner plate 1, and the front of liner plate 10 is provided with multiple grooves 6.The bottom of groove 6 is second metal layer 2,
The size of groove 6 unilateral distance L, L mono- that stretch out on the basis of the first power chip 20 or the size of the second power chip 30
As be 0.1~1mm.The first metal layer 1 is light current layer, and the etching width of circuit can reduce, can conduct during multiple liner plates 10
Pcb board uses, for connecting the control signal between each liner plate 10 (, it is necessary to more when being generally packaged into the IGBT module of high current
Individual liner plate is in parallel, but control signal has 1 group or multigroup according to modular circuit form, and early stage module completes liner plate using pcb board more
Between control signal interconnection, PCB typically not super-high-currents, and be low electric end；The first metal layer 1 in the present embodiment, which removes, to be drawn
Outside line bonding part, the interconnection between liner plate 10 can be achieved in remaining region).Remove the first metal layer 1 of colelctor electrode welding region
For emitter stage and gate signal layer, the first metal layer 1 can neatly arrange the trend of emitter stage and gate signal, equivalent to province
Pcb board is removed, the packaging efficiency of IGBT module is increased dramatically.
As shown in Figure 5, the liner plate 10 that embodiment 1 describes includes three-layer metal layer, two ceramic layers, when installed in liner plate
When the first power chip 20 and the second power chip 30 on 10 work, electricity is formed between the first metal layer 1 and second metal layer 2
Logical circulation road.As the direction of arrow show the current path in liner plate 10 in accompanying drawing 5, moved towards by arrow, pass through the first gold medal
Belong to the connection between layer 1 and second metal layer 2 so that the current direction in the first metal layer 1 and the electric current in second metal layer 2
Flow direction to be acted on by mutual inductance on the contrary, offset the first metal layer 1 and the stray inductance in second metal layer 2, so as to realize liner plate
10 low sense, and then the low sense of whole power semiconductor modular (IGBT module) can be realized, so as to greatly promote IGBT module
Performance.
Embodiment 2
As shown in Figure 6, a kind of specific embodiment of power model ceramic lining plate, liner plate 10 include：From top to bottom successively
The first metal layer 1, the metal level 3 of second metal layer 2 and the 3rd of arrangement.It is disposed between the first metal layer 1 and second metal layer 2
First ceramic layer 4, the second ceramic layer 5 is disposed between the metal level 3 of second metal layer 2 and the 3rd.The first metal layer 1 is arranged to that
The emitter region A and control signal terminal region C, second metal layer 2 of this isolation are arranged to collector area B.In the upper surface of liner plate 10
Through-thickness offers the groove 6 for being respectively used to install the first power chip 20 and the second power chip 30, groove 6 from first
Metal level 1 extends to second metal layer 2.Groove 6 can pass through the first ceramic layer 4 from the first metal layer 1, and extend to the second gold medal
Belong to the upper surface of layer 2, to realize the first power chip 20, the second power chip 30 and the electrical connection of second metal layer 2.
In example 2, colelctor electrode busbar is directly welded on second layer metal layer, and first layer metal layer (i.e. liner plate
The metal level on 10 surfaces) welding region without colelctor electrode busbar, all light current region of first layer metal layer, it can also realize lining
Mutual inductance between the first metal layer 1 and second metal layer 2 of plate 10.The more detailed technical scheme of remainder can specifically join
According to the corresponding description in embodiment 1, will not be repeated here.
The technical scheme of the power model ceramic lining plate described by implementing the specific embodiment of the invention, can be produced as follows
Technique effect：
(1) the power model ceramic lining plate of specific embodiment of the invention description realizes the connection of upper and lower metal layer region,
Current path structure, the metal level formation mutual inductance of colelctor electrode and emitter stage in a ring, the stray electrical of liner plate can be greatly reduced
Sense；
(2) there is groove structure on the power model ceramic lining plate of specific embodiment of the invention description, as chip weld tabs
The welding positioning of technique, it is proposed that the lining plate structure of multi-layer ceramics layer and stacks of metal layers stack-type containing multiple grooves, groove
Size is bigger 0.1~1mm than chip, and layer and chip are respectively positioned on the inside of groove, eliminates liner plate welding and places and remove welding
The time of frock, be advantageous to the intellectualized operation of batch, improve process efficiency, chip will not produce drift, can be applied to
The chip welding of different sizes；Layer is located at the inside of groove, and solder is connected with the first ceramic layer and second metal layer, subtracted
Small layer stress, improve the reliability of chip operation；
(3) increase of the power model ceramic lining plate thickness of specific embodiment of the invention description, does not influence the radiating of chip
Path, deflection is small in technical process, is advantageous to the stability of technique and the uniformity of properties of product；
(4) the control terminal wiring of the power model ceramic lining plate of specific embodiment of the invention description is flexible, and position can be with
Adjustment, the PCB during the first metal layer (removing colelctor electrode welding region) can encapsulate as module interconnect use, substantially increased
Packaging efficiency, reliability further improve.Meanwhile the first metal layer is not required to as light current layer (removing colelctor electrode welding region)
Consider Insulation Problems, the interconnection being easy between liner plate.
Each embodiment is described by the way of progressive in this specification, what each embodiment stressed be and other
The difference of embodiment, between each embodiment identical similar portion mutually referring to.
The above described is only a preferred embodiment of the present invention, any formal limitation not is made to the present invention.Though
So the present invention is disclosed as above with preferred embodiment, but is not limited to the present invention.It is any to be familiar with those skilled in the art
Member, in the case where not departing from the Spirit Essence of the present invention and technical scheme, all using in the methods and techniques of the disclosure above
Appearance makes many possible changes and modifications to technical solution of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore,
Every content without departing from technical solution of the present invention, the technical spirit according to the present invention is to made for any of the above embodiments any simple
Modification, equivalent substitution, equivalence changes and modification, still fall within the scope of technical solution of the present invention protection.
Claims (13)
1. a kind of power model ceramic lining plate, it is characterised in that the liner plate (10) includes：First be sequentially arranged from top to bottom
Metal level (1), second metal layer (2) and the 3rd metal level (3), the first metal layer (1) and the second metal layer (2) it
Between be disposed with the first ceramic layer (4), be disposed between the second metal layer (2) and the 3rd metal level (3) second ceramics
Layer (5)；The first metal layer (1) is arranged to the emitter region (A) being isolated from each other and control signal terminal region (C), and described
Two metal levels (2) are arranged to collector area (B)；In the liner plate (10) upper surface, through-thickness, which offers, is respectively used to install
The groove (6) of first power chip (20) and the second power chip (30), the groove (6) are prolonged from the first metal layer (1)
Extend the second metal layer (2).
2. a kind of power model ceramic lining plate, it is characterised in that the liner plate (10) includes：First be sequentially arranged from top to bottom
Metal level (1), second metal layer (2) and the 3rd metal level (3), the first metal layer (1) and the second metal layer (2) it
Between be disposed with the first ceramic layer (4), be disposed between the second metal layer (2) and the 3rd metal level (3) second ceramics
Layer (5)；The first metal layer (1) is arranged to the emitter region (A) being isolated from each other and control signal terminal region (C)；Described
Two metal levels (2) are arranged to collector area (B), and the second metal layer (2) is also by being arranged in first ceramic layer (4)
Through hole (16) extend to the upper surface of first ceramic layer (4)；In the liner plate (10) upper surface, through-thickness opens up
There is a groove (6) for being respectively used to install the first power chip (20) and the second power chip (30), the groove (6) is from described the
One metal level (1) extends to the second metal layer (2).
3. power model ceramic lining plate according to claim 1 or 2, it is characterised in that：When installed in the liner plate (10)
On the first power chip (20) and the second power chip (30) when working, the first metal layer (1) and second metal
Current path is formed between layer (2), the current direction in the first metal layer (1) and the electricity in the second metal layer (2)
Stream flow direction by mutual inductance effect on the contrary, to offset the first metal layer (1) and the stray electrical in the second metal layer (2)
Sense, so as to realize the low sense of the liner plate (10).
4. power model ceramic lining plate according to claim 3, it is characterised in that：The bottom of the groove (6) is second
Metal level (2), the size of the groove (6) is on first power chip (20) or the basis of the second power chip (30) size
The upper unilateral 0.1~1mm that stretches out.
5. according to the power model ceramic lining plate described in claim 1,2 or 4 any one, it is characterised in that：The control signal
Terminal region (C) includes the emitter stage control terminal sub-district (14) and gate pole control terminal sub-district (15) being isolated from each other, the emitter stage control
Terminal region (14) processed is connected to the emitter region (A) by lead (7), and the gate pole control terminal sub-district (15) passes through lead
(7) it is connected to the First Transition area (D).
6. power model ceramic lining plate according to claim 5, it is characterised in that：The first metal layer (1) is additionally operable to
Realize the interconnection between multiple liner plates (10).
7. according to the power model ceramic lining plate described in claim 1,2,4 or 6 any one, it is characterised in that：First gold medal
Category floor (1) is arranged to the emitter region (A), control signal terminal region (C) and First Transition area (D) that are isolated from each other, and described second
The gate pole (8) of power chip (30) is connected to the First Transition area (D) by lead (7).
8. power model ceramic lining plate according to claim 7, it is characterised in that：The first metal layer (1) is arranged to
Emitter region (A), control signal terminal region (C), First Transition area (D) and the second transition region (E) being isolated from each other, by described
Second transition region (E) realizes transition of the lead (7) between the First Transition area (D) and the gate pole control terminal sub-district (15)
Connection.
9. power model ceramic lining plate according to claim 8, it is characterised in that：The liner plate (10) includes two controls
Signal end sub-district (C) and two the second transition regions (E), the emitter region (A), collector area (B), control signal terminal region
(C), First Transition area (D) and the second transition region (E) the axisymmetricly structure distribution on the liner plate (10).
10. according to the power model ceramic lining plate described in claim 1,2,4,6,8 or 9 any one, it is characterised in that：Described
One power chip (20) is FRD chips, and second power chip (30) is igbt chip.
11. power model ceramic lining plate according to claim 10, it is characterised in that：Two are offered on the liner plate (10)
It is used for the groove (6) for installing first power chip (20), and two or more and first power chip more than individual
(20) it is used for the groove (6) for installing second power chip (30) corresponding to quantity；The bottom of the groove (6) is the second gold medal
Belong to layer (2), the groove (6) is used for placement and realizes first power chip (20), the second power chip (30) and described the
The weld tabs (9) of two metal levels (2) welding.
12. according to the power model ceramic lining plate described in claim 1,2,4,6,8 or 9 any one, it is characterised in that：Described
One power chip (20) is SBD chips, and second power chip (30) is MOSFET chips.
13. power model ceramic lining plate according to claim 12, it is characterised in that：Two are offered on the liner plate (10)
It is used for the groove (6) for installing first power chip (20), and two or more and first power chip more than individual
(20) it is used for the groove (6) for installing second power chip (30) corresponding to quantity；The bottom of the groove (6) is the second gold medal
Belong to layer (2), the groove (6) is used for placement and realizes first power chip (20), the second power chip (30) and described the
The weld tabs (9) of two metal levels (2) welding.
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| CN201710827140.XA CN107768340B (en) | 2017-09-14 | 2017-09-14 | Ceramic lining plate of power module |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710827140.XA CN107768340B (en) | 2017-09-14 | 2017-09-14 | Ceramic lining plate of power module |
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| CN107768340B CN107768340B (en) | 2019-12-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108766941A (en) * | 2018-04-12 | 2018-11-06 | 全球能源互联网研究院有限公司 | A kind of crimp type SiC mixing module encapsulating structures |
| CN114621776A (en) * | 2022-03-24 | 2022-06-14 | 武汉钢铁有限公司 | Coke pot bottom gate lining plate compounded with high-temperature ceramic part and preparation method thereof |
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| CN205452265U (en) * | 2015-09-02 | 2016-08-10 | 意法半导体股份有限公司 | Electronic Power Module |
| US20170125322A1 (en) * | 2015-10-31 | 2017-05-04 | Ixys Corporation | Bridging DMB Structure for Wire Bonding in a Power Semiconductor Module |
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|---|---|
| CN107768340B (en) | 2019-12-06 |
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Effective date of registration: 20200928 Address after: 412001 Room 309, floor 3, semiconductor third line office building, Tianxin hi tech park, Shifeng District, Zhuzhou City, Hunan Province Patentee after: Zhuzhou CRRC times Semiconductor Co.,Ltd. Address before: The age of 412001 in Hunan Province, Zhuzhou Shifeng District Road No. 169 Patentee before: ZHUZHOU CRRC TIMES ELECTRIC Co.,Ltd. |