CN106098651B - A kind of power device packaging structure and packaging method - Google Patents
A kind of power device packaging structure and packaging method Download PDFInfo
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- CN106098651B CN106098651B CN201610677974.2A CN201610677974A CN106098651B CN 106098651 B CN106098651 B CN 106098651B CN 201610677974 A CN201610677974 A CN 201610677974A CN 106098651 B CN106098651 B CN 106098651B
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- chip
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- chip slot
- insulating layer
- power device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Die Bonding (AREA)
- Inverter Devices (AREA)
Abstract
The present invention relates to a kind of power device packaging structure and packaging methods and packaging method, power device packaging structure of the present invention include chip slot, with chip slot one be the metal shell that can be used alone as an electrode, be fixed on by annular insulating layer metal shell side-lower pin, and the metal cover board for device sealing.Can of the invention can do independent electrode and use, and be welded in circuit in the form of patch;Four pipe leg structures possessed by this encapsulation can satisfy requirement of the New Type Power Devices to number of pins;It is more of the invention with the bigger chip slot for being used to place chip compared with conventional power devices, and outer pipe shell size made of metal is smaller, and the large chip small package of high-power component may be implemented.
Description
Technical field
The invention belongs to semiconductor device packaging technique fields, and in particular to a kind of power device packaging structure and encapsulation side
Method.
Background technique
Power semiconductor is primarily referred to as powerful in terms of transformation of electrical energy and control circuit for power equipment
Electronic device, usual electric current are tens of to thousands of peaces, and voltage reaches hundreds of volts or more.Currently used power semiconductor has
Thyristor, GTO, MOSFET, IGBT etc. are required on these power device package pins bear high voltage or high current, because
This power device package for being equipped with such high power semiconductor chip is needed with high voltage and very strong heat-sinking capability;Separately
Outside, with the increase of power pressure resistance and current driving ability, chip size is also being continuously increased, for the envelope of New Type Power Devices
Dress also needs the ability with encapsulation large size chip.
Furthermore the encapsulation of power device at present is mostly three-prong structure, power device common three theoretically can satisfy
The requirement of a electrode, but for the New Type Power Devices for pulsed discharge field, if still using the encapsulation of three-prong structure
Pattern easily causes the damage of device in pulsed discharge, as shown in Figure 1, for the IGBT being applied in pulse discharge circuit
Chip will pass through high current in device cathodes (E) moment when device is opened, lead and pin are parasitic when due to chip package
The presence of inductance L, moment generates the induced potential (U (t)=L*di/dt) of upper hectovolt at chip cathode, and grid is powered on
Position (generally can be in 10V or so) is held essentially constant, thus grid and chip cathode both ends can generate excessively high potential difference (U
(t)-Vg), to make gate oxide breakdown, lead to device failure.
Further, the complexity of the layout design of existing power device is continuously increased, by slide holder space and pin
The limitation of position, the optional row very little of routing, especially for the device of assembled package, often by slide glass space and
The limitation of routing narrow space.
Summary of the invention
The purpose of the present invention is made aiming at three pin configuration parasitic inductances present in the encapsulation of above-mentioned conventional power devices
At device failure, encapsulate chip size is small, the poor thermal conductivity of device encapsulation, outer pin resistance to the problem of forcing down propose one kind
Novel four pins, large chip small package, pin high voltage, the power device packaging structure of good heat conductivity.
The technical scheme is that a kind of power device packaging structure, including Can 2;In the Can 2
Portion, which is dug, chip slot 1, has the through-hole connecting with chip slot 1 below Can 2, has insulating layer 3 in through-hole, further include drawing
Foot 4, the pin 4 insulating layer 3 and extend in chip slot 1 from passing through outside Can 2;It further include metal cover board 5, it is described
Metal cover board 5 is formed with Can 2 and is tightly connected for chip slot 1 to be completely covered;It is characterized in that, 4 He of pin
Insulating layer 3 is 4, and the Can 2 is used to be used as absolute electrode;The size of the chip slot 1 is 10*9*3mm.
As shown in Fig. 2 (Fig. 5 is shown in the corresponding encapsulation of four feet), if above structure of the invention is applied to pulsed discharge field
Igbt chip uses four pipe leg structures, and the cathode (E1) that reference potential is provided for grid (G) is individually drawn, is opened in device
When, the discharge loop of capacitor is as shown by arrows in figure, and discharge current is mainly flowed through from device cathodes pin, and is that grid yin provides
The electrode of reference potential does not flow through high current, can effectively drag down the induced potential (U (t)) generated by parasitic inductance, from
And the potential difference (U (t)-Vg) of grid Yu cathode both ends is reduced, and then avoid the damage of gate oxide.
TO263-5L relative to metal structure encapsulates (Fig. 3), and the present invention has bigger slide glass slot, and big core may be implemented
The small package of piece eliminates the outer pin (5) of the connection Can of redundancy in TO263-5L encapsulation, increases between each pin
Spacing and insulating layer thickness, make that higher pressure resistance can be born between each pin.
In addition, the present invention uses bulk metal shell as the structure of an absolute electrode, the electrode structure in a creative way
With the bigger bonding space with on-chip lead, increasing heat-conducting area makes that high current can be carried on the electrode, simultaneously
The power device package that the present invention designs, pin use full floating structure, and the heating conduction between pin and shell electrode is more preferable,
Both it can be fixed on pcb board and can also have been welded in the form of used socket by way of patch welds using the device of the encapsulation
It connects, increases the optional row of connection.
Furthermore the chip slot for the larger size that the present invention designs, Can be the four of absolute electrode and high voltage
Mount structure can satisfy the assembled package of various chips, increase the alternative of routing mode;As shown in fig. 7, for one
The passive devices of a little small sizes, function element can be with the active device assembled packages of certain size in the encapsulation.
Further, the power device packaging structure is used for the chip of model TO263-5L.
A kind of packaging method of power device, which is characterized in that include the following steps:
A. chip slot 1 is set at the middle part of Can 2, the size of the chip slot 1 is 10*9*3mm;The metal tube
Shell 2 is used to be used as absolute electrode;
B., four mount structures of high voltage are set, and four mount structure includes that one end is connect with chip slot 1, and one end is run through
The ceramic ring shape insulating layer 3 of Can 2, pin 4 are installed in ceramic ring shape insulating layer 3;
C. the fixed chip in chip slot 1, one end of pin 4 are connect with chip;
D. the metal cover board 5 that setting is covered on chip slot 1 and is tightly connected with Can 2.
Beneficial effects of the present invention be heat-conducting area is increased to make that high current can be carried on the electrode, while the present invention
Power device package, pin use full floating structure, the heating conduction between pin and shell electrode is more preferable, uses the encapsulation
Device both can patch weld by way of be fixed on pcb board and can also be welded in the form of used socket, the company of increasing
The optional row connect.
Detailed description of the invention
Fig. 1 is the pulse discharge circuit figure of the igbt chip of traditional three-prong encapsulation;
Fig. 2 is the pulse discharge circuit figure using four pin package twin cathode igbt chips;
Fig. 3 is the main view of the TO263-5L encapsulation of conventional metals encapsulation (without cover board);
Fig. 4 is the encapsulating structure of the invention for being loaded with chip and lead (without cover board);
Fig. 5 is a kind of main view of power device packaging structure of the present invention (containing cover board);
Fig. 6 is a kind of side view of power device packaging structure of the present invention (containing covering plate structure);
Fig. 7 is the schematic diagram that the present invention is applied in the encapsulation of assembling device (containing covering plate structure).
Specific embodiment
A specific embodiment of the invention is described with reference to the accompanying drawing
As shown in figure 5, a kind of encapsulating structure of power device of the present invention includes that chip slot 1, Can 2, annular are become attached to
Layer 3, four outer pin 4, metal cover board 5.1 cun of the chip slot ruler is that traditional TO263-5L encapsulates (Fig. 3) for 10*9*3mm
1 size of chip slot is big, can place higher volume of chip and realize large chip small package, while 1 bottom plate of chip slot has more greatly
Space as chip and Can 2 and the bonding point of outer pin 4, also increase the heat-conducting area in chip slot 1.
Some New Type Power Devices are especially applied to four pin configurations of the power device of pulse domain, it is traditional
Three-prong encapsulates the encapsulation requirement for no longer having met such chip, as shown in Figure 1, if using three pin packages, for application
Igbt chip in pulse discharge circuit will pass through high current in device cathodes (E) moment when device is opened, due to chip
The presence of lead and pin parasitic inductance L when encapsulation, at chip cathode moment generate upper hectovolt induced potential (U (t)=
L*di/dt), and current potential added by grid (generally can be in 10V or so) is held essentially constant, thus grid and the both ends meeting of chip cathode
Excessively high potential difference (U (t)-Vg) is generated, so that gate oxide (G) be made to puncture, leads to device failure.If power device uses four
Encapsulation can solve the above problem that three-prong occurs very well, as shown in Fig. 2 (Fig. 5 is shown in the corresponding encapsulation of four feet), if this IGBT
Chip uses four pipe leg structures, and the cathode (E1) that reference potential is provided for grid (G) is individually drawn, when device is opened, electricity
The discharge loop of appearance is as shown by arrows in figure, and discharge current is mainly flowed through from device cathodes pin, and is the reference that grid yin provides
The electrode of potential does not flow through high current, the induced potential (U (t)) generated by parasitic inductance can be effectively dragged down, to drop
The potential difference (U (t)-Vg) of low grid and cathode both ends, and then avoid the damage of gate oxide.
The Can 2 of innovative design can be used as an absolute electrode electrode and use in the present invention, and the electrode is different
It is to remove the shell outer pin 5 (see Fig. 3) of redundancy in the shell electrode of traditional TO263-5L encapsulation, the metal tube in the present invention
The shell back side can be independently welded on pcb board as a pin with patch form, and this 2 shell of metal tube is as electrode pin
Advantage is there is bigger wire bonding space inside not only chip slot 1, moreover, because the metal electrode of this large area is deposited
, make the power device package more can load power device high current, as shown in figure 4, the shell electrode can be used as big function
The anode electrode of rate MCT device, since the electrode area is larger, overall resistance is smaller, even if in the case where high current, device
Also very little, other low current pins can be connected in outer pin power consumption on the pin by the lead in chip slot, by
In the presence of this absolute electrode, the range that can encapsulate chip is expanded, certain chip can be corresponding to select according to pin item number
Pin type of attachment.
A kind of shell 2 for power device package that the present invention designs is using Metal Packaging and the metal substrate area at the back side
Larger, the electrode for acting not only as carrying high current uses and the structure feature also has good heat dissipation performance, encapsulates
The large-area metal shell 2 at the back side is more conducive to the thermally conductive effect for distributing raising device of power chip interior heat in chip slot 1
Rate keeps power chip performance more stable;Furthermore the chip slot for the larger size that the present invention designs, Can do independence
Electrode and four mount structures of high voltage can satisfy the assembled package of various chips, increase may be selected for routing mode
Property;As shown in fig. 7, passive device, the function element for some small sizes can combine envelope with the active device of certain size
In the encapsulation.
As shown in figure 5, the annular insulating layer 3 being made by the good ceramic material of insulation performance is relative to traditional TO263-5L
Metal Packaging, the insulating layer made of insulating ceramic materials is thicker, and the breakdown voltage born between each adjacent leads 4 is more
Height is unlikely to cause the mistakenly hit of power chip to be worn because of resistance to force down between pin, the present invention is made to can be used for high voltage power
The encapsulation of device improves stability of the power device under high voltage.The insulating layer being made of simultaneously ceramic material is to the encapsulation
Pin there are also good fixed function, and insulating layer 3, pin 4, Can 1 and metal upper cover plate 5 form sealing
The internal fillable inert gas of encapsulation is set to improve the stability of chip operation.
It is encapsulated relative to traditional TO263-5L, The present invention reduces a redundancy shell pins, are carried on the back using Can
Face paste piece does pin design, in the case where not reducing the number of chip avaivable electrode, increases the spacing of metal electrode, absolutely
Edge layer thickness, which increases this, will be such that the breakdown voltage between pin increases, and can be used for high voltage power package, which can be with
It is widely used in the encapsulation of novel power semiconductor chip structure.
Claims (2)
1. a kind of power device packaging structure, including Can (2);Digging in the middle part of the Can (2) has chip slot (1),
There is the through-hole connecting with chip slot (1) below Can (2), there are insulating layer (3) in through-hole, further include pin (4), institute
Pin (4) is stated to pass through insulating layer (3) outside Can (2) and extend in chip slot (1);It further include metal cover board (5),
The metal cover board (5) forms with Can (2) and is tightly connected for being completely covered chip slot (1);It is characterized in that,
The pin (4) and insulating layer (3) are 4, and include 1 in 4 pins for providing the yin of reference potential for device grids
Pole pin, the Can (2) are used to be used as absolute electrode;The size of the chip slot (1) is 10*9*3mm.
2. a kind of packaging method of power device, which is characterized in that include the following steps:
A. chip slot (1) is set at the middle part of Can (2), the size of the chip slot (1) is 10*9*3mm;The metal
Shell (2) is used to be used as absolute electrode;
B., four mount structures of high voltage are set, and four mount structure includes that one end is connect with chip slot (1), and one end is through gold
Belong to the ceramic ring shape insulating layer (3) of shell (2), pin (4) is installed in ceramic ring shape insulating layer (3), includes 1 use in 4 pins
In providing the negative electrode pin of reference potential for device grids;
C. the fixed chip in chip slot (1), one end of pin (4) are connect with chip;
D. the metal cover board (5) that setting is covered on chip slot (1) and is tightly connected with Can (2).
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CN106098651B true CN106098651B (en) | 2018-11-23 |
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CN108598183A (en) * | 2018-04-23 | 2018-09-28 | 电子科技大学 | High di/dt photo thyristors encapsulating structure and packaging method |
CN113009254B (en) * | 2021-02-24 | 2022-11-01 | 中国人民解放军陆军工程大学 | High-power high-linearity current injection probe |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399850A (en) * | 1991-12-26 | 1995-03-21 | Kyocera Corporation | Document reading apparatus, having a body unit for holding apparatus components |
US6423575B1 (en) * | 2001-07-27 | 2002-07-23 | Dean Tran | Hydrogen gettering structure including silver-doped palladium layer to increase hydrogen gettering of module component and semiconductor device module having such structure, and methods of fabrication |
CN105529306A (en) * | 2014-10-15 | 2016-04-27 | 英飞凌科技奥地利有限公司 | Semiconductor component |
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2016
- 2016-08-17 CN CN201610677974.2A patent/CN106098651B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5399850A (en) * | 1991-12-26 | 1995-03-21 | Kyocera Corporation | Document reading apparatus, having a body unit for holding apparatus components |
US6423575B1 (en) * | 2001-07-27 | 2002-07-23 | Dean Tran | Hydrogen gettering structure including silver-doped palladium layer to increase hydrogen gettering of module component and semiconductor device module having such structure, and methods of fabrication |
CN105529306A (en) * | 2014-10-15 | 2016-04-27 | 英飞凌科技奥地利有限公司 | Semiconductor component |
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