CN209515657U - A kind of encapsulating structure - Google Patents

A kind of encapsulating structure Download PDF

Info

Publication number
CN209515657U
CN209515657U CN201822263046.9U CN201822263046U CN209515657U CN 209515657 U CN209515657 U CN 209515657U CN 201822263046 U CN201822263046 U CN 201822263046U CN 209515657 U CN209515657 U CN 209515657U
Authority
CN
China
Prior art keywords
convex block
chip
weld pad
ground terminal
power end
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201822263046.9U
Other languages
Chinese (zh)
Inventor
张江华
梁新夫
沈锦新
周海峰
吴昊平
周青云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
JCET Group Co Ltd
Original Assignee
Jiangsu Changjiang Electronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiangsu Changjiang Electronics Technology Co Ltd filed Critical Jiangsu Changjiang Electronics Technology Co Ltd
Priority to CN201822263046.9U priority Critical patent/CN209515657U/en
Application granted granted Critical
Publication of CN209515657U publication Critical patent/CN209515657U/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

The utility model relates to a kind of encapsulating structures, it includes substrate (1), metallic circuit layer (2) are provided on the substrate (1), chip (3) are provided on the metallic circuit layer (2), there are multiple ground pads (6) and power supply weld pad (7) in chip (3) front, convex block on partial earthing weld pad (6) is together in series to form ground terminal convex block (4), convex block on partial power weld pad (7) is together in series to form power end convex block (5), the chip (3) is connected by ground terminal convex block (4) power end convex block (5) and with metallic circuit layer (2), insulating materials (8) are filled between ground terminal convex block (4) the power end convex block (5).A kind of encapsulating structure of the utility model, convex block in chip front side partial power weld pad or ground pad is together in series by it, forms the projection cube structure of strip, can reduce packaged resistance, and insulating materials can be allowed to fill between chip and substrate, guarantee overall package reliability of structure.

Description

A kind of encapsulating structure
Technical field
The utility model relates to a kind of encapsulating structures, belong to technical field of semiconductor encapsulation.
Background technique
The product of low-voltage, high current, in order to which the electric connection provided between chip and substrate is by independent one by one Metal coupling realize that and the number of slugs of two electrodes is very more (as shown in FIG. 1 to 3).
Weld pad on chip is all to be powered by convex block, but the impedance that this design will cause intermediate region is larger, leads The voltage in this region is caused to reduce.
With the development of electronic technology, requirement of the client to electronic product is higher and higher.It is produced in some low-voltages, high current In product, for the voltage for guaranteeing chip, need to realize using three layers of above substrate.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of encapsulating structure for the above-mentioned prior art, it is by core The positive partial power weld pad of piece or ground pad are together in series, and form the projection cube structure of strip, can reduce packaged resistance.
The technical scheme in the invention for solving the above technical problem are as follows: a kind of encapsulating structure, it includes substrate, described It is provided with metallic circuit layer on substrate, chip is provided on the metallic circuit layer, the chip front side there are multiple ground pads With power supply weld pad, the convex block on partial earthing weld pad is together in series to form ground terminal convex block, the convex block string on partial power weld pad Connection gets up to form power end convex block, and the chip is connected by ground terminal convex block and power end convex block with metallic circuit layer, institute It states between ground terminal convex block and power end convex block filled with insulating materials.
The shape of the ground terminal convex block or power end convex block is strip.
Compared with the prior art, the advantages of the utility model are:
1, partial power end convex block or partial earthing end convex block are together in series to form the projection cube structure of strip, can allow absolutely Edge material is filled between chip and substrate, guarantees overall package reliability of structure;
2, chip is electrically connected to substrate by the projection cube structure of strip, and the pressure drop of chip pad to substrate is reduced, can To reduce packaged resistance, while the convex block area for connecting chip and substrate increases, and package cooling enhancing, chip operating temperature is low, Chip operation is more stable, while can reduce the cost of additional heat dissipation equipment;
3, partial power end convex block or partial earthing end convex block are together in series to form the projection cube structure of strip, can reduce Packaged resistance reduces the loss of chip supply voltage, improves single digital cash chip and calculates power, improves chip efficiency, furthermore reduce It is low in energy consumption caused by encapsulation, reduce product power consumption.
Detailed description of the invention
Fig. 1 is the schematic diagram of the end existing chip VSS (ground terminal) convex block.
Fig. 2 is the schematic diagram of the end existing chip VCC (power end) convex block.
Fig. 3 is the schematic diagram of the end existing chip VCC/VSS convex block.
Fig. 4 is a kind of schematic diagram of encapsulating structure of the utility model.
Fig. 5 is the schematic diagram of the end chip VCC/VSS convex block in Fig. 4.
Wherein:
Substrate 1
Metallic circuit layer 2
Chip 3
Ground terminal convex block 4
Power end convex block 5
Ground pad 6
Power supply weld pad 7
Insulating materials 8.
Specific embodiment
The utility model is described in further detail below in conjunction with figure embodiment.
Referring to fig. 4, Fig. 5, the utility model relates to a kind of encapsulating structure, it includes substrate 1, is arranged on the substrate 1 There is metallic circuit layer 2, chip 3 is provided on the metallic circuit layer 2, there are multiple ground pads 6 and power supply in 3 front of chip Weld pad 7, the convex block on partial earthing weld pad 6 are together in series to form ground terminal convex block 4, the convex block series connection on partial power weld pad 7 Getting up to be formed power end convex block 5, the chip 3 is connected by 4 power end convex block 5 of ground terminal convex block and with metallic circuit layer 2, Insulating materials 8 is filled between the 4 power end convex block 5 of ground terminal convex block.
The shape of the ground terminal convex block 4 or power end convex block 5 is strip.
Outside above-described embodiment, the utility model further includes having other embodiments, all using equivalents or equivalent to replace The technical solution that the mode of changing is formed should all be fallen within the protection scope of the utility model claims.

Claims (2)

1. a kind of encapsulating structure, it is characterised in that: it includes substrate (1), is provided with metallic circuit layer (2) on the substrate (1), It is provided with chip (3) on the metallic circuit layer (2), there are multiple ground pads (6) and power supply weld pad in chip (3) front (7), the convex block on partial earthing weld pad (6) is together in series to be formed ground terminal convex block (4), the convex block on partial power weld pad (7) It is together in series to be formed power end convex block (5), the chip (3) passes through ground terminal convex block (4) power end convex block (5) and and metal wire Road floor (2) is connected, and is filled with insulating materials (8) between ground terminal convex block (4) the power end convex block (5).
2. a kind of encapsulating structure according to claim 1, it is characterised in that: the ground terminal convex block (4) or power end are convex The shape of block (5) is strip.
CN201822263046.9U 2018-12-31 2018-12-31 A kind of encapsulating structure Active CN209515657U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201822263046.9U CN209515657U (en) 2018-12-31 2018-12-31 A kind of encapsulating structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201822263046.9U CN209515657U (en) 2018-12-31 2018-12-31 A kind of encapsulating structure

Publications (1)

Publication Number Publication Date
CN209515657U true CN209515657U (en) 2019-10-18

Family

ID=68198870

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201822263046.9U Active CN209515657U (en) 2018-12-31 2018-12-31 A kind of encapsulating structure

Country Status (1)

Country Link
CN (1) CN209515657U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022226889A1 (en) * 2021-04-29 2022-11-03 华为技术有限公司 Chip packaging structure, manufacturing method therefor, and terminal device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022226889A1 (en) * 2021-04-29 2022-11-03 华为技术有限公司 Chip packaging structure, manufacturing method therefor, and terminal device

Similar Documents

Publication Publication Date Title
CN203859110U (en) Double marker plate heap type pipe core packaging part and semiconductor packaging part
US8669650B2 (en) Flip chip semiconductor device
CN102760724B (en) Integrally-packaged power semiconductor device
CN205542761U (en) Power module
CN209515657U (en) A kind of encapsulating structure
CN206806321U (en) A kind of semiconductor package of no lead frame
CN103646942B (en) A kind of semiconductor package being applied to power switcher circuit
CN102842549B (en) The power MOSFET package body of square flat non-pin
CN204497239U (en) Metallic packaging big current, high voltage, fast recovery diode
CN106098651B (en) A kind of power device packaging structure and packaging method
CN206774529U (en) Biradical island encapsulated circuit
CN102842550B (en) The DFN encapsulating structure of power mosfet chip
CN209515649U (en) A kind of encapsulating structure
CN206650072U (en) A kind of integrated circuit package structure with good electrical performance
CN206774530U (en) Lead frame for biradical island encapsulated circuit
CN209515658U (en) A kind of encapsulating structure
CN108447844A (en) A kind of Modular QFN packaging structure
CN206789535U (en) A kind of fan-out package structure of power electronic devices
CN203631590U (en) Vertical LED light bar
CN104701440B (en) LED packaging element and its manufacture method
CN106449517A (en) Stack type single base island SIP (System in Package) packaging process
CN207116432U (en) A kind of high voltage LED chip structure of CSP encapsulation
CN109786367A (en) It is a kind of with the Mosfet semiconductor devices for being internally integrated temperature protective device
CN207304396U (en) A kind of ultra-thin paster bridge rectifier
CN203118935U (en) DFN (dual flat-pack no-lead) package structure for rectifier chip

Legal Events

Date Code Title Description
GR01 Patent grant
GR01 Patent grant