CN206806321U - A kind of semiconductor package of no lead frame - Google Patents
A kind of semiconductor package of no lead frame Download PDFInfo
- Publication number
- CN206806321U CN206806321U CN201720550529.XU CN201720550529U CN206806321U CN 206806321 U CN206806321 U CN 206806321U CN 201720550529 U CN201720550529 U CN 201720550529U CN 206806321 U CN206806321 U CN 206806321U
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- CN
- China
- Prior art keywords
- metal
- chip
- insulating
- lead frame
- semiconductor package
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Led Device Packages (AREA)
Abstract
The utility model discloses a kind of semiconductor package of no lead frame, including：Insulating metal substrate, it includes metal level, heat dissipating layer and for isolating both insulating barriers；An at least chip, it is fixed on metal level and is located at side of the metal level away from insulating barrier, and heat dissipating layer at least covers region corresponding to chip, is connected between chip and metal level by metal wire and/or metal bridge；Packaging part, its coated insulation metal substrate and chip, and side of the heat dissipating layer away from insulating barrier is exposed outside packaging part, packaging part is made of insulating dielectric materials.The insulating metal substrate formed using metal level, insulating barrier and heat dissipating layer substitutes conventional lead frame, overcomes the defects of existing product can not be provided simultaneously with the ability of insulating heat-conductive using metal lead wire frame.
Description
Technical field
It the utility model is related to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor packages knot of no lead frame
Structure.
Background technology
Frequently with chip carrier of the lead frame as integrated circuit in semiconductor package process, lead frame is a kind of
The electrical connection of chip internal circuits exit and outer lead is realized by means of bonding material (spun gold, aluminium wire, copper wire), forms electricity
The key structure part of air circuit, it serves the function served as bridge connected with outer lead, in most semiconductor integrated blocks
It is required for using lead frame, lead frame is basic material important in electronics and information industry.
As the development that semiconductor integration densities increase and terminal electronic small product size reduce, semiconductor components and devices encapsulation are integrated
Also more and more higher, heat caused by chip are needed in time and effectively distributed degree, and semiconductor components and devices otherwise will be hindered normally high
The work of effect, particularly when using power larger chip (such as power chip and diode chip for backlight unit), with greater need for timely
Radiating treatment is carried out to chip.And semiconductor package part most at present is the Reflow Soldering chip on a lead frame, recycle
Sealing operation, to form the packing colloid for being used for coating the chip.Wherein, the packing colloid to coating chip is mostly thermal diffusivity
Difference epoxy resin (Epoxy Resin) class material, therefore semiconductor chip operationally caused heat will be unable to through
Effectively distributed to the external world by packing colloid, cause heat emission efficiency low, and then have influence on the performance of semiconductor chip.
Utility model content
The purpose of this utility model is：A kind of semiconductor package of no lead frame is provided, its is simple in construction, dissipates
Thermal effect is good.
For the above-mentioned purpose, the utility model uses following technical scheme：
A kind of semiconductor package of no lead frame is provided, including：
Insulating metal substrate, it includes metal level, heat dissipating layer and for isolating both insulating barriers；
An at least chip, it is fixed on the metal level and is located at side of the metal level away from the insulating barrier,
The heat dissipating layer at least covers region corresponding to the chip, between the chip and the metal level by metal wire and/or
Metal bridge connects；
Packaging part, it coats the insulating metal substrate and the chip, and at least makes the heat dissipating layer away from described exhausted
The side of edge layer exposes outside the packaging part, and the packaging part is made of insulating dielectric materials.
As a kind of preferred scheme of the semiconductor package without lead frame, the chip is away from the insulated metal
The side of substrate sets auxiliary heat dissipation plate.
As a kind of preferred scheme of the semiconductor package without lead frame, the auxiliary heat dissipation plate includes setting successively
The auxiliary metal layer in side of the chip away from the insulating metal substrate, auxiliary insulating layer and auxiliary heat dissipation layer are put,
Wherein, the side of the auxiliary heat dissipation layer away from the auxiliary insulating layer exposes outside the packaging part.
As a kind of preferred scheme of the semiconductor package without lead frame, it is spaced and sets on the insulating metal substrate
Put control chip, power chip and diode chip for backlight unit.
As a kind of preferred scheme of the semiconductor package without lead frame, the control chip by metal wire with
The metal level connection of the insulating metal substrate, the control chip, the power chip and the diode chip for backlight unit
Between connected by metal wire, the metal level that the diode chip for backlight unit passes through metal wire and the insulating metal substrate connects
Connect.
As a kind of preferred scheme of the semiconductor package without lead frame, the control chip passes through metal wire point
It is not connected with the metal level of the insulating metal substrate and the power chip, the power chip and the diode core
Connected between piece by metal bridge, the diode chip for backlight unit is connected by the metal level of metal bridge and the insulating metal substrate
Connect.
As a kind of preferred scheme of the semiconductor package without lead frame, state control chip and distinguished by metal wire
It is connected with the metal level of the insulating metal substrate and the power chip, the power chip and the diode chip for backlight unit
The side of the metal level away from the insulating metal substrate sets auxiliary heat dissipation plate, the power chip and the diode
Connected between chip by the auxiliary metal layer of the auxiliary heat dissipation plate, the auxiliary metal layer of the auxiliary heat dissipation plate and institute
State the metal level connection of insulating metal substrate.
As a kind of preferred scheme of the semiconductor package without lead frame, the auxiliary of the auxiliary heat dissipation plate
Metal level is connected by transition metal plate with the metal level of the insulating metal substrate.
As a kind of preferred scheme of the semiconductor package without lead frame, the packaging part is epoxy encapsulation
Glue.
As a kind of preferred scheme of the semiconductor package without lead frame, the described of the insulating metal substrate dissipates
Thermosphere is metallic radiating layer.
Preferably, the heat dissipating layer is layers of copper, tin layers, aluminium lamination or aluminium alloy layer.
The beneficial effects of the utility model are：By the way that chip is arranged on insulating metal substrate, this insulation can be utilized
Metal substrate provides the demand of radiating for chip, and insulating barrier can ensure metal level and heat dissipating layer high-voltage isulation, and metal level can provide
Chip circuit turns on, and the insulating metal substrate formed using metal level, insulating barrier and heat dissipating layer substitutes conventional lead frame,
The defects of existing product can not be provided simultaneously with the ability of insulating heat-conductive using metal lead wire frame is overcome, and the nothing of this programme is drawn
The semiconductor package of wire frame has the advantages of simple in construction, high-cooling property.
Brief description of the drawings
The utility model is described in further detail below according to drawings and examples.
Fig. 1 is the schematic cross-sectional view of the semiconductor package without lead frame described in the embodiment of the utility model one.
Fig. 2 is the section view signal of the semiconductor package without lead frame described in another embodiment of the utility model
Figure.
Fig. 3 is the section view signal of the semiconductor package without lead frame described in the another embodiment of the utility model
Figure.
In figure：
1st, insulating metal substrate；11st, metal level；12nd, insulating barrier；13rd, heat dissipating layer；2nd, packaging part；3rd, auxiliary heat dissipation plate；
31st, auxiliary metal layer；32nd, auxiliary insulating layer；33rd, auxiliary heat dissipation layer；4th, control chip；5th, power chip；6th, diode chip for backlight unit；
7th, metal wire；8th, metal bridge；9th, transition metal plate.
Embodiment
It is clearer for the technical scheme and the technique effect that reaches that make technical problem that the utility model solves, use,
The technical scheme of the utility model embodiment is described in further detail below in conjunction with accompanying drawing, it is clear that described reality
It is only the utility model part of the embodiment to apply example, rather than whole embodiments.Based on the embodiment in the utility model,
The every other embodiment that those skilled in the art are obtained under the premise of creative work is not made, it is new to belong to this practicality
The scope of type protection.
In description of the present utility model, unless otherwise clearly defined and limited, term " connected ", " connection ", " Gu
It is fixed " it should be interpreted broadly, for example, it may be fixedly connected or be detachably connected, or integrally；Can be that machinery connects
Connect or electrically connect；Can be joined directly together, can also be indirectly connected by intermediary, can be in two elements
The connection in portion or the interaction relationship of two elements.For the ordinary skill in the art, can be managed with concrete condition
Solve concrete meaning of the above-mentioned term in the utility model.
As shown in Figures 1 to 3, in the present embodiment, a kind of semiconductor package of no lead frame of the present utility model,
Including：
Insulating metal substrate 1, it includes metal level 11, heat dissipating layer 13 and for isolating both insulating barriers 12；
An at least chip, it is fixed on the metal level 11 and positioned at the metal level 11 away from the insulating barrier 12
Side, the heat dissipating layer 13 at least cover region corresponding to the chip, pass through gold between the chip and the metal level 11
Category line 7 and/or metal bridge 8 connect；
Packaging part 2, it coats the insulating metal substrate 1 and the chip, and at least makes the heat dissipating layer 13 away from institute
The side for stating insulating barrier 12 exposes outside the packaging part 2, and the packaging part 2 is made of insulating dielectric materials.
By the way that chip is arranged on insulating metal substrate 1, radiating can be provided for chip using this insulating metal substrate 1
Demand, insulating barrier 12 can ensure metal level 11 and the high-voltage isulation of heat dissipating layer 13, and metal level 11 can provide chip circuit conducting, adopt
The insulating metal substrate 1 formed with metal level 11, insulating barrier 12 and heat dissipating layer 13 substitutes conventional lead frame, overcomes existing
Have the defects of ability that product can not be provided simultaneously with insulating heat-conductive using metal lead wire frame, and this programme without lead frame
Semiconductor package has the advantages of simple in construction, high-cooling property.
In a preferred embodiment of the present utility model, side of the chip away from the insulating metal substrate 1
Auxiliary heat dissipation plate 3 is set.By setting auxiliary heat dissipation plate 3, it is possible to achieve chip both sides are radiated simultaneously, auxiliary heat dissipation effect, this
Structure is applied to the larger chip of power.
Specifically, the auxiliary heat dissipation plate 3 includes being successively set on one of the chip away from the insulating metal substrate 1
Auxiliary metal layer 31, auxiliary insulating layer 32 and the auxiliary heat dissipation layer 33 of side, wherein, the auxiliary heat dissipation layer 33 is away from described auxiliary
The side of insulating barrier 32 is helped to expose outside the packaging part 2.
Control core is arranged at intervals in another preferred embodiment of the present utility model, on the insulating metal substrate 1
Piece 4, power chip 5 and diode chip for backlight unit 6.
In a specific embodiment of the present utility model, as shown in figure 1, this semiconductor packages knot without lead frame
Structure includes insulating metal substrate 1, the chip and packaging part 2 being arranged on insulating metal substrate 1, specifically, insulated metal base
Plate 1 includes metal level 11, heat dissipating layer 13 and for isolating both insulating barriers 12, wherein, heat dissipating layer 13 is metal dielectric layer,
Such as layers of copper, tin layers, aluminium lamination or aluminium alloy layer, heat dissipating layer 13 and insulating barrier 12 are pressed together on metal level 11 and form integrative-structure successively
Insulating metal substrate 1.
In the present embodiment, side of the metal level 11 away from insulating barrier 12 is arranged at intervals three chips, respectively controls core
Piece 4, power chip 5 and diode chip for backlight unit 6, multiple insulating barriers 12 are spaced apart in side of the metal level 11 away from chip, often
Individual side of the insulating barrier 12 away from metal level 11 is provided with one layer of heat dissipating layer 13, wherein, in one of metal level 11 away from chip
Side corresponds to chip setting area and sets a monoblock insulating barrier 12 and heat dissipating layer 13.It is of course also possible in metal level 11 away from chip
Side one monoblock insulating barrier 12 and heat dissipating layer 13 are set.
The control chip 4 is connected by metal wire 7 with the metal level 11 of the insulating metal substrate 1, the control
Connected between coremaking piece 4, the power chip 5 and the diode chip for backlight unit 6 by metal wire 7, the diode chip for backlight unit 6 is logical
The metal level 11 that metal wire 7 is crossed with the insulating metal substrate 1 is connected.
Packaging part 2 is made of epoxy encapsulation glue, its coated insulation metal substrate 1, control chip 4, power chip 5
And diode chip for backlight unit 6, and side of the heat dissipating layer 13 away from insulating barrier 12 is exposed outside packaging part 2.
In another specific embodiment of the present utility model, as shown in Fig. 2 the reality that this embodiment is shown with Fig. 1
It is similar to apply a structure, differs only in, the present embodiment is between power chip 5 and diode chip for backlight unit 6, diode chip for backlight unit 6 with absolutely
Connected between the metal level 11 of edge metal substrate 1 using metal bridge 8.Specifically, the control chip 4 is distinguished by metal wire 7
It is connected with the metal level 11 and the power chip 5 of the insulating metal substrate 1, the power chip 5 and two pole
Connected between die 6 by metal bridge 8, the diode chip for backlight unit 6 passes through metal bridge 8 and the institute of the insulating metal substrate 1
Metal level 11 is stated to connect.
In the present embodiment, one end of metal bridge 8 is arranged on power chip 5 and is connected thereto, the other end and insulated metal
The metal level 11 of substrate 1 is connected, and middle part is connected with diode chip for backlight unit 6, and metal bridge 8 and power chip 5 and diode chip for backlight unit 6 are equal
Contacted for face, heat dispersion can be improved, and the use of metal bridge 8 can reduce resistance.
In another specific embodiment of the present utility model, as shown in figure 3, the reality that this embodiment is shown with Fig. 1
It is similar to apply a structure, differs only in, the side of power chip 5 and diode chip for backlight unit 6 away from insulating metal substrate 1 sets auxiliary
Heat sink 3, specifically, the control chip 4 passes through the metal level 11 with the insulating metal substrate 1 respectively of metal wire 7
Connected with the power chip 5, the power chip 5 and the diode chip for backlight unit 6 are away from described in the insulating metal substrate 1
The side of metal level 11 sets auxiliary heat dissipation plate 3, passes through the auxiliary between the power chip 5 and the diode chip for backlight unit 6
The auxiliary metal layer 31 of heat sink 3 connects, the auxiliary metal layer 31 and the insulating metal substrate of the auxiliary heat dissipation plate 3
1 metal level 11 connects.
The auxiliary metal layer 31 of the auxiliary heat dissipation plate 3 passes through transition metal plate 9 and the insulating metal substrate
The metal level 11 connects.
Auxiliary heat dissipation plate 3 also includes being successively set on one of auxiliary metal layer 31 away from power chip 5 and diode chip for backlight unit 6
The auxiliary insulating layer 32 and auxiliary heat dissipation layer 33 of side.
Packaging part 2 is made of epoxy encapsulation glue, its coated insulation metal substrate 1, control chip 4, power chip
5th, diode chip for backlight unit 6 and auxiliary heat dissipation plate 3, and make side of the heat dissipating layer 13 away from insulating barrier 12, auxiliary heat dissipation layer 33 remote
The side of auxiliary insulating layer 32 exposes outside packaging part 2.
Power chip 5 and diode chip for backlight unit 6 are connected and turned on using the auxiliary metal layer 31 of auxiliary heat dissipation plate 3, are formed double
Face radiator structure, heat dispersion is further improved, increase the power density in unit volume.
In the description of this specification, the description of reference term " embodiment ", " example " etc. means to combine the embodiment
Or specific features, structure, material or the feature of example description are contained at least one embodiment or example of the present utility model
In.In this manual, identical embodiment or example are not necessarily referring to the schematic representation of above-mentioned term.Moreover, retouch
Specific features, structure, material or the feature stated can be in any one or more embodiments or example with suitable side
Formula combines.
Technical principle of the present utility model is described above in association with specific embodiment.These descriptions are intended merely to explain this reality
With new principle, and the limitation to scope of protection of the utility model can not be construed in any way.Based on explanation herein,
Those skilled in the art, which would not require any inventive effort, can associate other embodiments of the present utility model,
These modes are fallen within the scope of protection of the utility model.
Claims (10)
- A kind of 1. semiconductor package of no lead frame, it is characterised in that including：Insulating metal substrate, it includes metal level, heat dissipating layer and for isolating both insulating barriers；An at least chip, it is fixed on the metal level and is located at side of the metal level away from the insulating barrier, described Heat dissipating layer at least covers region corresponding to the chip, passes through metal wire and/or metal between the chip and the metal level Bridging connects；Packaging part, it coats the insulating metal substrate and the chip, and at least makes the heat dissipating layer away from the insulating barrier Side expose outside the packaging part, the packaging part is made of insulating dielectric materials.
- 2. the semiconductor package of no lead frame according to claim 1, it is characterised in that the chip is away from institute The side for stating insulating metal substrate sets auxiliary heat dissipation plate.
- 3. the semiconductor package of no lead frame according to claim 2, it is characterised in that the auxiliary heat dissipation plate Including being successively set on the auxiliary metal layer of side of the chip away from the insulating metal substrate, auxiliary insulating layer and auxiliary Heat dissipating layer is helped, wherein, the side of the auxiliary heat dissipation layer away from the auxiliary insulating layer exposes outside the packaging part.
- 4. the semiconductor package of no lead frame according to claim 2, it is characterised in that the insulated metal base Control chip, power chip and diode chip for backlight unit are arranged at intervals on plate.
- 5. the semiconductor package of no lead frame according to claim 4, it is characterised in that the control chip leads to Cross metal wire to be connected with the metal level of the insulating metal substrate, the control chip, the power chip and described Connected between diode chip for backlight unit by metal wire, the diode chip for backlight unit passes through described in metal wire and the insulating metal substrate Metal level connects.
- 6. the semiconductor package of no lead frame according to claim 4, it is characterised in that the control chip leads to Cross metal wire to be connected with the metal level of the insulating metal substrate and the power chip respectively, the power chip and institute State and connected by metal bridge between diode chip for backlight unit, the diode chip for backlight unit passes through metal bridge and the institute of the insulating metal substrate State metal level connection.
- 7. the semiconductor package of no lead frame according to claim 4, it is characterised in that the control chip leads to Cross metal wire to be connected with the metal level of the insulating metal substrate and the power chip respectively, the power chip and institute The side for stating the metal level of the diode chip for backlight unit away from the insulating metal substrate sets auxiliary heat dissipation plate, the power chip Be connected between the diode chip for backlight unit by the auxiliary metal layer of the auxiliary heat dissipation plate, the auxiliary heat dissipation plate it is described auxiliary Aided metal layer is connected with the metal level of the insulating metal substrate.
- 8. the semiconductor package of no lead frame according to claim 7, it is characterised in that the auxiliary heat dissipation plate The auxiliary metal layer be connected by transition metal plate with the metal level of the insulating metal substrate.
- 9. the semiconductor package without lead frame according to any one of claim 1 to 8, it is characterised in that described Packaging part is epoxy encapsulation glue.
- 10. the semiconductor package without lead frame according to any one of claim 1 to 8, it is characterised in that described The heat dissipating layer of insulating metal substrate is metallic radiating layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720550529.XU CN206806321U (en) | 2017-05-16 | 2017-05-16 | A kind of semiconductor package of no lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201720550529.XU CN206806321U (en) | 2017-05-16 | 2017-05-16 | A kind of semiconductor package of no lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN206806321U true CN206806321U (en) | 2017-12-26 |
Family
ID=60741165
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201720550529.XU Active CN206806321U (en) | 2017-05-16 | 2017-05-16 | A kind of semiconductor package of no lead frame |
Country Status (1)
| Country | Link |
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| CN (1) | CN206806321U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109994437A (en) * | 2019-03-29 | 2019-07-09 | 上海天马微电子有限公司 | Chip packaging structure and manufacturing method thereof |
| CN111769091A (en) * | 2020-06-23 | 2020-10-13 | 合肥速芯微电子有限责任公司 | Frame packaging structure and preparation method thereof |
| CN112687640A (en) * | 2019-10-18 | 2021-04-20 | Jmj韩国株式会社 | Heat dissipation plate, method of manufacturing the same, and semiconductor package including the same |
| US11189555B2 (en) | 2019-01-30 | 2021-11-30 | Delta Electronics, Inc. | Chip packaging with multilayer conductive circuit |
-
2017
- 2017-05-16 CN CN201720550529.XU patent/CN206806321U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11189555B2 (en) | 2019-01-30 | 2021-11-30 | Delta Electronics, Inc. | Chip packaging with multilayer conductive circuit |
| CN109994437A (en) * | 2019-03-29 | 2019-07-09 | 上海天马微电子有限公司 | Chip packaging structure and manufacturing method thereof |
| CN112687640A (en) * | 2019-10-18 | 2021-04-20 | Jmj韩国株式会社 | Heat dissipation plate, method of manufacturing the same, and semiconductor package including the same |
| CN112687640B (en) * | 2019-10-18 | 2024-06-11 | Jmj韩国株式会社 | Heat dissipation plate, method of manufacturing the same, and semiconductor package including the same |
| CN111769091A (en) * | 2020-06-23 | 2020-10-13 | 合肥速芯微电子有限责任公司 | Frame packaging structure and preparation method thereof |
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