CN209515658U - A kind of encapsulating structure - Google Patents
A kind of encapsulating structure Download PDFInfo
- Publication number
- CN209515658U CN209515658U CN201822272378.3U CN201822272378U CN209515658U CN 209515658 U CN209515658 U CN 209515658U CN 201822272378 U CN201822272378 U CN 201822272378U CN 209515658 U CN209515658 U CN 209515658U
- Authority
- CN
- China
- Prior art keywords
- substrate
- circuit layer
- metallic circuit
- chip
- size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Structure Of Printed Boards (AREA)
Abstract
The utility model relates to a kind of encapsulating structures, it includes substrate (1), metallic circuit layer (2) are provided on the substrate (1), the height of the metallic circuit layer (2) is higher than substrate (1) surface, chip (3) are provided on the metallic circuit layer (2), the chip (3) is connected by metal coupling (4) with metallic circuit layer (2), the metallic circuit layer (2) includes ground path (6) and power circuit (7), the ground path (6) is arranged in the inside of power circuit (7) further groove (8), the size of the ground path (6) is less than or equal to metal coupling (4) size, the power circuit (7) is all connected.A kind of encapsulating structure of the utility model, the metallic circuit layer on substrate are higher than substrate surface, and the pin size on substrate is less than or equal to chip lug size, substrate is preferably combined with chip, the power circuit on substrate is all connected simultaneously, and line width broadens, and can reduce product pressure drop.
Description
Technical field
The utility model relates to a kind of encapsulating structures, belong to technical field of semiconductor encapsulation.
Background technique
Low-voltage, the product of high current, in order to which the electric connection provided between chip and substrate is by independent one by one
Metal coupling realize that and the number of slugs of two electrodes is very more (as shown in FIG. 1 to 3).
Weld pad on chip is powered by convex block, and the impedance that the above design will cause intermediate region is larger, leads to this
The voltage in region reduces, and influences the electrical property of entire encapsulating structure.
And existing substrate metal route design is lower than substrate surface, as shown in figure 4, have metallic circuit layer 2 on substrate 1,
One layer insulating 5 (i.e. ink layer) covering part metallic circuit layer 2, the metallic circuit phase that chip 3 passes through metal coupling 4 and exposing
Even, the metallic circuit size of exposing and the size greater than metal coupling 4.With the development of electronic technology, client is to electronic product
Requirement it is higher and higher.In some low-voltages, high current product, for the voltage for guaranteeing chip, it is desirable that the substrate of multilayer comes real
It is existing, so increase substrate manufacture complexity.
Utility model content
Technical problem to be solved in the utility model is to provide a kind of encapsulating structure, substrate for the above-mentioned prior art
On metallic circuit layer be higher than substrate surface, the pin size on substrate is less than or equal to chip lug size, so that VCC
End line line width broadens, and reduces product pressure drop.
The technical scheme in the invention for solving the above technical problem are as follows: a kind of encapsulating structure, it includes substrate, described
Metallic circuit layer is provided on substrate, the height of the metallic circuit layer is higher than substrate surface, is arranged on the metallic circuit layer
There is chip, the chip is connected by metal coupling with metallic circuit layer, and the metallic circuit layer includes ground path and electricity
The inside of power circuit further groove is arranged in source route, the ground path, and the size of the ground path is less than or equal to gold
Belong to size of lug, the power circuit is all connected.
Compared with the prior art, the advantages of the utility model are:
A kind of encapsulating structure of the utility model, the metallic circuit layer on substrate are higher than substrate surface, the pin on substrate
Size is less than or equal to chip lug size, substrate is preferably combined with chip, while the power circuit on substrate is complete
Portion is connected, and line width broadens, and can reduce product pressure drop.
Detailed description of the invention
Fig. 1 is the schematic diagram of the end existing chip VSS (ground terminal) convex block.
Fig. 2 is the schematic diagram of the end existing chip VCC (power end) convex block.
Fig. 3 is the schematic diagram of the end existing chip VCC/VSS convex block.
The schematic diagram of the existing substrate encapsulation structure of Fig. 4.
Fig. 5 is a kind of schematic diagram of encapsulating structure of the utility model.
Fig. 6 is a kind of substrate top view of encapsulating structure of the utility model.
Wherein:
Substrate 1
Metallic circuit layer 2
Chip 3
Metal coupling 4
Insulating layer 5
Ground path 6
Power circuit 7
Groove 8.
Specific embodiment
The utility model is described in further detail below in conjunction with figure embodiment.
Referring to Fig. 5, Fig. 6, the utility model relates to a kind of encapsulating structure, it includes substrate 1, is arranged on the substrate 1
There is metallic circuit layer 2, the height of the metallic circuit layer 2 is higher than 1 surface of substrate, is provided with chip on the metallic circuit layer 2
3, the chip 3 is connected by metal coupling 4 with metallic circuit layer 2, and the metallic circuit layer 2 includes ground path 6 and electricity
The inside of 7 further groove 8 of power circuit is arranged in source route 7, the ground path 6, and the size of the ground path 6 is less than or waits
In 4 size of metal coupling, the power circuit 7 is all connected.
Outside above-described embodiment, the utility model further includes having other embodiments, all using equivalents or equivalent to replace
The technical solution that the mode of changing is formed should all be fallen within the protection scope of the utility model claims.
Claims (1)
1. a kind of encapsulating structure, it is characterised in that: it includes substrate (1), is provided with metallic circuit layer (2) on the substrate (1),
The height of the metallic circuit layer (2) is higher than substrate (1) surface, is provided with chip (3) on the metallic circuit layer (2), described
Chip (3) is connected by metal coupling (4) with metallic circuit layer (2), and the metallic circuit layer (2) includes ground path (6)
With power circuit (7), the ground path (6) is arranged in the inside of power circuit (7) further groove (8), the ground path (6)
Size be less than or equal to metal coupling (4) size, the power circuit (7) is all connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822272378.3U CN209515658U (en) | 2018-12-31 | 2018-12-31 | A kind of encapsulating structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201822272378.3U CN209515658U (en) | 2018-12-31 | 2018-12-31 | A kind of encapsulating structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN209515658U true CN209515658U (en) | 2019-10-18 |
Family
ID=68199192
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201822272378.3U Active CN209515658U (en) | 2018-12-31 | 2018-12-31 | A kind of encapsulating structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN209515658U (en) |
-
2018
- 2018-12-31 CN CN201822272378.3U patent/CN209515658U/en active Active
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |