CN114914235A - Packaging structure and packaging method of multi-chip parallel asymmetric silicon carbide module - Google Patents
Packaging structure and packaging method of multi-chip parallel asymmetric silicon carbide module Download PDFInfo
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- CN114914235A CN114914235A CN202210427689.0A CN202210427689A CN114914235A CN 114914235 A CN114914235 A CN 114914235A CN 202210427689 A CN202210427689 A CN 202210427689A CN 114914235 A CN114914235 A CN 114914235A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
Abstract
The invention discloses a packaging method and a packaging structure of a multi-chip parallel asymmetric silicon carbide module. The power terminals include a main power DC + terminal, a main power DC-terminal, and a main power AC terminal. The plurality of silicon carbide power chips are connected in parallel to form a half-bridge circuit, and the plurality of silicon carbide power chips, the plurality of driving resistors and the gasket are arranged between the bottom layer direct copper-clad lining board and the top layer direct copper-clad lining board. The resistance value of each of the plurality of drive resistors is inversely proportional to the distance of each of the plurality of silicon carbide power chips from the corresponding main power DC + terminal or main power DC-terminal.
Description
Technical Field
The invention relates to the technical field of packaging and integration of power semiconductor modules, in particular to a packaging structure of a multi-chip parallel asymmetric silicon carbide module and a packaging method of the multi-chip parallel asymmetric silicon carbide module.
Background
Modern power electronics are moving towards high power density and high efficiency. However, as the working environment tends to be high frequency, high voltage and high temperature, the Si semiconductor is difficult to meet the requirements due to the material limitation thereof.
In this context, wide bandgap semiconductor material devices have come into play, and the wide bandgap semiconductor materials are typically represented by silicon carbide (SiC) and gallium nitride (GaN), and these semiconductor materials are also referred to as third generation semiconductor materials. The advantages of the wide bandgap semiconductor are more prominent than those of the second generation semiconductors represented by silicon (Si) and gallium arsenide (GaAs). Under the same conditions, the wide bandgap semiconductor material device has higher breakdown voltage, higher on-current, higher operating temperature, higher switching speed and lower switching loss, and thus is widely applied.
Because the current capacity of the existing single silicon carbide chip is limited, a plurality of discrete devices are generally connected in parallel or a power module with a multi-chip parallel structure is adopted in a high-power occasion, and most of the existing direct copper-clad (DBC) lining plates of the commercial multi-chip parallel module are in asymmetric physical structures, so that the problem of unbalanced current and loss distribution on different chips and the problem of reliability such as unbalanced thermal stress are inevitably caused. With higher switching frequencies and greater rates of current change for SiC devices, the difference in parasitic parameters can cause greater current imbalance problems than for Si devices.
Disclosure of Invention
The invention aims to provide a packaging structure and a packaging method of a multi-chip parallel asymmetric silicon carbide module, which can overcome the defects, wherein the packaging structure can overcome the defects of inconsistent parasitic parameters and uneven current and loss distribution caused by the asymmetric structure of the conventional commercial multi-chip parallel silicon carbide power module.
Furthermore, the present invention is also directed to solve or alleviate other technical problems of the prior art.
According to a first aspect of the present invention, a technical solution to solve the technical problem is to provide a package structure of a multi-chip parallel asymmetric silicon carbide module, which includes a bottom direct copper-clad board, a top direct copper-clad board facing the bottom direct copper-clad board, a plurality of silicon carbide power chips, a plurality of driving resistors corresponding to the plurality of silicon carbide power chips, a pad, and a power terminal, wherein the power terminal includes a main power DC + terminal, a main power DC-terminal, and a main power AC terminal, wherein the plurality of silicon carbide power chips are connected in parallel to each other to form a half-bridge circuit, and the plurality of silicon carbide power chips, the plurality of driving resistors, and the pad are disposed between the bottom direct copper-clad board and the top direct copper-clad board, a resistance value of each of the plurality of drive resistors is inversely proportional to a distance of each of the plurality of silicon carbide power chips from the corresponding main power DC + terminal or main power DC-terminal.
Optionally, according to an embodiment of the invention, the plurality of silicon carbide power chips includes a first group of silicon carbide power chips and a second group of silicon carbide power chips, and the first silicon carbide power chips are connected in parallel with each other and attached to the bottom layer direct copper clad laminate to form an upper leg of the half bridge circuit, and the second silicon carbide power chips are connected in parallel with each other and attached to the top layer direct copper clad laminate to form a lower leg of the half bridge circuit.
Optionally, according to an embodiment of the invention, the first heat sink and the second heat sink are connected to the outside of the top layer direct copper clad backing plate and the bottom layer direct copper clad backing plate, respectively.
Optionally, according to an embodiment of the present invention, each of the top layer direct copper clad laminate and the bottom layer direct copper clad laminate includes a circuit layer composed of a copper block, a heat dissipation layer, and an insulating layer disposed between the circuit layer and the heat dissipation layer.
Alternatively, in accordance with an embodiment of the present invention, the insulating layer is made of Si 3 N 4 Is made of ceramics.
Optionally, according to an embodiment of the present invention, the circuit layer of the bottom direct copper clad laminate includes a first copper block, a second copper block, a DC + copper block, a DC-copper block, and a sixth copper block, and the circuit layer of the top direct copper clad laminate includes a third copper block, a fourth copper block, a fifth copper block, and an AC copper block.
Optionally, according to an embodiment of the present invention, the package structure includes an upper bridge arm source terminal, an upper bridge arm gate driving terminal, a lower bridge arm source terminal, and a lower bridge arm gate driving terminal; the drain electrode of the silicon carbide power chip of the upper bridge arm is connected to the DC + copper block of the bottom layer direct copper-clad lining plate, the source electrode of the silicon carbide power chip of the upper bridge arm is connected to the first copper block of the bottom layer direct copper-clad lining plate through an upper bridge arm source electrode bonding wire, the grid electrode of the silicon carbide power chip of the upper bridge arm is connected to the sixth copper block of the bottom layer direct copper-clad lining plate through an upper bridge arm grid electrode bonding wire and is connected with the second copper block and the upper bridge arm grid electrode driving terminal through a driving resistor, the drain electrode of the silicon carbide power chip of the lower bridge arm is connected to the AC copper block of the top layer direct copper-clad lining plate, the source electrode of the silicon carbide power chip of the lower bridge arm is connected to the fourth copper block of the top layer direct copper-clad lining plate through a lower bridge arm source electrode bonding wire, and the grid electrode of the silicon carbide power chip of the lower bridge arm is connected to the top layer direct copper-clad lining plate through a lower bridge arm grid electrode bonding wire And the fifth copper block of the lining plate is connected with the third copper block and the lower bridge arm grid driving terminal through a driving resistor.
Optionally, according to an embodiment of the invention, the main power DC + terminal and the main power DC-terminal are located on a side of the package structure, and the main power AC terminal is located on another side of the package structure opposite to the side.
Optionally, according to an embodiment of the invention, the shims include an upper bridge arm shim and a lower bridge arm shim.
According to a second aspect of the invention, a packaging method for the packaging structure of the multi-chip parallel asymmetric silicon carbide module is provided, which is characterized by comprising the following steps: selecting a bottom layer direct copper-clad liner plate and a top layer direct copper-clad liner plate, and etching copper block structures of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate; welding an upper bridge arm silicon carbide power chip, an upper bridge arm driving terminal, main power DC + and DC-terminals and a lower bridge arm gasket to the bottom layer and directly coating a copper lining plate; welding a lower bridge arm silicon carbide power chip, a lower bridge arm driving terminal, a main power AC terminal and an upper bridge arm gasket to the top layer and directly coating a copper lining plate; connecting electrodes of the silicon carbide power chip with corresponding copper blocks and connecting terminals with the corresponding copper blocks by using bonding wires on the bottom layer direct copper-clad lining plate and the top layer direct copper-clad lining plate respectively; stacking the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate, and connecting corresponding copper blocks of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate with corresponding gaskets; and welding the radiator on the outer sides of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate, and injecting epoxy resin between the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate to form a plastic package structure.
Compared with the prior art, the packaging structure of the multi-chip parallel asymmetric silicon carbide module has the following beneficial effects: because the resistance value of the driving resistor corresponding to each silicon carbide power chip of each parallel branch of the packaging structure is inversely proportional to the distance from the silicon carbide power chip to the corresponding direct current terminal, the switching loss is evenly distributed, and the problem of uneven thermal stress and other reliability is solved.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Drawings
The invention may be more particularly described, by way of example, with reference to the accompanying drawings, which are not drawn to scale, and in which:
fig. 1 is an external structural perspective view of a package structure of a multi-tube parallel asymmetric silicon carbide double-sided heat dissipation module according to an embodiment of the present invention;
FIG. 2 is a side view of an external structure of a package structure according to one embodiment of the invention;
FIG. 3 is a top view of the internal structure of a package structure according to one embodiment of the invention;
fig. 4 is a bottom view of the internal structure of a package structure according to one embodiment of the invention;
FIG. 5 is a schematic diagram of a half-bridge circuit corresponding to a package structure according to an embodiment of the invention; and
fig. 6 is a flow chart of a method of packaging a multi-tube parallel asymmetric silicon carbide double-sided heat dissipation module according to an embodiment of the invention.
The same reference numbers are used throughout the drawings to refer to the same elements or structures.
Detailed Description
It is easily understood that according to the technical solution of the present invention, a person skilled in the art can propose various alternative structures and implementation ways without changing the spirit of the present invention. Therefore, the following detailed description and the accompanying drawings are merely illustrative of the technical aspects of the present invention, and should not be construed as all of the present invention or as limitations or limitations on the technical aspects of the present invention.
The terms of orientation of up, down, left, right, front, back, top, bottom, and the like referred to or may be referred to in this specification are defined relative to the configuration shown in the drawings, and are relative terms, and thus may be changed correspondingly according to the position and the use state of the device. Therefore, these and other directional terms should not be construed as limiting terms. Furthermore, the terms "first," "second," "third," and the like are used for descriptive and descriptive purposes only and not for purposes of indication or implication as to the relative importance of the respective components.
As known to those skilled in the art, a transistor is a solid-state semiconductor device (including a diode, a triode, a field-effect transistor, a thyristor, etc., and sometimes referred to as a bipolar device), and has multiple functions of detecting, rectifying, amplifying, switching, voltage stabilizing, signal modulating, etc. The transistor, which is a type of variable current switch, is capable of controlling an output current based on an input voltage. The transistor controls its own switching by an electrical signal, and the switching speed can be very fast, wherein the switching speed in a laboratory can reach more than 100 GHz.
In general, a transistor generally includes three electrodes, i.e., a source, a drain, and a gate. The channel is disposed between the source and the drain. When no voltage is applied to the gate, no effective charge is accumulated in the channel, no effective current is generated between the source and the drain, and the transistor is in an off state. In contrast, when a voltage is applied to the gate, effective charges are collected in the channel to form a channel that is conductive from the source to the drain, and the transistor is in an on state.
In addition, in the embodiment of the present invention, the power chip used is a MOSFET, that is, a metal oxide semiconductor field effect transistor.
Referring to fig. 1, fig. 1 is an external structural perspective view of a package structure of a multi-tube parallel asymmetric silicon carbide double-sided heat dissipation module according to an embodiment of the present invention. As shown in fig. 1, in the package structure, a main power DC + terminal 7, a main power DC-terminal 6, an upper bridge arm source terminal 1, and an upper bridge arm gate driving terminal 2 are connected to corresponding copper blocks inside a bottom layer DBC liner plate 8; and a main power AC terminal 3, a lower bridge arm grid driving terminal 4 and a lower bridge arm source terminal 5 are connected to corresponding copper blocks in the top layer DBC lining plate 9.
The main power DC + terminal 7 and the main power DC-terminal 6 belong to the main power input terminal, while the main power AC terminal 3 is the main power output terminal. Although the main power DC + terminal 7, the main power DC-terminal 6 and the main power AC terminal 3 are each in the shape of a thin plate, they may also be in the form of post terminals (and optionally copper post terminals). In the case where the main power DC + terminal 7, the main power DC-terminal 6 and the main power AC terminal 3 are all copper pillar terminals, these terminals may be arranged in parallel and/or as close to each other as desired to improve stability and reduce loop parasitic inductance.
As clearly shown in fig. 1, upper arm source terminal 1 and upper arm gate drive terminal 2 in the shape of rods, arm gate drive terminal 4 and lower arm source terminal 5 in the shape of rods, and main power AC terminal are arranged on one side of the package structure, while main power DC + terminal 7 and main power DC-terminal 6 are arranged on the opposite side of the package structure. The upper arm source terminal 1, the upper arm gate drive terminal 2, the arm gate drive terminal 4, and the lower arm source terminal 5 collectively constitute a drive circuit terminal.
As is known, the power terminals may have different shapes and numbers, in addition to those disclosed in the embodiment of fig. 1, to meet different arrangements and power requirements.
As shown in fig. 2, an external structural side view of a package structure according to one embodiment of the present invention is provided. In fig. 2, the drains of the upper arm switching tubes (i.e., transistors) 10 are connected to respective copper blocks (i.e., DC + copper blocks 20 as described below) of the bottom layer DBC patch 8 by silver sintering, and the sources of the upper arm switching tubes 10 are connected to the upper arm pads 12 by silver sintering, which in turn are connected to respective copper blocks (i.e., AC copper blocks 27 as described below) of the top layer DBC patch 9 by silver sintering.
On the other hand, the drain of lower arm switch tube (i.e., transistor) 11 is connected by silver sintering on the corresponding copper block (i.e., AC copper block 27 as described below) of top layer DBC patch 9, and the source of lower arm switch tube 11 is connected by silver sintering on lower arm pad 13, which in turn is connected by silver sintering on the corresponding copper block (i.e., DC-copper block 21 as described below) of bottom layer DBC patch 8.
The upper leg drive resistors 14 are connected to respective copper blocks (i.e., sixth copper blocks 28 as described below) of the bottom DBC substrate 8 and to the gates of the upper leg switching tubes 10 by gate bond wires, while the lower leg drive resistors 15 are connected to respective copper blocks (i.e., fifth copper blocks 24 as described below) of the top DBC substrate 9 and to the gates of the lower leg switching tubes 11 by gate bond wires.
Compared with the high-temperature lead-free solder in the traditional soldering, the sintering connecting layer of the silver sintering technology is silver, and has excellent electric conduction and heat conduction performance. In addition, the melting point of silver is up to 961 o C, so that no melting point less than 300 is generated o The fatigue phenomenon occurring in the solder bonding layer of C has very high reliability, and the life of the power module can be further extended.
As shown in fig. 3, a top view of the internal structure of the package structure according to an embodiment of the present invention is provided, and at the same time, as shown in fig. 4, a bottom view of the internal structure of the package structure according to an embodiment of the present invention is provided. The upper bridge arm switch tube 10 may be formed by connecting a plurality of silicon carbide power chips (MOSFETs) in parallel, and the lower bridge arm switch tube 11 may be formed by connecting a plurality of silicon carbide power chips (MOSFETs) in parallel. In the present embodiment, the upper arm switch 10 is formed by connecting four silicon carbide power chips (MOSFETs) in parallel, and the lower arm switch 11 is formed by connecting four silicon carbide power chips (MOSFETs) in parallel. The eight silicon carbide power chips (MOSFETs) collectively form a synchronous rectifying half-bridge circuit and are soldered on respective bottom and top DBC pads 8 and 9 stacked on each other and disposed facing each other.
As clearly depicted in fig. 3 and 4, the upper surface copper layer of the underlying DBC backing plate 8 is a circuit layer and may be divided into five sections, namely a first copper block 18, a second copper block 19, a DC + copper block 20, a DC-copper block 21, and a sixth copper block 28. On the other hand, the lower surface copper layer of the top DBC backing plate 9 is a circuit layer and can be divided into four sections, i.e., a third copper block 22, a fourth copper block 23, a fifth copper block 24, and an AC copper block 27. Further, in the case where the power module includes eight silicon carbide power chips (MOSFETs) divided into two groups, four sixth copper blocks 28 and four upper arm driving resistors 14, and four fifth copper blocks 24 and four lower arm driving resistors 15 are provided, respectively.
Furthermore, with respect to the bottom layer DBC substrate 8, the first copper block 18 is connected to the source of the power chip of the upper arm switch tube 10 by the upper arm source bonding wire 17; and the second copper block 19 is connected to one end of the driving resistor 14 of the upper arm switch tube 10, and the other end of the driving resistor 14 is connected to the sixth copper block 28, and then connected to the gate of the power chip of the upper arm switch tube 10 through the upper arm gate bonding wire 16. Further, the DC + copper block 20 is connected to the drain electrode of the power chip of the upper arm switching tube 10 and is also connected to the main power DC + terminal 7 by silver sintering, wherein four silicon carbide power chips (MOSFETs) constituting the upper arm switching tube 10 are uniformly connected to the upper surface of the DC + copper block 20 at the same interval, and the DC + terminal 7 is lapped over the upper surface of the DC + copper block 20; the DC-copper block 21 is connected to the lower bridge arm pad 13 by silver sintering and to the main power DC-terminal 6, wherein the main power DC-terminal 6 is bonded to the upper surface of the DC-copper block 21.
Meanwhile, regarding the top layer DBC substrate 9, the fourth copper block 23 is connected to the source of the power chip of the upper arm switch tube 11 through the lower arm source bonding wire 25; and the third copper block 22 is connected with one end of the driving resistor 15 of the lower arm switch tube 11, and the other end of the driving resistor 15 is connected to the fifth copper block 24 and then connected to the gate of the power chip of the lower arm switch tube 11 through the lower arm gate bonding wire 26. Further, an AC copper block 27 is connected to the upper arm pad 12 by silver sintering, and on the other hand, the AC copper block 27 is connected to the drain of the power chip of the lower arm switching tube 11 by silver sintering while being connected to the main power AC terminal 3, wherein four silicon carbide power chips (MOSFETs) constituting the lower arm switching tube 11 are uniformly connected to the lower surface of the AC copper block 27 at the same pitch, and the main power AC terminal 3 is overlapped to the lower surface of the AC copper block 27.
The DBC liner plate comprises a circuit layer formed by a copper block, a heat dissipation layer and an insulating layer arranged between the circuit layer and the heat dissipation layer. The power chip, the power terminals and the driving terminals are bonded on the circuit layer. The circuit layer is made of oxygen-free copper material, and the surface of the circuit layer is subjected to nickel plating treatment, so that the oxidation resistance of the surface is enhanced, and the wire bonding is facilitated. AlN or Si can be used as the insulating layer 3 N 4 A ceramic. Si 3 N 4 The ceramic has higher yield strength, is not easy to break and has higher reliability than Al 2 O 3 The ceramic is higher. When the power chip in the packaging structure works, the insulating layer transfers heat generated by the power chip to the heat dissipation layer for heat dissipation, and meanwhile, the insulation of electric parts inside the packaging structure to an external radiator is realized.
In addition, the resistance value of a single one of upper arm drive resistor 14 and lower arm drive resistor 15 depends on the distance of its corresponding power chip to the corresponding main power DC-terminal 6 or main power DC + terminal 7. Since the closer the power chip is to the main power DC-terminal 6 and the main power DC + terminal 7, the smaller the parasitic inductance of the power loop where the power chip is located, and the larger the dynamic current at the transient time of switching is, the larger the loss is, the larger the driving resistance is provided to the power chip, so that the switching loss is evenly distributed, and the problem of uneven thermal stress reliability is avoided.
Fig. 5 is a schematic diagram of a half-bridge circuit corresponding to a package structure according to an embodiment of the invention. The half-bridge circuit configuration shown in fig. 5 is formed by a main power DC + terminal 7, a main power DC-terminal 6, a main power AC terminal 3, an upper arm gate drive terminal 2, an upper arm source terminal 1, a lower arm gate drive terminal 4, a lower arm source terminal 5, an upper arm switching transistor 10, an upper arm drive resistor 14, a lower arm switching transistor 11, a lower arm drive resistor 15, and electrical connections therebetween. Specifically, the half-bridge circuit is a synchronous rectification half-bridge circuit, the upper arm switching tube 10 is an upper arm of the synchronous rectification half-bridge circuit, and the lower arm switching tube 11 is a lower arm of the synchronous rectification half-bridge circuit. In addition, an upper arm switching tube 10 and a lower arm switching tube 11 are connected in series between the main power DC + terminal 7 and the main power DC-terminal 6. The upper arm switching tube 10 is provided with an upper arm gate drive terminal 2, an upper arm drive resistor 14, and an upper arm source terminal 1, and the lower arm switching tube 11 is provided with a lower arm gate drive terminal 4, a lower arm drive resistor 15, and a lower arm source terminal 5.
When the module works, a driving signal is transmitted to the grid electrode of the power chip in the bridge arm switching tube through the driving resistor so as to control the turn-off of the power chip.
Fig. 6 is a flowchart of an encapsulation method of a multi-tube parallel asymmetric silicon carbide double-sided heat dissipation module according to an embodiment of the present invention, and the encapsulation method may include the steps of:
a first step S101 of selecting a bottom DBC backing plate and a top DBC backing plate, wherein each of the bottom DBC backing plate and the top DBC backing plate comprises a circuit layer, an insulating layer and a heat dissipation layer, and the material of the insulating layer is selected to be silicon nitride (Si) having a high thermal conductivity 3 N 4 ) A material. In addition, corresponding patterns are etched on both the top DBC liner and the lower DBC liner. Specifically, the uppermost circuit layer of the lower DBC backing plate 8 is divided into five sections, namely, a first copper block 18, a second copper block 19, a DC + copper block 20, a DC-copper block 21, and a sixth copper block 28. On the other hand, the lowermost circuit layer of the top DBC substrate 9 is divided into four sections, i.e., a third copper block 22, a fourth copper block 23, a fifth copper block 24, and an AC copper block 27;
in the second step S102, firstly, a nano silver material is uniformly coated on the corresponding soldering position of the copper block of the bottom DBC lining board, then a silicon carbide power chip (MOSFET), a gasket and a terminal to be soldered are placed on the soldering position and fixed by using a clamp, and finally, a vacuum reflow soldering method is adopted to heat and sinter. The silicon carbide power chips (MOSFET) comprise four silicon carbide power chips (MOSFET) which are arranged in a straight line at the same interval, the gaskets comprise four lower bridge arm gaskets, and the terminals are an upper bridge arm source terminal 1, an upper bridge arm gate driving terminal 2, a main power DC + terminal 7 and a main power DC-terminal 6. The four silicon carbide power chips (MOSFETs) are connected in parallel to form the upper arm switching tube 10. Vacuum reflow is the soldering of a product in a vacuum environment to protect the product and the solder (i.e., nanosilver) from oxidation. The vacuum reflow soldering system is relatively closed and needs vacuum auxiliary conditions, and under the conditions, the vacuum reflow soldering can efficiently discharge bubbles generated when the soldering flux volatilizes, reduce the voidage of the soldering surface of the product and improve the soldering quality of the product;
and a third step S103, uniformly coating a nano silver material on the corresponding welding position of the copper block of the top DBC lining plate, placing a silicon carbide power chip (MOSFET), a gasket and a terminal to be welded on the welding position, fixing by using a clamp, and finally heating and sintering by adopting a vacuum reflow soldering method. The silicon carbide power chips (MOSFETs) include four silicon carbide power chips (MOSFETs) arranged in a straight line at the same interval, the pads include four upper arm pads, and the terminals are a lower arm gate driving terminal 4, a lower arm source terminal 5, and a main power AC terminal 3. The four silicon carbide power chips (MOSFETs) are connected in parallel to form a lower bridge arm switching tube 11;
a fourth step S104 of connecting electrodes of the silicon carbide power chip (MOSFET) to the corresponding copper blocks and connecting terminals to the corresponding copper blocks on the bottom-layer DBC substrate and the top-layer DBC substrate, respectively, by using a wire bonding method. Specifically, regarding the bottom layer DBC substrate 8, the first copper block 18 is connected to the source of the power chip of the upper arm switching tube 10 through the upper arm source bonding wire 17; and the second copper block 19 is connected with one end of the driving resistor 14 of the upper arm switch tube 10, and the other end of the driving resistor 14 is connected to the sixth copper block 28 and then connected to the gate of the power chip of the upper arm switch tube 10 through the upper arm gate bonding wire 16. Further, the DC + copper block 20 is connected to the drain electrode of the power chip of the upper arm switching tube 10 and is also connected to the main power DC + terminal 7 by silver sintering, wherein four silicon carbide power chips (MOSFETs) constituting the upper arm switching tube 10 are uniformly connected to the upper surface of the DC + copper block 20 at the same interval, and the DC + terminal 7 is lapped over the upper surface of the DC + copper block 20; and the DC-copper block 21 is connected to the main power DC-terminal 6, wherein the main power DC-terminal 6 is bonded to the upper surface of the DC-copper block 21. Meanwhile, regarding the top layer DBC substrate 9, the fourth copper block 23 is connected to the source of the power chip of the upper arm switch tube 11 through the lower arm source bonding wire 25; and the third copper block 22 is connected with one end of the driving resistor 15 of the lower arm switch tube 11, and the other end of the driving resistor 15 is connected to the fifth copper block 24 and then connected to the gate of the power chip of the lower arm switch tube 11 through the lower arm gate bonding wire 26. Further, the AC copper block 27 is connected to the drain electrode of the power chip of the lower arm switching tube 11 and also to the main power AC terminal 3 by silver sintering, wherein four silicon carbide power chips (MOSFETs) constituting the lower arm switching tube 11 are uniformly connected to the lower surface of the AC copper block 27 at the same pitch, and the main power AC terminal 3 is lapped on the lower surface of the AC copper block 27;
in a fifth step S105, a nano silver material is uniformly coated on the pads of the silicon carbide power chip (MOSFET), and then the top DBC substrate is stacked on the bottom DBC substrate in a manner of facing each other, wherein the corresponding pads are aligned with the copper blocks of the corresponding silicon carbide power chip (MOSFET) and fixed by using a jig, and finally, a vacuum reflow method is used for heat sintering. Specifically, the DC-copper block 21 is connected to the lower arm pad 13 by silver sintering, and the AC-copper block 27 is connected to the upper arm pad 12 by silver sintering; and
a sixth step S106 is to weld the heat sink on the outer sides (i.e., heat dissipation layers) of the bottom DBC backing plate and the top DBC backing plate, and to pour epoxy resin between the bottom DBC backing plate and the top DBC backing plate to form a plastic package. The plastic packaging material can play the role of insulation and dust prevention.
The package structure of the multi-chip parallel asymmetric silicon carbide module may further include other necessary components (e.g., detection terminals, protection terminals, module housing, etc.) for realizing the functions thereof, which are well known to those skilled in the art and will not be described herein again.
Compared with the prior art, the packaging structure of the multi-chip parallel asymmetric silicon carbide module disclosed by the invention has the advantages that the driving resistors with different sizes are arranged according to the distance from the direct current terminal to each power chip, so that the problem of different parasitic inductances of a power loop caused by different lengths of conductors from the DC + terminal to the DC-terminal through the power chips is solved, the switching loss is uniformly distributed, and the problem of reliability such as uneven thermal stress is solved. In this case, the packaging structure of the present invention can better accommodate fast switching processes and high frequency power electronic converters.
It should be understood that the foregoing description is only exemplary of the invention and is not intended to limit the invention. It should be noted that several improvements, modifications and variations of the present invention may be made by those skilled in the art, but these improvements, modifications and variations do not depart from the spirit of the present invention and are deemed to fall within the scope of the present invention.
Parts list
1 upper bridge arm source terminal
2 upper bridge arm grid driving terminal
3 main power AC terminal
4 lower bridge arm grid drive end
5 lower bridge arm source terminal
6 main power DC-terminal
7 main power DC + terminal
8 bottom layer DBC lining board
9 top layer DBC lining board
10 upper bridge arm switch tube
11 lower bridge arm switch tube
12 upper bridge arm pad
13 lower bridge arm gasket
14 upper bridge arm driving resistor
15 lower bridge arm driving resistor
16 upper bridge arm grid bonding wire
17 upper bridge arm source electrode bonding wire
18 first copper block
19 second copper block
20 DC + copper block
21 DC-copper block
22 third copper block
23 fourth copper block
24 fifth copper block
25 lower bridge arm source electrode bonding wire
26 lower bridge arm grid bonding wire
27 AC copper block
28 sixth copper block.
Claims (10)
1. A packaging structure of a multi-chip parallel asymmetric silicon carbide module is characterized by comprising a bottom layer direct copper-clad liner plate, a top layer direct copper-clad liner plate, a plurality of silicon carbide power chips, a plurality of driving resistors, gaskets and power terminals, wherein the top layer direct copper-clad liner plate is opposite to the bottom layer direct copper-clad liner plate,
wherein the power terminals comprise a main power DC + terminal, a main power DC-terminal, and a main power AC terminal,
wherein the plurality of silicon carbide power chips are connected in parallel to form a half-bridge circuit, and the plurality of silicon carbide power chips, the plurality of driving resistors and the gasket are arranged between the bottom layer direct copper-clad backing plate and the top layer direct copper-clad backing plate, and
wherein a resistance value of each of the plurality of drive resistors is inversely proportional to a distance of each of the plurality of silicon carbide power chips from the corresponding main power DC + terminal or main power DC-terminal.
2. The package structure of a multi-chip parallel asymmetric silicon carbide module according to claim 1, wherein the plurality of silicon carbide power chips comprises a first group of silicon carbide power chips and a second group of silicon carbide power chips, and the first silicon carbide power chips are connected in parallel to each other and attached to the bottom layer direct copper clad laminate to form an upper leg of the half bridge circuit, and the second silicon carbide power chips are connected in parallel to each other and attached to the top layer direct copper clad laminate to form a lower leg of the half bridge circuit.
3. The package structure of the multi-chip parallel asymmetric silicon carbide module according to claim 1, wherein a first heat sink and a second heat sink are connected to the outer sides of the top direct copper-clad substrate and the bottom direct copper-clad substrate, respectively.
4. The package structure of the multi-chip parallel asymmetric silicon carbide module according to claim 2, wherein the top layer direct copper-clad substrate and the bottom layer direct copper-clad substrate each comprise a circuit layer composed of a copper block, a heat dissipation layer, and an insulating layer disposed between the circuit layer and the heat dissipation layer.
5. The multi-chip parallel asymmetric carbonization of claim 4The packaging structure of the silicon module is characterized in that the insulating layer is made of Si 3 N 4 Is made of ceramics.
6. The package structure of a multi-chip parallel asymmetric silicon carbide module according to claim 4, wherein the circuit layers of the bottom direct copper clad laminate include a first copper block, a second copper block, a DC + copper block, a DC-copper block, and a sixth copper block, and the circuit layers of the top direct copper clad laminate include a third copper block, a fourth copper block, a fifth copper block, and an AC copper block.
7. The package structure of the multi-chip parallel asymmetric silicon carbide module according to claim 6, wherein the package structure comprises an upper bridge arm source terminal, an upper bridge arm gate drive terminal, a lower bridge arm source terminal, and a lower bridge arm gate drive terminal; and is
The drain electrode of the silicon carbide power chip of the upper bridge arm is connected to the DC + copper block of the bottom layer direct copper-clad liner plate, the source electrode of the silicon carbide power chip of the upper bridge arm is connected to the first copper block of the bottom layer direct copper-clad liner plate through an upper bridge arm source electrode bonding wire, the grid electrode of the silicon carbide power chip of the upper bridge arm is connected to the sixth copper block of the bottom layer direct copper-clad liner plate through an upper bridge arm grid electrode bonding wire and is connected with the second copper block and the upper bridge arm grid electrode driving terminal through a driving resistor,
the drain electrode of the silicon carbide power chip of the lower bridge arm is connected to the AC copper block of the top layer direct copper-clad lining plate, the source electrode of the silicon carbide power chip of the lower bridge arm is connected to the fourth copper block of the top layer direct copper-clad lining plate through a lower bridge arm source electrode bonding wire, and the grid electrode of the silicon carbide power chip of the lower bridge arm is connected to the fifth copper block of the top layer direct copper-clad lining plate through a lower bridge arm grid electrode bonding wire and is connected with the third copper block and the lower bridge arm grid electrode driving terminal through a driving resistor.
8. The package structure of a multi-chip parallel asymmetric silicon carbide module according to claim 1, wherein the main power DC + terminal and the main power DC-terminal are located on a side of the package structure, and the main power AC terminal is located on another side of the package structure opposite the side.
9. The package structure of the multi-chip parallel asymmetric silicon carbide module according to claim 2, wherein the pads comprise an upper bridge arm pad and a lower bridge arm pad.
10. A packaging method for a packaging structure of a multi-chip parallel asymmetric silicon carbide module according to any of claims 1 to 9, characterized in that it comprises the following steps:
selecting a bottom layer direct copper-clad liner plate and a top layer direct copper-clad liner plate, and etching copper block structures of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate;
welding an upper bridge arm silicon carbide power chip, an upper bridge arm driving terminal, main power DC + and DC-terminals and a lower bridge arm gasket to the bottom layer and directly coating a copper lining plate;
welding a lower bridge arm silicon carbide power chip, a lower bridge arm driving terminal, a main power AC terminal and an upper bridge arm gasket to the top layer and directly coating a copper lining plate;
connecting electrodes of the silicon carbide power chip with corresponding copper blocks and connecting terminals with the corresponding copper blocks by using bonding wires on the bottom layer direct copper-clad lining plate and the top layer direct copper-clad lining plate respectively;
stacking the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate, and connecting corresponding copper blocks of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate with corresponding gaskets; and
and welding a radiator on the outer sides of the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate, and injecting epoxy resin between the bottom layer direct copper-clad liner plate and the top layer direct copper-clad liner plate to form a plastic package structure.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202210427689.0A CN114914235A (en) | 2022-04-22 | 2022-04-22 | Packaging structure and packaging method of multi-chip parallel asymmetric silicon carbide module |
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| CN202210427689.0A CN114914235A (en) | 2022-04-22 | 2022-04-22 | Packaging structure and packaging method of multi-chip parallel asymmetric silicon carbide module |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116913910A (en) * | 2022-11-25 | 2023-10-20 | 苏州悉智科技有限公司 | Power module packaging structure of laminated wiring |
| CN117393528A (en) * | 2023-10-30 | 2024-01-12 | 西安电子科技大学 | Axisymmetric silicon carbide power module packaging structure |
-
2022
- 2022-04-22 CN CN202210427689.0A patent/CN114914235A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116913910A (en) * | 2022-11-25 | 2023-10-20 | 苏州悉智科技有限公司 | Power module packaging structure of laminated wiring |
| CN116913910B (en) * | 2022-11-25 | 2024-03-22 | 苏州悉智科技有限公司 | Power module packaging structure of laminated wiring |
| CN117393528A (en) * | 2023-10-30 | 2024-01-12 | 西安电子科技大学 | Axisymmetric silicon carbide power module packaging structure |
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