CN112886558A - Power semiconductor chip parallel structure and drive circuit overcurrent failure suppression method thereof - Google Patents
Power semiconductor chip parallel structure and drive circuit overcurrent failure suppression method thereof Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/02—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess current
- H02H9/026—Current limitation using PTC resistors, i.e. resistors with a large positive temperature coefficient
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
- H01L2224/48139—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Abstract
The invention discloses a power semiconductor chip parallel structure and a driving circuit overcurrent failure suppression method thereof, and belongs to the technical field of power electronic devices. The invention designs a novel parallel structure of power semiconductor chips, which comprises a power drain port, a power source port, an auxiliary source port, a grid port and a plurality of power semiconductor chips connected in parallel, wherein a thermosensitive element with positive temperature characteristic is added between an auxiliary source and a chip source based on the analysis of the phenomenon of overcurrent failure from the source of the power semiconductor chips connected in parallel to the auxiliary source, and the thermosensitive element can serve as a driving loop resistor in the normal operation process without influencing the operation; under the aging or fault state of the parallel structure, the unbalanced current flows through the thermistor, so that the temperature of the thermistor is increased, the resistance value of the thermistor is increased, the amplitude of the unbalanced current on a chip driving circuit is inhibited, the overcurrent failure of the driving circuit is avoided, and the service life and the operation reliability of the power semiconductor module are improved.
Description
Technical Field
The invention belongs to the technical field of power electronic devices, and particularly relates to a parallel structure of power semiconductor chips and a driving circuit overcurrent failure suppression method thereof.
Background
The power semiconductor chip is widely applied to occasions of high-capacity converters such as a photovoltaic power generation system, a solid-state transformer and alternating current traction, and the requirement of an application scene on high power output capacity is met in a multi-chip parallel mode. Due to the spatial limitation of the two-dimensional layout mode, external circuit parameters, such as resistance and inductance, of the driving circuit and the power circuit corresponding to each parallel chip inevitably have unbalanced sizes, and the aging of connecting devices such as solder, binding wires and the like after the module runs for a long time can further increase the unbalanced degree of parasitic parameters between the parallel chips, so that the power current distribution between the parallel chips is not uniform, and part of source binding wires bearing larger current chips are gradually heated and fail or even fall off. Furthermore, the source impedances of the parallel chips are inconsistent, unbalanced current occurs, and after the unbalanced current flows into the module driving loop, the binding line of the driving loop is broken due to overheating, so that a new failure mode is initiated.
In the 20 th European Conference on Power Electronics and Applications in 2018, the argument set of "Impact of key-Source resistance on Current shaping and Failure Detection in multi-chip Power Modules" written by n.baker, f.ian nuzzo, h.li describes the module Failure phenomenon caused by the non-uniform auxiliary Source parasitic parameters in a multi-chip Power module, which indicates that the gate Current on the core of the Power semiconductor module gradually increases during the through-Current operation to cause the gate bonding line to melt due to overheating, and at the same time, the Power drain port and the Power Source port do not melt, and the corresponding bonding line is intact. Further described is a technique for chip current sharing and fault detection with auxiliary source resistance. However, in order to ensure that the normal operation of the module is not affected after the auxiliary source resistor is added, the resistance value of the auxiliary source resistor needs to be as low as possible, and the low resistance value reduces the current sharing optimization effect of the chip.
The current sharing method for parallel chips in the existing power semiconductor module is generally realized in a module drive or power loop: if the same impedance parameters are adopted in the driving circuit, the grid voltage among the parallel chips is kept consistent, and the effect of uniform current sharing of the parallel chips is achieved.
This is described in the 25 th international conference on power semiconductor devices and integrated circuits (ISPSD) paper set by m.sasaki, h.nishio, a.short, w.t.ng in 2013 in "Current balancing controlled for parallel connected IGBTs using programmable gate output response". According to this document, a method is described in which the programmable drive technique adjusts the output resistance difference between parallel chips to achieve current equalization.
Or mutually coupled coils are added into the power loop, and the currents flowing between the power ports are equalized through the electromagnetic coupling effect.
This is described in 2019 in the IEEE applied Power electronics conference and exhibition (APEC) paper set by S.Lu, X.Deng, S.Li, E.Rong, "A Passive Transmission Current Balancing Method for Multiple parallel SiC-MOSFET Half-Bridge Modules". According to this document, a method for transient current balancing of parallel silicon carbide modules using passive devices with mutually coupled inductances as the main component is proposed.
The above methods all have certain effects, but cannot inhibit the power current from flowing into the driving loop, and the design methods all need to consider the transfer characteristics and the output characteristics of the chip at different temperatures, so the design process is complex. Meanwhile, the traditional method for detecting the health state of the power semiconductor module based on the drain-source voltage of the device cannot acquire the health state information of the module driving loop.
Disclosure of Invention
Aiming at the problems, the invention provides a power semiconductor chip parallel structure and a driving circuit overcurrent failure suppression method thereof, only a passive device needs to be added, the structure is simple, the suppression effect on unbalanced power current can be automatically realized, the service life and the operation reliability of a power module are improved, and the passive device does not have any influence on the normal operation of the parallel structure.
In order to achieve the purpose, the invention adopts the following technical scheme:
a power semiconductor chip parallel structure comprises a power drain port, a power source port, an auxiliary source port, a grid port and a plurality of power semiconductor chips connected in parallel;
the chip drain electrode in the power semiconductor chip is connected with the power drain electrode port, the chip grid electrode in the power semiconductor chip is connected with the grid electrode port, the chip source electrode in the power semiconductor chip is respectively connected with the power source electrode port and the auxiliary source electrode port, and a thermosensitive element with positive temperature characteristic is arranged between the chip source electrode and the auxiliary source electrode port.
Furthermore, a connecting device is arranged between the power semiconductor chip and the power drain port, the power source port or the grid port, and the connecting device is one or more of solder, a binding wire, a substrate copper layer and a copper power terminal.
Further, the power semiconductor chip is an IGBT, a MOSFET or a BJT, and the material is silicon, silicon carbide or gallium nitride.
Further, the number of the power semiconductor chips is at least 2, and the power semiconductor chips are in the form of bare chips, single-tube packages or module packages.
Further, the thermosensitive element is arranged on the surface of the metal electrode of the power semiconductor chip or the conductive copper layer inside the parallel structure.
Further, the thermosensitive element is a thermistor, and the resistance value of the thermistor at room temperature is 0-2 omega.
Another objective of the present invention is to provide a method for suppressing an overcurrent failure of a driving circuit based on the above parallel structure of power semiconductor chips, wherein when the parallel structure of power semiconductor chips normally operates, no current flows through the thermistor, the temperature of the thermistor is not affected at room temperature, and the resistance value is maintained at 0-2 Ω, which is used as a driving circuit resistor and does not affect the normal operation;
after the power semiconductor chip parallel structure runs for a long time, if the structure is aged or fails, the power current from the chip source electrode to the power source electrode port is unbalanced, and the current of the chip source electrode is kept unchanged due to the fact that the potential difference between the chip grid electrode and the chip source electrode is unchanged, so that part of the power current is forced to flow to the power source electrode port through the thermistor with the positive temperature characteristic between the chip source electrode and the auxiliary source electrode port; when the unbalanced current flows into the driving circuit of the power semiconductor chip parallel structure, the temperature of the thermistor rises, the resistance value becomes large, so that the unbalanced current on the driving circuit is reduced, the heating power of the thermistor is reduced, the temperature and the resistance value are further reduced gradually, and finally, the stable operation is recovered.
Compared with the prior art, the invention has the advantages that:
because the difference between the parallel chips in the parallel structure of the power semiconductor chip is influenced by the module packaging design and the manufacturing process, the power current from the chip source electrode to the power source electrode of the parallel chip is easily unbalanced, and the optimization effect of the prior art is limited or the power current cannot be inhibited from flowing into a driving loop. The thermistor is added between the auxiliary source electrode port and each parallel chip source electrode, so that on one hand, the manufacturing process is simple and easy to realize, and the thermistor can serve as a driving loop resistor in the normal operation process of the parallel structure without influencing the normal operation; on the other hand, when the parallel structure is aged or in a fault state, because the source electrode current of the parallel chip is determined by the driving voltage, the unbalanced power current flows to the power source electrode through the auxiliary source electrode, so that the overheating failure of the connecting device of the driving circuit of the parallel chip is caused.
Drawings
FIG. 1 is a circuit model of a parallel configuration of power semiconductor chips;
FIG. 2 is a schematic diagram of the arrangement of parallel chips in a power semiconductor module;
FIG. 3 is a circuit model of a parallel configuration of power semiconductor chips with the addition of a thermal sensitive element;
FIG. 4 is a schematic diagram of the arrangement of parallel chips in a power semiconductor module with the addition of a thermal sensing element;
FIG. 5 is a graph of resistance of a thermistor as a function of temperature;
wherein: 1-power semiconductor chip, 2-power drain port, 3-power source port, 4-auxiliary source port, 5-gate port, 6-chip drain, 7-chip source, 8-chip gate, 9-auxiliary source resistor (thermistor).
Detailed Description
For a better understanding of the present invention, reference will now be made in detail to the present embodiments of the invention as illustrated in the accompanying drawings.
Aiming at the problem that the power current can not be inhibited from flowing into a driving loop in the prior art, the invention designs a power semiconductor chip parallel structure capable of inhibiting unbalanced power current, which mainly comprises a power drain port 2, a power source port 3, an auxiliary source port 4, a grid port 5 and a plurality of power semiconductor chips 1 connected in parallel.
The chip drain 6 in the power semiconductor chip 1 is connected with the power drain port 2, the chip grid 8 in the power semiconductor chip 1 is connected with the grid port 5, the chip source 7 in the power semiconductor chip 1 is respectively connected with the power source port 3 and the auxiliary source port 4, and a thermosensitive element 9 with positive temperature characteristic is arranged between the chip source 7 and the auxiliary source port 4.
In one embodiment of the present invention, a connection device is provided between the power semiconductor chip 1 and the power drain port 2, the power source port 3 or the gate port 5, and the connection device is one or more of solder, a bonding wire, a substrate copper layer and a copper power terminal.
Modeling and analyzing a parallel structure of the power semiconductor chip:
as shown in fig. 1, part of the connecting elements in the parallel structure of the power semiconductor chips are equivalently converted into parasitic resistance and parasitic inductance, and the converted model structure comprisesThe power semiconductor chip comprises a power semiconductor 1, a connecting device, a power drain port 2, a power source port 3, an auxiliary source port 4 and a grid port 5, wherein the power semiconductor chip 1 comprises a chip drain 6, a chip source 7 and a chip grid 8; the chip parallel model in the structure comprises a power semiconductor chip 1, a parasitic resistor R between a power drain port 2 and a chip drain 6d1、Rd2And parasitic inductance Ld1、Ld2Parasitic resistance R between power source port 3 and chip source 7s1、Rs2And parasitic inductance Ls1、Ls2Parasitic resistance R between gate port 5 and chip gate 8g1、Rg2And parasitic inductance Lg1、Lg2Auxiliary source port to chip source parasitic resistance Re1、Re2。
The properties of the parasitic resistance and parasitic inductance in the above were analyzed as follows:
parasitic resistance R between power drain port 2 and chip drain 6 of power semiconductor moduled1、Rd2And parasitic inductance Ld1、Ld2The bulk resistance and the bulk inductance of components such as a substrate copper layer and a power terminal which are connected with the chip drain electrode 6 are included; the parasitic resistance and the parasitic inductance of the part have small difference between the parallel chips and do not change obviously along with the use of the power semiconductor module.
Parasitic resistance R between gate port 5 and chip gate 8 of power semiconductor moduleg1、Rg2And parasitic inductance Lg1、Lg2The body resistance and the body inductance of connecting parts such as chip grid internal resistance, binding lines and the like in the power semiconductor module are included; the difference between the parasitic resistance and the parasitic inductance between the gate port 5 and the chip gate 8 between the parallel chips is small and does not change obviously with the use of the power semiconductor module.
Parasitic resistance R between power source port 3 and chip source 7 of power semiconductor modules1、Rs2And parasitic inductance Ls1、Ls2The body resistance and the body inductance which are connected with the chip source electrode 7 and comprise binding lines, substrate copper layers, power terminals and the like are packaged by a module according to the difference between parallel chipsThe chip power binding line is easy to age or fall off and parasitic resistance is easy to increase due to the influence of design and manufacturing process, long-time operation of the parallel structure, defects of the manufacturing process and the like, and the chip power binding line is gradually enlarged in the using process of the power semiconductor module, so that the power current from the chip source electrode to the power source electrode of the parallel chip is unbalanced.
Since the source current of the power semiconductor chip is only determined by the potential difference between the gate and the source of the chip, when the driving voltage is unchanged during the operation of the module, the source current of the chip remains unchanged, so that part of the power current is forced to flow to the power source port 3 through the parasitic current between the source 7 and the auxiliary source of the chip, the current path is shown by a dotted line in fig. 1, and the power current causes the driving loop connecting device to generate heat and even break, thereby accelerating the package failure of the module.
Based on the above model and the failure mechanism of the driving circuit, as shown in fig. 3, compared with fig. 2, the present invention adds a thermistor R with positive temperature characteristics between the auxiliary source port 4 and the chip source 7PTC1、RPTC2The resistance value increases with the temperature rise, the characteristic curve is shown in fig. 5, the parallel structure of the power semiconductor chips of the invention is obtained, and fig. 4 is a schematic layout diagram of the component chips in the power semiconductor module with the heat-sensitive component added.
In one embodiment of the invention, the power semiconductor chip is an IGBT, MOSFET or BJT, made of silicon, silicon carbide or gallium nitride, in a number of at least 2, in the form of a bare chip, a single-tube package or a module package.
In one embodiment of the invention, the thermistor is arranged on the surface of the metal electrode of the power semiconductor chip 1 or on a conductive copper layer inside the parallel structure. At normal temperature, the thermistor serves as a driving loop resistor in a normal working state, normal operation is not affected, and the resistance value at the normal temperature is generally small, preferably 0-2 Ω.
The structure was tested and when it was operating normally, no current was passed through the thermistor and the temperature was maintained at T-25 c, when R was present251 Ω. When unbalanced power current is generated between the auxiliary source port 4 and the power source 7Then, the unbalanced power current raises the temperature of the thermistor to T80 ℃, and the resistance value is increased to R75At the moment, the unbalance current on the driving circuit can be reduced by 77%, the heating power of the binding line of the driving circuit is reduced by nearly 95%, and meanwhile, the unbalance current is reduced to reduce the heating power of the thermistor, so that the temperature of the thermistor is reduced to 60 ℃, the resistance value is reduced to 6 omega, and the stable operation is recovered. In conclusion, the resistance value of the thermistor is increased, the size of unbalanced power current is restrained, the heating power of the binding wire is reduced, overcurrent failure of the driving circuit is avoided, and the service life and the operation reliability are improved.
In the description of the present invention, it should be noted that a series of terms describing an orientation, such as "upper", "lower", "left", "right", "inner", "outer", "vertical", "horizontal", etc., are used to indicate an orientation or positional relationship referred to in the drawings.
The foregoing lists merely illustrate specific embodiments of the invention. It is obvious that the invention is not limited to the above embodiments, but that many variations are possible. All modifications which can be derived or suggested by a person skilled in the art from the disclosure of the present invention are to be considered within the scope of the invention.
Claims (8)
1. A power semiconductor chip parallel structure is characterized by comprising a power drain port (2), a power source port (3), an auxiliary source port (4), a grid port (5) and a plurality of power semiconductor chips (1) connected in parallel;
the chip drain electrode (6) in the power semiconductor chip (1) is connected with the power drain electrode port (2), the chip grid electrode (8) in the power semiconductor chip (1) is connected with the grid electrode port (5), the chip source electrode (7) in the power semiconductor chip (1) is respectively connected with the power source electrode port (3) and the auxiliary source electrode port (4), and a thermosensitive element (9) with positive temperature characteristic is arranged between the chip source electrode (7) and the auxiliary source electrode port (4).
2. The power semiconductor chip parallel structure according to claim 1, wherein a connecting device is arranged between the power semiconductor chip (1) and the power drain port (2), the power source port (3) or the gate port (5), and the connecting device is one or more of solder, a binding wire, a substrate copper layer and a copper power terminal.
3. The power semiconductor chip parallel structure according to claim 1, wherein the power semiconductor chip is an IGBT, a MOSFET or a BJT, and the material is silicon, silicon carbide or gallium nitride.
4. The power semiconductor chip parallel structure according to claim 3, wherein the number of the power semiconductor chips is at least 2, and is in the form of one of a bare chip, a single-tube package, or a module package.
5. The power semiconductor chip parallel structure according to claim 1, wherein the thermistor is arranged on a surface of a metal electrode of the power semiconductor chip (1) or on a conductive copper layer inside the parallel structure.
6. The parallel structure of power semiconductor chips as claimed in claim 1 or 5, wherein the thermistor is a thermistor having a resistance value of 0-2 Ω at room temperature.
7. The method for suppressing the overcurrent failure of the driving circuit of the power semiconductor chip parallel structure is characterized in that when the power semiconductor chip parallel structure operates normally, no current flows through the thermistor, the temperature of the thermistor is not affected at room temperature, and the resistance value is kept between 0 and 2 omega, so that the thermistor is used as a driving circuit resistor and does not affect the normal operation;
after the power semiconductor chip parallel structure runs for a long time, if the structure is aged or fails, the power current from the chip source electrode (7) to the power source electrode port (3) is unbalanced, and the current of the chip source electrode keeps unchanged due to the fact that the potential difference between the chip grid electrode (8) and the chip source electrode (7) is unchanged, so that part of the power current is forced to flow to the power source electrode port through the thermistor with the positive temperature characteristic between the chip source electrode (7) and the auxiliary source electrode port (4); when the unbalanced current flows into the driving circuit of the power semiconductor chip parallel structure, the temperature of the thermistor rises, the resistance value becomes large, so that the unbalanced current on the driving circuit is reduced, the heating power of the thermistor is reduced, the temperature and the resistance value are further reduced gradually, and finally, the stable operation is recovered.
8. The method for suppressing the overcurrent failure of the driving circuit of the parallel structure of the power semiconductor chips as recited in claim 7, wherein a parasitic resistance and a parasitic inductance exist between the power semiconductor chip (1) and the power drain port (2), the power source port (3) or the gate port (5);
parasitic resistance and parasitic inductance between the power drain port (2) to the chip drain (6) result from bulk resistance and bulk inductance of the copper power terminal and the substrate copper layer;
parasitic resistance between the grid port (5) and the chip grid (8) is generated by internal resistance of the chip grid and body resistance of the binding line, and parasitic inductance is generated by body inductance of the binding line;
parasitic resistance and parasitic inductance between the power source port (3) and the chip source (7) are generated by the body resistance and the body inductance of the binding line, the substrate copper layer and the copper power terminal.
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Application publication date: 20210601 |