CN105931973A - 半导体装置及其组装方法 - Google Patents

半导体装置及其组装方法 Download PDF

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Publication number
CN105931973A
CN105931973A CN201610104175.6A CN201610104175A CN105931973A CN 105931973 A CN105931973 A CN 105931973A CN 201610104175 A CN201610104175 A CN 201610104175A CN 105931973 A CN105931973 A CN 105931973A
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Prior art keywords
chip
joint sheet
support structure
vertical support
array
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CN201610104175.6A
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CN105931973B (zh
Inventor
T.巴维茨
Y.C.马丁
罗载雄
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International Business Machines Corp
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International Business Machines Corp
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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4228—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements
    • G02B6/4232—Passive alignment, i.e. without a detection of the degree of coupling or the position of the elements using the surface tension of fluid solder to align the elements, e.g. solder bump techniques
    • H—ELECTRICITY
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K1/00—Soldering, e.g. brazing, or unsoldering
    • B23K1/0008—Soldering, e.g. brazing, or unsoldering specially adapted for particular articles or work
    • G—PHYSICS
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    • G02B6/122—Basic optical elements, e.g. light-guiding paths
    • G02B6/1225—Basic optical elements, e.g. light-guiding paths comprising photonic band-gap structures or photonic lattices
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    • G02B6/13—Integrated optical circuits characterised by the manufacturing method
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Abstract

提供了用于微电子、光子和光电装置的倒装芯片组装以及封装的技术，其中，封装组件的三维对准是在回流焊工艺中使用焊料表面张力移动一个或多个封装组件并且使用机械止挡和芯片对接技术在X、Y和Z方向上对准此类组件而实现的。

Description

半导体装置及其组装方法
技术领域
本公开大体涉及微电子、光子和光电装置的组装。
背景技术
通常，用于组装倒装芯片(flip-chip)封装结构的传统技术典型地将通过光刻定义的机械止挡(stop)与回流焊工艺结合使用，以在一维或二维上对准各组件。然而，由于存在于某些制造和组装工艺中的各种各样的公差，这种对准和封装技术可能无法有效地精确地对准封装组件。例如，当将晶片切割为多个类似芯片时，切割出的芯片(裸芯)的尺寸可能存在+/-15μm范围内的差异(variations)。而且，当使用高速取放工具进行倒装芯片组装时，初始芯片(裸芯)放置可能存在+/-10μm范围内的差异。当使用机械止挡和回流焊技术进行对准时，芯片尺寸和放置的这种差异可能造成被组装组件的错位。
发明内容
总的来说，本发明的实施例包括能够在回流焊工艺过程中使用焊料表面张力来移动一个或多个封装组件并且使用芯片对接和机械止挡来获得该组件的多维对准从而实现封装组件的倒装芯片组装的装置和方法。
在本发明的一个实施例中，提供一种用于组装具有第一和第二芯片的半导体装置的方法。所述第一芯片包括由凹陷表面和侧壁表面限定的腔区域，其中所述第一芯片包括形成在所述第一芯片的所述凹陷表面上的第一接合垫阵列，其中焊料设置在第一接合垫上，其中所述第一芯片包括设置在所述第一芯片的所述凹陷表面上的多个垂直支撑结构，并且其中所述第一芯片包括设置在所述侧壁表面上的第一电路组件。所述第二芯片包括形成在所述第二芯片的表面上的第二接合垫阵列和对准止挡，其中所述第二接合垫阵列对应于所述第一接合垫阵列，并且其中所述第二芯片包括设置在所述第二芯片的侧表面上的第二电路组件。所述组装方法包括：将所述第二芯片放置在所述第一芯片的所述腔中的初始位置中且使所述第二接合垫阵列面对所述第一接合垫阵列、使所述第二芯片安置在所述多个垂直支撑结构的顶部上。在所述初始位置中，所述第一接合垫阵列和第二接合垫阵列在水平的X和Y方向上是错位的，并且所述第一电路组件和第二电路组件在垂直的Z方向上是对准的。执行回流焊工艺以使得所述第一接合垫上的焊料接触所述第二芯片的第二接合垫中的对应接合垫并且使得所述第二芯片在X和Y方向上移动的同时沿着所述垂直支撑结构的顶表面滑动，从而使所述第二芯片的第二电路组件与所述第一芯片的第一电路组件在X、Y和Z方向上对准。在X方向上的对准是通过所述对准止挡与至少一个所述垂直支撑结构的接触获得的，并且在Y方向上的对准是通过所述第一芯片的侧壁表面与所述第二芯片的侧表面之间的接触获得的。
在本发明的另一实施例中，所述第一芯片包括光子芯片，而所述第二芯片包括半导体激光芯片。所述第一电路组件包括多个半导体波导结构，所述半导体波导结构具有暴露在所述第一芯片的侧壁表面上的输入，并且其中所述第二电路组件包括半导体激光波导，所述半导体激光波导具有暴露在所述第二芯片的侧表面上的输出。
通过下文中对实施例的详细说明，本发明的这些及其他实施例将得以描述或变得显而易见，并且应将该详细说明与附图结合阅读。
附图说明
图1A、1B和1C示意性地示出了根据本发明实施例的光子芯片，其中图1是光子芯片的俯视示意图，图1B是沿图1A中线1B-1B截取的光子芯片的剖面侧视示意图，并且其中图1C是沿图1A中线1C-1C截取的光子芯片的局部剖面侧视示意图；
图2A和2B示意性地示出了根据本发明实施例的激光芯片，其中图2A是激光芯片的俯视示意图，而图2B是沿图2A中线2B-2B截取的激光芯片的剖面侧视示意图；
图3是示出了形成在图1A中光子芯片上的波导的波导输入接口的透视图；
图4A和4B示意性地示出了根据本发明实施例的激光芯片和光子芯片的倒装芯片组装方法；其中图4A是在回流焊工艺之前、将激光芯片初始放置在光子芯片的凹陷腔内时、包括激光芯片和光子芯片的组装的平面示意图；而图4B是在回流焊工艺之后的组装的平面示意图，其中激光芯片和光子芯片在X、Y和Z方向上自对准；
图5A、5B和5C示意性地示出了根据本发明实施例的激光芯片和光子芯片在Y和Z方向上对准的过程；其中图5A和5B分别是初始放置阶段和焊料熔化/回流阶段中沿图4A所示的线L1-L1截取的剖面侧视示意图；并且其中图5C是沿图4B所示的线L2-L2截取的剖面侧视示意图，其示出了在回流焊阶段结束时光子芯片和激光芯片在Y和Z方向上的对准；
图6A和6B示意性地示出了根据本发明实施例的激光芯片和光子芯片在Y和Z方向上对准的过程；其中图6A是在初始放置阶段中沿图4A所示的线L3-L3截取的局部剖面侧视图；并且其中图6B是沿图4B所示的线L4-L4截取的局部剖面侧视示意图，其示出了在回流焊阶段结束时光子芯片和激光芯片在X和Z方向上的对准。
具体实施方式
现在将关于使用倒装芯片封装技术组装微电子、光子和光电装置而更详细地讨论本发明的实施例，其中，封装组件的三维对准是通过使用回流焊工艺中的焊料表面张力来移动一个或多个封装组件并且使用机械止挡和芯片对接技术使此类组件在X、Y和Z方向上对准而实现的。
虽然本发明的各实施例可在构建倒装芯片组件的各种各样的应用中使用，但出于例示的目的，将在其中使用回流焊工艺中的焊料表面张力来移动激光芯片并且使用芯片对接和机械止挡使激光芯片与光子芯片对准从而对准激光芯片和光子芯片的波导结构来实现三维对准的光学应用下讨论本发明的示范性实施例。
如下文中详细解释的，在回流焊工艺中，熔融焊料的表面张力可使芯片移动多于100μm。我们利用这些运动、通过将运动约束至由光刻定义的机械止挡并且通过芯片表面/边缘对接来获得自对准。例如，在本发明的一实施例中，Y(水平)方向上的对准是通过激光芯片的发射平面与光子芯片的接收波导的接触而获得的。多个垂直支撑结构集成在光子芯片的基板中，从而提供激光芯片和光子芯片在Z(垂直)方向上的支撑和对准。而且，X(水平)方向上的对准是通过在回流焊工艺中、由光刻定义的伸出的机械止挡(其集成在激光芯片的表面上)与基板的其中至少一个垂直支撑结构的接触而获得的。
本发明的示范性实施例可以与标准高速取放工具作用结合实施，随后执行标准回流焊，以进行高精度倒装芯片组装。而且，虽然示范性实施例是参照InP激光倒装芯片组件与Si纳米光子芯片的对准而描述的，但在此描述的技术可应用于需要高对准精度的任意倒装芯片组装。
图1A、1B和1C示意性地例示了根据本发明实施例的光子芯片100(例如，纳米光子芯片)。具体地，图1A是光子芯片100的俯视示意图，图1B是光子芯片100沿图1A所示的线1B-1B截取的剖面侧视示意图，并且图1C是光子芯片100沿图1A所示的线1C-1C截取的局部剖面侧视示意图。图2A和2B示意性地例示了根据本发明实施例的激光芯片200。具体地，图2A是激光芯片200的俯视示意图，图2B是激光芯片200沿图2A所示的线2B-2B截取的剖面侧视示意图。
共同参照图1A、1B和1C，光子芯片100包括基板102(例如，硅基板)，基板102在光子芯片100的刻蚀腔区域104内具有凹陷表面102-1。多个垂直支撑结构106-1、106-2、106-3、106-4和108设置在腔区域104的凹陷表面102-1上。如图1B和1C所示，垂直支撑结构106-1、106-2、106-3、106-4和108形成为具有在基板102的凹陷表面102-1上方的高度H1。在本发明的实施例中，垂直支撑结构106-1、106-2、106-3、106-4和108是在凹陷腔区域104的形成过程中、使用标准光刻和刻蚀技术形成的。
如下文中更详细讨论的，垂直支撑结构106-1、106-2、106-3、106-4和108配置为在组装过程中与激光芯片200的表面接触，并且因此在激光芯片200和光子芯片100的倒装芯片组装过程中充当用于Z方向对准的垂直支撑体(或桩)。而且，如下文中解释的，垂直支撑结构108还在激光芯片200和光子芯片100的倒装芯片组装过程中充当用于X方向对准的机械止挡。
在本发明的一个实施例中，使垂直支撑结构108(其用于X方向对准)(截面接触区域)大于其他垂直支撑结构106-1、106-2、106-3和106-4，以便有效地抵抗在X方向对准过程中施加于垂直支撑结构108的水平力。使其他垂直支撑结构106-1、106-2、106-3和106-4相对较小(截面接触区域)，以在激光芯片200的表面在垂直支撑结构106-1、106-2、106-3和106-4的顶部上沿X和Y水平方向可滑动地移动时使阻力最小化。例如，垂直支撑结构108的截面面积可为50μm x50μm,而其他垂直支撑结构106-1、106-2、106-3和106-4的截面面积可形成为30μm x30μm。
如图1A、1B和1C进一步所示，第一接合垫阵列110形成在基板102的凹陷表面102-1上。第一接合垫阵列110包括多个金属接合垫(比如金属接合垫110-1、110-2、110-3和110-4，其具体标示以用于讨论的目的)。在本发明的一个实施例中，第一接合垫阵列110是通过使用标准UBM(凸点下金属化)技术形成的，其中该金属接合垫可由Ni、Cu或Au或其组合(例如，1μm Ni/0.2μm Cu/0.1μm Au)形成。
光子芯片100还包括形成在凹陷腔区域104外、基板102的上表面上的第一绝缘层112(例如，硅氧化物层)、多个波导120、BEOL(后端工艺(backend of line))结构114和第二绝缘层116(例如，聚酰亚胺层)。如图1A所示，多个波导120包括分离的波导120-1、120-2、120-3、120-4、120-5、120-6、120-7和120-8。在本发明的一个实施例中，波导120-1、120-2、120-3、120-4、120-5、120-6、120-7和120-8是单模硅波导结构。如图1B所示，波导120设置在垂直支撑结构(例如，垂直平衡物106-3)的顶表面上方的垂直高度H3处。
如图1A进一步所示，每个波导120-1、120-2、120-3、120-4、120-5、120-6、120-7和120-8具有位于多个伸出波导部分122中的对应一个的边缘处的波导输入。这些波导部分122是通过沿着凹陷腔104的一个边缘区域、对层112、120和114进行刻蚀/图案化而形成的。该伸出波导部分122提供波导输入接口。
具体地，图3是示出了用于提供光子芯片100的波导120的波导输入接口的多个伸出波导部分122的透视图。在本发明的一实施例中，该伸出波导部分122是通过对第一绝缘层112、硅波导层120和BEOL层114进行RIE(反应离子刻蚀)以形成该伸出波导部分122的图案而形成的，每个与一个对应的波导120的输入对准。该伸出波导部分122形成波导输入接口。而且，如下文解释的，该伸出波导部分122充当用于Y方向对准的机械止挡，其中激光芯片200的劈开边缘(侧表面)在激光芯片200与光子芯片100的倒装芯片组装和对准期间与该伸出波导部分122平接(butted up against)。
如图1B和1C中进一步所示，为了实现激光芯片200与光子芯片100的倒装芯片接合，至少在第一接合垫阵列110中的至少一些或所有金属接合垫(例如，接合垫110-1、110-2、110-3和110-4，如具体所示)上形成焊料130。在本发明的一个实施例中，焊料130采用例如电镀工艺沉积在接合垫110上。在本发明的一个实施例中，焊料130由Sn和Ag形成，例如，Sn-0.6wt％Ag形成。
接下来，如图2A和2B共同所示，激光芯片200包括基板202(例如，硅基板)，硅基板202具有第一侧边缘202-1、第二侧边缘202-2和底表面202-3。通过光刻在基板202的底表面202-3上形成对准止挡208。如下文中进一步详细解释的，对准止挡208充当机械止挡，在激光芯片200和光子芯片100的倒装芯片组装过程中，垂直支撑结构108抵接对准止挡208以进行X方向对准。在本发明的一个实施例中，对准止挡208形成为具有约50μm的宽度和约200μm的长度。
如图2A和2B中进一步所示，第二接合垫阵列210形成在激光芯片200的基板202的底表面202-3上。第二接合垫阵列210包括多个金属接合垫(比如金属接合垫210-1、210-2、210-3和210-4，其具体标示以用于讨论的目的)，其匹配于形成在光子芯片100的基板102的凹陷表面102-1上的第一接合垫阵列110的对应金属接合垫。在本发明的一个实施例中，第二接合垫阵列210通过使用标准UBM技术而形成，其中，该金属接合垫可由Ni、Cu或Au或其组合(例如，1μm Ni/0.2μm Cu/0.1μm Au)形成。
应注意的是，在此使用的术语“接合垫”指的是用于通过焊料130连接将第一芯片(例如，激光芯片200)倒装芯片接合至第二芯片(例如，光子芯片100)的对应接合垫110和210。对应接合垫110/201的焊接对(solderedpair)可以是仅仅充当芯片之间结构化倒装芯片接合的被动结构。此外，对应接合垫110/201的焊接对不仅可用于结构化接合，还可用于芯片之间的电连接(电源、接地、I/O信号等等)。而且，基于应用，芯片的表面上也可存在实际上不用于倒装芯片接合的其他金属接合垫。
如下文进一步详细解释的，倒装芯片组装工艺中的关键参数是沉积在金属接合垫110上的焊料130的量。在本发明的一个实施例中，焊料130形成在金属接合垫(例如，接合垫110-1、110-2、110-3和110-4)上，使得焊料130和相关联的接合垫110的总高度H2小于垂直支撑结构106、108的高度H1。此相对高度差(H1-H2)提供了焊料130顶部与形成在激光芯片200上的金属接合垫210之间的间隙G。如下文解释的，由于在将激光芯片200倒装芯片组装至光子芯片100的回流焊工艺中的焊料表面张力，该间隙对于生成X、Y和Z方向中每一方向上的自对准力是至关重要的。
再次参照图2A和2B，激光芯片200还包括多个激光波导220，例如，激光波导220-1、220-2、220-3、220-4、220-5、220-6、220-7和220-8。激光波导220形成在激光芯片200的基板202内并且从激光芯片200的第一侧边缘202-1延伸至第二侧边缘202-2。激光波导220的光发射端位于激光芯片200的第一侧边缘202-1处，而激光波导220的非发射端位于激光芯片200的第二侧边缘202-2处。在本发明的一个实施例中，激光芯片200包括边发射型激光器，其中激光光线在沿着半导体激光芯片200的波导220的方向上传播，并且被波导220的光发射端处的劈开边缘(例如，第一侧边缘202-1)反射或耦合。
现在将参照图4A、4B、5A、5B、5C、6A和6B进一步详细讨论根据本发明实施例的用于将激光芯片200倒装芯片组装至光子芯片100的示范性方法。图4A是包括激光芯片200和光子芯片100的组装300的示意性平面图，其中，在回流焊工艺之前，激光芯片200初始放置在光子芯片100的凹陷腔104内。图4B是回流焊工艺之后组装300的示意性平面图，其中激光芯片200和光子芯片100在X、Y和Z方向上是自对准的。
而且，图5A、5B和5C示意性地例示了在组装工艺的不同阶段、激光芯片200在Y和Z方向上相对于光子芯片100的位置。具体地，图5A是沿图4A所示的线L1-L1截取的组装300的剖面侧视示意图，其示出了在将激光芯片200初始放置在光子芯片100的凹陷腔104内的初始放置阶段之后、激光芯片200在Y和Z方向上相对于光子芯片100的初始位置。图5B是沿图4A所示的线L1-L1截取的组装300的剖面侧视示意图，其例示了在焊料熔融和回流焊的初始阶段、激光芯片200在Y和Z方向上相对于光子芯片100的位置。图5C是沿图4B所示的线L2-L2截取的、回流焊工艺结束后组装300的剖面侧视示意图，其中光子芯片100和激光芯片200在Y和Z方向上在目标位置处彼此自对准。
而且，图6A和6B示意性地例示了在组装工艺中的不同阶段、激光芯片200在X和Z方向上相对于光子芯片100的位置。具体地，图6A是沿图4A所示的线L3-L3截取的组装300的局部剖面侧视示意图，其例示了在将激光芯片200初始放置在光子芯片100的凹陷腔104内的初始放置阶段之后、激光芯片200在X和Z方向上相对于光子芯片100的初始位置。图6B是沿图4B所示的线L4-L4截取的、在回流焊工艺结束后组件300的局部剖面侧视示意图，其中光子芯片100和激光芯片200在目标位置处在X和Z方向上彼此自对准。
共同参照图4A、5A和6A，根据本发明实施例的倒装芯片组装过程的初始步骤包括将激光芯片200放置在光子芯片100的凹陷腔104内。在本发明的一个实施例中，此步骤通过在晶片切割工艺之后使用用于倒装芯片技术的任意标准取放工具/工艺来执行。大体上，晶片切割涉及将晶片(其包括，例如，多个形成于其上的激光芯片200)安装在环刀上；在晶片的背面铺开晶片带(wafer tape)；将晶片安装在切割盘上；以及使用金刚石刀片将晶片切割为单独的裸芯(例如，单独的激光芯片)。通过晶片切割工艺，晶片被切成单独的裸芯而不会穿透晶片带，使得单独的裸芯在切割工艺之后保持附着至晶片带。在晶片切割之后，取放机(半自动的或全自动的)用于将单独的裸芯(例如，激光芯片200)从晶片带上(经由真空夹头(vacuum collet))提起，并且将裸芯放置到例如基板、封装或其他裸芯堆叠上(例如，将激光芯片200放置在光子芯片100上)。通过自动取放工具、使用图案识别系统自动执行X和Y定位。
如图4A和5A所示，例如，激光芯片200初始放置在光子芯片100的凹陷腔104内，而激光芯片200的第一侧边缘202-1(激光发射边缘)设置为离开伸出波导部分122(波导接口)一距离处，其中该伸出波导部分122包含光子芯片100的波导120的波导输入。此初始距离部分地基于芯片切割(或芯片劈开(cleaving))工艺的公差以及用于将激光芯片200初始定位在光子芯片100上的取放工具的芯片放置公差。
例如，如上所述，芯片切割工艺在切割芯片的尺寸上的公差可为约+/-15μm，并且取放工具可具有+/-10μm的对准精度公差。在这一方面，最坏情况下可能会因切割和对准公差而存在+/-25μm的公差。因此，在本发明的一个实施例中，如图4A和5A示意性所示，对于激光芯片200的初始放置，激光芯片200的接合垫210(例如，接合垫210-3和210-4)可以在距光子芯片100的对应接合垫110(例如，相应接合垫110-3和110-4)的边缘为25μm或更远的距离D1处，而在Y方向上故意错位。
而且，基于放置过程的+/-10μm的对准精度公差，在本发明的一个实施例中，如图4A和6A示意性所示，激光芯片200的接合垫210(例如，接合垫210-1和210-2)可以在距光子芯片100的对应接合垫110(例如，相应接合垫110-1和110-2)的边缘为10μm或更远的距离D2处、在X方向上故意错位。
激光芯片200的接合垫210与光子芯片100的对应接合垫110之间的最大错位量(对于初始放置)可随接合垫110和210在X和Y方向上的节距和/或尺寸而变化。例如，对应接合垫110和210的错位不应过大以防止激光芯片200上的接合垫210被光子芯片100的对应接合垫110上的焊料130焊料润湿，或者允许指定接合垫110上的焊料130润湿激光芯片200上的接合垫210中的对应接合垫210和相邻接合垫。
关于Z方向上的对准，例如，图5A和6A显示了激光芯片200的底表面202-3与垂直支撑结构106-1、106-3和108的顶表面相接触。由此，在拾取和放置过程之后，激光芯片200安置于垂直支撑结构的顶部。这种垂直定位是有可能的，因为每一焊料130/接合垫110结构的总高度H2小于垂直支撑结构106-1、106-3和108的高度H1，从而提供焊料130与激光芯片200底表面202-3上对应接合垫210之间的间隙G。
在图5A所示的垂直定位中，激光芯片200的激光波导220与光子芯片100的波导120对准(在垂直Z方向上)。这是因为激光波导220和激光芯片200的底表面202-3之间的距离H3等于从垂直支撑结构106-1、106-3和108的顶部到光子芯片100的波导120之间的垂直高度H3。
在拾取和放置过程结束之后，开始回流焊工艺。如图5B所描绘的，在回流焊工艺的初始阶段，当平坦的电镀焊料130开始熔融时，该平坦的电镀焊料130变为球形，这使得焊料130与激光芯片200的底表面202-3上的接合垫中的对应接合垫(例如，焊盘210-3、210-4)相接触。
一旦熔融的焊料130接触激光芯片200的接合垫210，该熔融的焊料130就开始润湿焊盘210并且遍布到接合垫210上。在回流过程中，激光芯片200的接合垫210上的熔融焊料130的表面张力有效地导致激光芯片200在X和Y方向上的运动，从而最小化熔融焊料130的表面能量。具体地，如图5C所示，激光芯片200在Y方向上移动，直至激光芯片200的第一侧边缘202-1紧靠光子芯片100的伸出波导部分122。而且，如图6B所示，激光芯片200在X方向上移动，直至激光芯片200的底表面202-3上的对准止挡208紧靠垂直支撑结构108。
一旦激光芯片200的第一侧边缘202-1紧靠伸出波导部分122(图5C)并且对准止挡208紧靠垂直支撑结构108(图6B)，激光芯片200就将在X和Y两个方向上均与光子芯片100对准。在这种XY对准的状态下，如图4B所描绘的，激光芯片200的激光波导220-1、220-2、220-3、220-4、220-5、220-6、220-7和220-8的输出对准并且接触光子芯片100的伸出波导部分122中的对应波导120-1、120-2、120-3、120-4、120-5、120-6、120-7和120-8的输入。
如图4B、5C和6B所示，在激光芯片200和光子芯片100的回流焊和对准之后，保持光子芯片100的接合垫110与激光芯片200的对应接合垫210在X和Y两个方向上的一些错位。所产生的在对应接合垫110和210之间、X和Y两个方向上的错位确保了激光芯片200将继续在X和Y方向上运动直至激光芯片200的第一侧边缘202-1与伸出波导部分122相接触(Y方向对准)并且使对准止挡208紧靠垂直支撑结构108(X方向对准)。实际上，基于拉伸表面张力，如果对应接合垫110和210的边缘在X或Y方向上对准，则在X或Y任一方向上的运动将实质上在X或Y方向上停止。因此，通过防止对应接合垫110和120的边缘的对准，确保了激光芯片200在X和Y方向上继续运动，直至通过上述接触机制机械地停止。
关于Z方向上的对准，在回流焊过程中，激光芯片200的接合垫210上的熔融焊料130的表面张力有效地维持激光芯片200的底表面202-3可滑动地与垂直支撑结构106-1、106-2、106-3、106-4和108的顶表面相接触，同时使激光芯片200在X和Y方向上水平地移动并且在垂直支撑结构106-1、106-2、106-3、106-4和108的顶部上滑动。因此，在从放置到回流焊和最终自对准的整个组装过程中有效地维持Z对准。例如，如图5C和6B所示，在回流焊之后，激光芯片200的激光波导220-1、220-2、220-3、220-4、220-5、220-6、220-7和220-8与对应波导102-1、120-2、120-3、120-4、120-5、120-6、120-7和120-8垂直对准。
回流焊过程中激光芯片200在X和Y方向上的运动以及XY对准结果可取决于激光芯片200的底表面202-3与垂直支撑结构106-1、106-2、106-3、106-4和108的顶表面之间的摩擦力。因此，为了最小化回流焊过程中激光芯片200的底表面202-3与垂直支撑结构106-1、106-2、106-3、106-4和108的顶表面之间的摩擦力，可在某些制造步骤，例如，用于形成凹陷腔104和垂直支撑结构的深反应离子深刻蚀(deep RIE)工艺以及包括种子层沉积和刻蚀步骤的焊料电镀工艺之后，利用已知的半导体制造技术来清洁垂直支撑结构106-1、106-2、106-3、106-4和108的表面。
在本发明的一个实施例中，在回流焊工艺过程中使用诸如甲酸的气相助焊剂(vapor phase flux)，其与液型助焊剂(liquid type flux)相反。诸如甲酸的气相助焊剂的使用使得能够移除回流焊工艺过程中的锡氧化物，并且消除可能会随着液型助焊剂而生成的助焊剂残留的形成。助焊剂残留会增加回流焊工艺过程中激光芯片200的底表面202-3与垂直支撑结构106-1、106-2、106-3、106-4和108的顶表面之间的摩擦，并且阻碍激光芯片200的运动，由此阻碍适当的XY对准。
而且，对于光学应用，使用液型助焊剂而生成的助焊剂残留和排出气体无法与良好的光学特性相兼容。通过使用诸如甲酸的气相助焊剂，不会生成助焊剂残留，并且不需要清洁助焊剂残留。因此，在回流焊之后，可执行组装工艺的下一阶段，例如，在对准的激光芯片200和光子芯片100之间分配光学填充材料，而无需执行助焊剂残留清洁过程。
如下文进一步详细解释的，倒装芯片组装工艺中的关键参数是沉积在金属接合垫110上的焊料130的量以及焊料130与激光芯片200的底表面202-3上的金属接合垫210之间的间隙G(参见图5A、6A)。与1D(仅Y方向)和2D(YZ方向)的自对准相比，根据本发明一实施例的3D(XYZ方向)自对准工艺具有更窄的工艺窗口并且必须考虑各种各样的参数。通过实验和计算，我们已确定焊料的水平和垂直表面张力为接合垫110和220之间的焊料量的函数。如上所示，电镀焊料130/接合垫100结构的总高度H2应小于垂直支撑结构的高度H1，以使得当焊料130熔融并且润湿激光芯片200的接合垫210时、熔融焊料的表面张力将在激光芯片200上施加X、Y和Z方向上的拉力。
通过实验和计算，我们已发现间隙G(其与焊料130的量有关)的尺寸对于产生正确量的水平和垂直力以使得芯片能够随着在垂直支撑结构上的滑动而在X和Y方向上有效地进行可滑动的移动以及保持芯片抵靠该垂直支撑结构的顶表面是至关重要的。对于大的间隙G尺寸(或小量的焊料)，水平力(X和Y方向上)减小至0，而对于小的间隙G尺寸(或大量的焊料)，垂直力(Z方向上)减小至0。基于这些计算结果和模型，我们已确定理想的间隙G的尺寸是垂直支撑结构的高度H1的函数：0.15×H1＜G＜0.25×H1。例如，在图5A所示的实施例中，假设垂直支撑结构(例如，垂直支撑结构106-3)的高度H1是10μm，那么理想的间隙G将在约1.50μm至约2.50μm的范围内。该理想的间隙G将足以提供能够在H1＝10μm的情况下实现X、Y和Z方向上的适当对准的期望的水平和垂直力。
通过实验，我们已确定，在此描述的根据本发明实施例的XYZ对准方法有利地提供了在X、Y和Z方向上小于1μm的对准精度。示范性的倒装芯片组装对准方法考虑到了例如激光芯片200的芯片的分割或切割公差，其中，芯片的关键边缘之间的对准(例如，波导对准)是使用例如芯片对接(butting)实现的。对于光学应用，在此讨论的对准方法能够实现激光芯片与Si纳米光子芯片之间的精确对准，与单模光学器件相适应，而不管由标准高速取放工具提供的低的对准精度(+/-10μm)。
虽然已在此参照随附附图出于例示的目的描述了各实施例，但应理解的是，本发明不限于那些具体的实施例，并且本领域技术人员在不脱离本发明范围的前提下可受此影响想到各种各样的其他变化和修改。

Claims (20)

1.一种用于组装半导体装置的方法，包括：
提供第一芯片，所述第一芯片包括由凹陷表面和侧壁表面限定的腔区域，其中所述第一芯片包括形成在所述第一芯片的凹陷表面上的第一接合垫阵列，其中焊料设置在所述第一接合垫上，其中所述第一芯片包括设置在所述第一芯片的凹陷表面上的多个垂直支撑结构，并且其中所述第一芯片包括设置在所述侧壁表面上的第一电路组件；
提供第二芯片，其中所述第二芯片包括形成在所述第二芯片的表面上的第二接合垫阵列和对准止挡，其中所述第二接合垫阵列对应于所述第一接合垫阵列，并且其中所述第二芯片包括设置在所述第二芯片的侧表面上的第二电路组件；
将所述第二芯片放置到所述第一芯片的所述腔中的初始位置且使所述第二接合垫阵列面对所述第一接合垫阵列、使所述第二芯片支撑在所述多个垂直支撑结构的顶部上，其中在所述初始位置中，所述第一接合垫阵列和第二接合垫阵列在水平的X方向和Y方向上错位，并且所述第一组件和第二组件在垂直的Z方向上对准；
执行回流焊工艺以使得所述第一接合垫上的焊料接触所述第二芯片的第二接合垫中的对应接合垫，并且使得所述第二芯片在X方向和Y方向上移动的同时沿着所述垂直支撑结构的顶表面滑动，从而使所述第二芯片的第二电路组件与所述第一芯片的第一电路组件在X、Y和Z方向上对准，
其中，在X方向上的对准是通过所述对准止挡与至少一个所述垂直支撑结构之间的接触获得的，并且其中在Y方向上的对准是通过所述第一芯片的侧壁表面与所述第二芯片的侧表面之间的接触获得的。
2.如权利要求1所述的方法，其中，所述第一芯片包括光子芯片，而所述第二芯片包括半导体激光芯片。
3.如权利要求1所述的方法，其中，所述第一电路组件包括具有暴露在所述第一芯片的侧壁表面上的输入的多个半导体波导结构，并且其中所述第二电路组件包括具有暴露在所述第二芯片的侧表面上的输出的半导体波导。
4.如权利要求1所述的方法，其中，在所述初始位置中，在所述焊料和所述第二芯片的第二接合垫之间存在间隙，其中，所述间隙的尺寸G的范围为：0.15×H1＜G＜0.25×H1，其中，H1是所述垂直支撑结构的高度。
5.如权利要求1所述的方法，其中，所述回流焊工艺是使用气相助焊剂执行的。
6.如权利要求1所述的方法，其中，在所述第一电路组件和第二电路组件在所述X、Y和Z方向上对准时，所述第一接合垫和所述第二接合垫中对应接合垫之间在所述X方向和所述Y方向中的至少一个方向上留有错位。
7.如权利要求1所述的方法，其中，与所述对准止挡接触的所述至少一个垂直支撑结构的截面积大于不与所述对准止挡接触的其他垂直支撑结构的截面积。
8.如权利要求1所述的方法，其中，所述第一电路组件设置在形成于所述第一芯片的侧壁表面上的伸出部分中。
9.如权利要求1所述的方法，其中，在所述初始位置中，所述第一接合垫阵列和第二接合垫阵列在水平的X方向和Y方向上的错位量大于约10μm。
10.如权利要求1所述的方法，其中，在回流焊工艺过程中，所述第一电路组件和第二电路组件之间在Z方向上的对准是通过保持所述第二芯片的表面与所述垂直支撑结构的顶表面相接触而维持的。
11.一种使用以下方法制造的半导体装置：
提供第一芯片，所述第一芯片包括由凹陷表面和侧壁表面限定的腔区域，其中所述第一芯片包括形成在所述第一芯片的凹陷表面上的第一接合垫阵列，其中焊料设置在所述第一接合垫上，其中所述第一芯片包括设置在所述第一芯片的凹陷表面上的多个垂直支撑结构，并且其中所述第一芯片包括设置在所述侧壁表面上的第一电路组件；
提供第二芯片，其中所述第二芯片包括形成在所述第二芯片的表面上的第二接合垫阵列和对准止挡，其中所述第二接合垫阵列对应于所述第一接合垫阵列，并且其中所述第二芯片包括设置在所述第二芯片的侧表面上的第二电路组件；
将所述第二芯片放置到所述第一芯片的所述腔中的初始位置且使所述第二接合垫阵列面对所述第一接合垫阵列、使所述第二芯片支撑在所述多个垂直支撑结构的顶部上，其中在所述初始位置中，所述第一接合垫阵列和第二接合垫阵列在水平的X方向和Y方向上错位，并且所述第一组件和第二组件在垂直的Z方向上对准；
执行回流焊工艺以使得所述第一接合垫上的焊料接触所述第二芯片的第二接合垫中的对应接合垫，并且使得所述第二芯片在X方向和Y方向上移动的同时沿着所述垂直支撑结构的顶表面滑动，从而使所述第二芯片的第二电路组件与所述第一芯片的第一电路组件在X、Y和Z方向上对准，
其中，在X方向上的对准是通过所述对准止挡与至少一个所述垂直支撑结构之间的接触获得的，并且其中在Y方向上的对准是通过所述第一芯片的侧壁表面与所述第二芯片的侧表面之间的接触获得的。
12.如权利要求11所述的半导体装置，其中，所述第一芯片包括光子芯片，而所述第二芯片包括半导体激光芯片。
13.如权利要求11所述的半导体装置，其中，所述第一电路组件包括具有暴露在所述第一芯片的侧壁表面上的输入的多个半导体波导结构，并且其中，所述第二电路组件包括具有暴露在所述第二芯片的侧表面上的输出的半导体波导。
14.如权利要求11所述的半导体装置，其中，在所述初始位置中，在所述焊料和所述第二芯片的第二接合垫之间存在间隙，其中，所述间隙的尺寸G的范围为：0.15×H1＜G＜0.25×H1，其中，H1是所述垂直支撑结构的高度。
15.如权利要求11所述的半导体装置，其中，所述回流焊工艺是使用气相助焊剂执行的。
16.如权利要求11所述的半导体装置，其中，在所述第一电路组件和第二电路组件在所述X、Y和Z方向上对准时，第一接合垫和第二接合垫中对应接合垫之间在所述X方向和Y方向中的至少一个方向上保持错位。
17.如权利要求11所述的半导体装置，其中，与所述对准止挡接触的所述至少一个垂直支撑结构的截面积大于不与所述对准止挡接触的其他垂直支撑结构的截面积。
18.如权利要求11所述的半导体装置，其中，所述第一电路组件设置在形成于所述第一芯片的侧壁表面上的伸出部分中。
19.如权利要求11所述的半导体装置，其中，在所述初始位置中，所述第一接合垫阵列和第二接合垫阵列在所述水平的X方向和Y方向上的错位量大于约10μm。
20.如权利要求11所述的半导体装置，其中，在回流焊工艺过程中，所述第一电路组件和第二电路组件之间在所述Z方向上的对准是通过保持所述第二芯片的表面与所述垂直支撑结构的顶表面相接触而维持的。
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Publication number Priority date Publication date Assignee Title
US20160291269A1 (en) * 2015-04-01 2016-10-06 Coriant Advanced Technology, LLC Photonic integrated circuit chip packaging
WO2016202357A1 (en) * 2015-06-15 2016-12-22 Rwth Aachen Self-alignment for apparatus comprising photonic device
US9466590B1 (en) * 2015-11-13 2016-10-11 International Business Machines Corporation Optimized solder pads for microelectronic components
US10176833B1 (en) 2016-01-22 2019-01-08 Seagate Technology Llc Horizontal cavity surface emitting laser integration features for heat assisted magnetic recording
JP6933794B2 (ja) * 2016-12-01 2021-09-08 富士通株式会社 光モジュール及び光モジュールの製造方法
US20180190614A1 (en) * 2016-12-05 2018-07-05 Ananda H. Kumar Massively parallel transfer of microLED devices
US10490971B2 (en) 2017-06-09 2019-11-26 International Business Machines Corporation Self-alignment features for III-V ridge process and angled facet die
US10156688B1 (en) * 2017-08-17 2018-12-18 Avago Technologies International Sales Pte. Limited Passive alignment system and an optical communications module that incorporates the passive alignment system
US10393962B2 (en) * 2017-11-30 2019-08-27 International Business Machines Corporation Optimized stand-offs and mechanical stops for precise three dimensional self-alignment
JP2019186467A (ja) 2018-04-16 2019-10-24 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US10302859B1 (en) 2018-06-22 2019-05-28 International Business Machines Corporation Single edge coupling of chips with integrated waveguides
US11166381B2 (en) 2018-09-25 2021-11-02 International Business Machines Corporation Solder-pinning metal pads for electronic components
KR102541564B1 (ko) 2018-10-04 2023-06-08 삼성전자주식회사 반도체 패키지
WO2020181097A1 (en) 2019-03-06 2020-09-10 Lightmatter, Inc. Photonic communication platform
US10895702B2 (en) * 2019-04-01 2021-01-19 Google Llc Integrated heater structures in a photonic integrated circuit for solder attachment applications
US11710672B2 (en) * 2019-07-08 2023-07-25 Intel Corporation Microelectronic package with underfilled sealant
US11557878B2 (en) * 2019-10-22 2023-01-17 University Of Maryland, College Park High power, narrow linewidth semiconductor laser system and method of fabrication
EP4100773A4 (en) 2020-02-03 2024-03-20 Lightmatter, Inc. PHOTONIC UNIT COMMUNICATION SYSTEMS AND ASSOCIATED PACKAGING
US11651973B2 (en) 2020-05-08 2023-05-16 International Business Machines Corporation Method and apparatus of processor wafer bonding for wafer-scale integrated supercomputer
WO2021247994A1 (en) * 2020-06-05 2021-12-09 Siphox, Inc. Systems and methods for photonic chip coupling
US11462497B2 (en) * 2020-10-14 2022-10-04 Western Digital Technologies, Inc. Semiconductor device including coupled bond pads having differing numbers of pad legs
US20230092060A1 (en) * 2021-09-20 2023-03-23 Intel Corporation Optical circuit with optical port in sidewall
CN118202286A (zh) 2021-10-13 2024-06-14 光物质公司 多光罩光子通信平台上的多租户隔离
DE102022121857A1 (de) 2022-08-30 2024-02-29 Ams-Osram International Gmbh Kantenemittierende halbleiterlaserdiode; verfahren zur herstellung eines halbleiterlaserbauelements und halbleiterlaserbauelement

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110085760A1 (en) * 2009-10-13 2011-04-14 Electronics And Telecommunications Research Institute Optical devices and methods of fabricating the same
CN102163589A (zh) * 2010-02-17 2011-08-24 美士美积体产品公司 具有自组装式弹性引线的晶片级封装装置
US20110267930A1 (en) * 2010-04-30 2011-11-03 Seagate Technology Llc Method and Apparatus for Aligning a Laser Diode on a Slider
CN103500716A (zh) * 2013-10-08 2014-01-08 华进半导体封装先导技术研发中心有限公司 一种芯片键合对准方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5077878A (en) 1990-07-11 1992-01-07 Gte Laboratories Incorporated Method and device for passive alignment of diode lasers and optical fibers
US5745631A (en) 1996-01-26 1998-04-28 Irvine Sensors Corporation Self-aligning optical beam system
EP1122567A1 (en) 2000-02-02 2001-08-08 Corning Incorporated Passive alignement using slanted wall pedestal
TW449797B (en) 2000-09-22 2001-08-11 Ind Tech Res Inst Integrated surface-emitting type electro-optical module and the fabrication method thereof
US6793407B2 (en) 2002-09-25 2004-09-21 International Business Machines Corporation Manufacturable optical connection assemblies
FR2919757A1 (fr) 2007-07-31 2009-02-06 Intexys Sa Technique d'assemblage de sous-ensemble optoelectronique
US8035221B2 (en) * 2007-11-08 2011-10-11 Intersil Americas, Inc. Clip mount for integrated circuit leadframes
DE102010048003B4 (de) 2010-05-05 2016-01-14 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zur Herstellung von mechanischen Anschlägen zur Selbstjustage und Vorrichtung mit Anschlägen zur Selbstjustage
EP2795674B1 (en) 2011-12-22 2021-12-15 Heptagon Micro Optics Pte. Ltd. Opto-electronic modules, in particular flash modules, and method for manufacturing the same
US9227257B2 (en) * 2012-04-24 2016-01-05 Seagate Technology Llc Laser subassembly metallization for heat assisted magnetic recording

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110085760A1 (en) * 2009-10-13 2011-04-14 Electronics And Telecommunications Research Institute Optical devices and methods of fabricating the same
CN102163589A (zh) * 2010-02-17 2011-08-24 美士美积体产品公司 具有自组装式弹性引线的晶片级封装装置
US20110267930A1 (en) * 2010-04-30 2011-11-03 Seagate Technology Llc Method and Apparatus for Aligning a Laser Diode on a Slider
CN103500716A (zh) * 2013-10-08 2014-01-08 华进半导体封装先导技术研发中心有限公司 一种芯片键合对准方法

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110071209A (zh) * 2018-01-22 2019-07-30 罗姆股份有限公司 Led封装
CN110071209B (zh) * 2018-01-22 2022-11-29 罗姆股份有限公司 Led封装
CN112703596A (zh) * 2018-09-19 2021-04-23 脸谱科技有限责任公司 显示器制造中的发光结构对准保持
CN110571159A (zh) * 2019-08-01 2019-12-13 广东芯华微电子技术有限公司 一种提高大规模芯片组定位精度的即时自补偿方法
CN113555449A (zh) * 2020-04-03 2021-10-26 华为技术有限公司 半导体器件及其制备方法和通信设备
CN113555449B (zh) * 2020-04-03 2024-03-15 华为技术有限公司 半导体器件及其制备方法和通信设备

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