TW463284B - Flip chip semiconductor packaging method with three-dimensional automatically precise alignment - Google Patents

Abstract

A flip chip semiconductor packaging method with three-dimensional automatically precise alignment is provided, which includes the following steps: first, forming a plurality of first sets of bumps on a substrate; next, forming a plurality of second sets of bumps on the substrate, wherein the melting point of the first set of bumps is higher than the melting point of the second set of bumps, and the height of the first set of bumps on the substrate is lower than the height of the second set of bumps on the substrate; using the first set of bumps to define a plane in the Z-axis direction; using flip chip to bond a chip with the substrate; melting the second set of bumps with low melting point to pull back the alignment force to achieve the alignment of the chip and the substrate on the XY plane. Also, in the melting and breaking process of the second set of bumps, the plane in the Z-axis direction defined by the first set of bumps with high melting point can still maintain the original designed height in which the height is the assembly height for the chip with the substrate.

Description

4 6 328 4 V. Description of the invention (1) 5 ~ 1 Field of the invention: The present invention relates to a method for connecting semiconductor structures, and in particular to an improved method for flip-chip bonding (f 1 i p c h i p) connection. 5-2 Background of the Invention: The flip-chip bonding (f 1 ip ch ip) technology was developed by the American I BM company in about 1960, the purpose is to replace the slower wireb ο nding, reduce costs and Improve component connection reliability. Wire bonding is a peripheral type bonding, while flip chip bonding is a parallel type (a r e a a r r a y) bonding, so it is more suitable for high-density construction wiring applications. The flip-chip bonding technology is an emerging important milestone technology for integrated circuit construction. The first step of flip-chip bonding is to grow a solder bump on the chip of the integrated circuit. Solder (solder) is grown on the integrated circuit pad (pad), and reflow is used to form a spherical solder bump. The solder bumps can also be prepared by solder immersion (s ο 1 d e r d i p) or electroless plating with ultrasonic spot welding. After the solder bumps are formed, the flip-chip bonding machine is used to accurately position and bond the substrates. The first figure is a schematic diagram of the traditional flip-chip bonding method. The traditional flip-chip bonding uses only a single size of a single bump 3, and the process of assembly and bonding

4 6328 4 V. Description of the invention (2) The pull-back force generated during the melting and solidification of the bumps automatically and accurately aligns the wafer 1 and the substrate 2 on the two-dimensional plane in the X-axis and Y-axis directions. The height of the Z-axis wafer after assembly and bonding is determined by the collapse height of the bump after melting and solidification. Because the current process of growing bumps on wafers is almost impossible to grow bumps that meet the requirements of accurate alignment, the height error is soil 2 / i, making the collapse height of the bumps after melting and solidification unable to meet the requirements of accurate alignment. Therefore, traditional flip-chip bonding can only achieve automatic and accurate alignment on a two-dimensional plane in the X-axis and Y-axis directions. The second figure is a schematic diagram of a semiconductor laser device bonded by a conventional flip-chip bonding method. The uneven height of the bumps 4 makes it difficult for the assembled GaAs wafer 5 to reach the design height and flatness of the wafer. The laser rod (1 aser bar) 6 cannot be accurately aligned with the transmission fiber 7, which makes the laser light transmission efficiency not meet the specifications. In addition, if the semiconductor laser device bonded by the conventional flip-chip bonding method and the silicon substrate etching positioning bump method (as shown in the third figure), if the bump 8 is improperly designed, the friction force will be too large, which will affect the bump X, The strength of the Y-axis straightening, and the process of etching and positioning the bumps on the silicon substrate is complicated and the cost is too high, which does not meet the needs of low-cost flip-chip semiconductor laser device construction. 5-3 Invention Purpose and Overview:

46328 4 a — _ five _, description of the invention (3) As the above background of the invention, ^

There are still many shortcomings in the connection * type of the body structure = the improvement of the flip-chip bonding method to improve the bonding of the crystal bonding. 'The present invention has produced the inventor .: J The main purpose of the present invention is to provide a flip-chip = Bonding semiconductor assembly method, which is: automatically aligning bumps of different heights and different melting points in the J direction, so that two bumps growing on the wafer can be bonded together to complete the x-axis; the die is on, process t: by and Directional automatic alignment. Another aspect of the present invention provides a three-chip flip-chip bonding semiconductor fabrication method, which automatically and accurately aligns two sets of bumps of different heights and different melting points in a quasi-direction, and a semiconductor element grown on a single wafer. Making. In process 1 to low-cost flip-chip bonding, high-precision, low-throughput active alignment coating:; :: No ,,: = text Additional process that requires etching to locate bumps. The present invention provides a flip-chip bonding semiconductor assembly method for automatic and accurate alignment in three-dimensional directions, which at least includes: providing a substrate for flip-chip bonding to form a plurality of A first group of bumps are formed on the substrate, and then a plurality of second groups of bumps are formed on the substrate having the first group of bumps. A wafer is bonded to the substrate, and the wafer and the substrate are re-soldered. The second group of bumps; wherein the melting point of the first group of bumps is higher than the melting point of the second group of bumps, and the height of the first group of bumps on this substrate is smaller than the height of the second group of bumps on this substrate. Low-melting second set of bumps are melt-solidified

Page 7 463284 V. Description of the invention (4) The pull-back force is generated during the process, which makes the 4 pairs of positions on the two-dimensional plane in the X-drawing and Y-axis directions automatically quasi-aligned, and at the same time during the melting and solidification of the second group of bumps with a low melting point, Since the first group of bumps with a high melting point does not melt, the Z-axis height defined by the first group of bumps with a high melting point is the assembly height of the wafer and the substrate. With this, with a combination of two sets of bumps of different heights and different melting points on a single wafer, a flip-chip bonded semiconductor structure can be automatically and accurately aligned in three dimensions. The purpose and many advantages of the present invention will become apparent from the following detailed description of the preferred embodiments and with reference to the accompanying drawings. Detailed description of the preferred embodiments 5-4: The fourth figure is an exploded view of the preferred embodiment of the present invention. First, a plurality of first ball bumps of a height DB are formed on a silicon substrate 9. (solder bump), the number of the first group of solder ball bumps 1 is at least three, and then a plurality of second group of solder ball bumps 1 1 of height DA are formed on the substrate 9. The melting point of the first group of solder ball bumps 10 is higher than the melting point of the second group solder ball bumps 1 1, and as shown in FIG. 5A, the height DB of the first group solder ball bumps 10 is smaller than that of the second group. The height DA of the solder ball bump 1 1 1. The arrangement of the solder ball bumps on the silicon substrate 9 depends on the design, which is not the focus of the present invention. The embodiments of the present invention are applicable to solder ball bumps of any arrangement. The arrangement of the solder ball bumps 10 and 11 shown in the fourth figure is only an example for the simple schematic description of this embodiment. And base

463284 V. Description of the invention (5) The material of the plate 9 can also be used, such as polyimide, triazabenzene, pentylphenol and BT substrate. Any suitable material can be used as the substrate of the present invention. The first group of bumps 10 and the second group of bumps 11 can also be designed as bumps of other shapes, such as L-shaped or T-shaped. Next, a wafer 1 2 is bonded, such as a laser semiconductor element.

GaAs chip, with this silicon substrate 9. The second set of solder ball bumps 1 1 of the wafer 12 and the silicon substrate 9 are re-soldered. The lower-melting second group of solder ball bumps 1 1 generates a pull-back force during the melting and solidification process, so that the X-axis and Y-axis directions are automatically and accurately aligned on a two-dimensional plane. As shown in FIG. 5B, it is a relationship diagram between the height DAm of the second group of solder bumps 11 after melting and solidification and the height DB of the first group of solder bumps 10. During the melt-down process of the second group of solder ball bumps 1 with a lower melting point, the first group of solder ball bumps 1 with a higher melting point do not melt, and the first group of solder ball bumps with a higher melting point 1 The plane in the Z-axis direction defined by 〇 can still maintain the original design height DB, and this height becomes the assembly height of the chip 12 and the silicon substrate 9. In this way, a flip-chip bonded semiconductor structure is automatically and accurately aligned in three dimensions with a combination of two sets of bumps of different heights and different melting points on a single wafer. According to the above-mentioned construction process of the present invention, the present invention does not need to use a high-priced, high-precision, low-capacity active alignment flip-chip bonding machine in terms of process equipment, and does not need to etch additional processes of positioning bumps on the silicon substrate. Through the combination of bumps with different melting points and different heights, the production of low-cost flip-chip semiconductor devices can be achieved.

463284 V. Description of the invention (6) In another embodiment of the present invention, two sets of bumps of different heights and different melting points can also be grown on a single wafer, and then the wafer and a substrate are connected by flip-chip bonding. The above are only specific embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all other equivalent changes or modifications made without departing from the spirit disclosed by the present invention should be included in the following Within the scope of patent application.

Page 10 463284 Brief description of the diagram The first diagram is an exploded schematic diagram of bonding a wafer and a substrate by a conventional flip-chip bonding method; the second diagram is a schematic diagram of a semiconductor laser element bonded by a conventional flip-chip bonding method; the third The figure is a schematic cross-sectional view of a conventional silicon substrate etching positioning bump structure. The fourth figure is an exploded schematic diagram of a flip-chip semiconductor device bonded by a flip-chip bonding method in a preferred embodiment of the present invention, in which the substrate for flip-chip bonding is used. Two groups of bumps with different melting points and different heights are formed on the top; FIG. 5A is a schematic diagram of the relationship between the height of the low melting point bump group and the high melting point bump group before the low melting point bump group in FIG. 4 is melted and solidified; Figure 5B is a schematic diagram of the relationship between the height of the low-melting bump group and the high-melting bump group after the low-melting bump group in Figure 4 is melt-solidified.

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Claims (1)

46328 4 VI. Application Patent Scope 1. A flip-chip bonding semiconductor assembly method with automatic and accurate alignment in three dimensions, which at least includes: providing a substrate for flip-chip bonding; forming a plurality of first sets of bumps on the substrate Forming a plurality of second sets of bumps on the substrate having the first set of bumps; bonding a wafer to the substrate; and resoldering the crystal moon and the second set of bumps of the substrate; wherein The melting point of the first group of bumps is higher than the melting point of the second group of bumps, and the height of the first group of bumps on the substrate is smaller than the height of the second group of bumps on the substrate. 2. For the method of claim 1 in the patent scope, in which any one of the above and below sides of the wafer can be bonded to the substrate. 3. The method according to item 1 of the patent application range, wherein the first set of bumps mentioned above includes at least three bumps. 4. The method according to item 1 of the scope of patent application, wherein the first group of bumps and the second group of bumps mentioned above both include solder ball bumps. 5. The method according to item 1 of the patent application range, wherein the first set of bumps and the second set of bumps mentioned above both include L-shaped bumps. Page 13 4 6328 4 6. Scope of Patent Application 6 · As for the method of applying for item 1 of the patent scope, wherein the first group of bumps and the second group of bumps mentioned above both include T-shaped bumps. 7. The method according to item 1 of the scope of patent application, wherein the above substrate is a silicon substrate. 8. A flip-chip bonded semiconductor fabrication method for automatic and accurate alignment in three dimensions, comprising at least: providing a substrate for flip-chip bonding; forming a plurality of first sets of bumps on a wafer; forming a plurality of first Two sets of bumps are on the wafer having the first set of bumps; the wafer is bonded to the substrate; and the second set of bumps and the substrate of the wafer are re-soldered; The melting point is higher than the melting point of the second group of bumps, and the height of the first group of bumps on the substrate is less than the south of the second group of bumps on the substrate. 9. The method of claim 8 in the scope of patent application, wherein the first set of bumps and the second set of bumps are formed on either side of the front and back of the wafer at the same time. 10. The method according to item 8 of the scope of patent application, wherein the above-mentioned first set of bumps includes at least three bumps. Page 14 463284 VI. Application scope of patents 1 1 _If the method of the eighth scope of patent application is applied, the first group of bumps and the second group of bumps mentioned above both include solder ball bumps. 1 2. The method according to item 8 of the scope of patent application, wherein the first set of bumps and the second set of bumps both include L-shaped bumps. 1 3. The method according to item 8 of the scope of patent application, wherein the first set of bumps and the second set of bumps both include T-shaped bumps. 1 4. The method according to item 8 of the scope of patent application, wherein the above-mentioned substrate is a silicon substrate. Page 15