CN105914157A - Chip package technology and chip package structure - Google Patents
Chip package technology and chip package structure Download PDFInfo
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- CN105914157A CN105914157A CN201610292703.5A CN201610292703A CN105914157A CN 105914157 A CN105914157 A CN 105914157A CN 201610292703 A CN201610292703 A CN 201610292703A CN 105914157 A CN105914157 A CN 105914157A
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- 238000000034 method Methods 0.000 claims description 92
- 238000004806 packaging method and process Methods 0.000 claims description 14
- 230000003287 optical effect Effects 0.000 claims description 12
- 239000004020 conductor Substances 0.000 claims description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 239000010949 copper Substances 0.000 claims description 7
- 239000005022 packaging material Substances 0.000 claims description 6
- 238000005520 cutting process Methods 0.000 claims description 3
- 238000004070 electrodeposition Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 claims description 2
- 239000004744 fabric Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 230000010354 integration Effects 0.000 abstract 1
- 238000005538 encapsulation Methods 0.000 description 13
- 238000002372 labelling Methods 0.000 description 3
- 230000004807 localization Effects 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000004615 ingredient Substances 0.000 description 2
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000008707 rearrangement Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000000712 assembly Effects 0.000 description 1
- 238000000429 assembly Methods 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000011900 installation process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
- H01L2924/1815—Shape
- H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
- H01L2924/18162—Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
The present invention provides a chip package technology and a chip package structure. After a chip is packaged to a package carrier, the position information of an electrode pad on the chip is obtained, the cover body of the chip is covered, and the position information of the electrode pad is obtained; and the cover body is subjected to opening processing to bare the electrode terminal of the chip, and finally the electrode terminal is electrically connected with an external circuit. The package technology is simple, and the package structure formed by the technology is low in manufacturing cost and high in reliability and integration level.
Description
Technical field
The present invention relates to chip encapsulation technology field, particularly relate to a kind of chip package process and chip-packaging structure.
Background technology
Manufacture integrated circuit time, chip generally with other electronic assemblies integrated before packed.Applying wide chip package process in early days is wire bond package technique, i.e. by the electrode terminal on chip is bonded on lead frame by metal lead wire, and the then packaged type of plastic packaging.But the area of the encapsulating structure formed by wire bond package technique is relatively big, and encapsulation performance receives metal lead wire resistance and the impact of parasitic capacitance and can not effectively improve.Therefore, flip-chip packaged technique is arisen at the historic moment subsequently, and the flip-chip packaged structure formed by flip-chip packaged technique is little due to package dimension, and encapsulation performance is high and receives much concern.
Fig. 1 is the flip-chip packaged structural representation formed by flip-chip packaged technique, chip 02 is electrically connected on lead frame 01 by the conductive projection 021 being positioned on its active face, and plastic packaging material 03 covers chip 02 and exposes the bottom of lead frame 01 using as the pin electrically connected with external circuit.The flip-chip packaged processing step forming this flip-chip packaged structure includes the stickup of chip, back-off and plastic packaging.As shown in Figure 2, many chip blocks 02 are pasted the pre-position on package carrier 00, conductive projection 021 is set in the electrical terminal of the active face of each of which chip block 02, then, by on the chip back-off on package carrier 00 to the lead frame 01 set as shown in Figure 3, so that conductive projection 021 electrical connection corresponding with the pad on lead frame 01, finally carry out plastic packaging and form plastic-sealed body 03.But, as shown in Figure 2, segment chip 02 can not paste the pre-position (at dotted line) on base plate for packaging 00 the most accurately, when during this stickup, inevitable deviation can make chip 02 back-off to lead frame 01, as shown in Figure 4, conductive projection 021 can not be corresponding with on lead frame pad electrical connection, consequently, it is possible to cause the short circuit of encapsulating structure or the phenomenon of open circuit, have impact on the reliability of encapsulation.
In addition, in above-mentioned flip-chip packaged technique, owing to carrying out plastic packaging again after chip 02 is electrically connected to lead frame 01, therefore, when the size of conductive projection 021 is less, plastic packaging material is difficult to be filled in the gap between chip 02 and lead frame 01, needs the underfill process using technology difficulty big, thus adds technology difficulty and manufacturing cost.And; owing to needing to use conductive projection to realize electrically connecting between chip 02 with lead frame 01; have yet with the conductive projection being positioned at chip 02 active face and have the dimensions (the typically larger than size of pad); when the electrode terminal quantity on face, chip active face gets more and more; spacing between pad and the pad of these electrode terminals also can be more and more less, thus cannot make soldered ball on pad or conductive projection realizes the electrical connection with external circuit.
Summary of the invention
In view of this, the invention provides a kind of chip package process and chip-packaging structure, the cost with Simplified flowsheet complexity, reducing encapsulation, the reliability improving chip package and the integrated level of increasing encapsulation chip.
A kind of chip package process, it is characterised in that including:
At least chip piece is mounted on package carrier in active supine mode, the active face of described chip is provided with electrode pad；
Obtain the position data of described electrode pad, and store described position data；
Cover on the chip with insulant, to form nappe；
According to described position data, described nappe is carried out opening process, to remove the described insulant above described electrode pad.
Preferably, described package carrier being provided with telltale mark, described telltale mark is exposed by described nappe.
Described position data characterizes the most described specifically labelled relative position of described electrode pad.
Preferably, described chip package process also includes, after described nappe is carried out opening process, at least forms one layer and reroute layer, with the electrode position of chip described in rearrangement on described nappe.
Preferably, described chip package process also includes, the surface rerouting layer in top forms weld layer, and described chip passes through described weld layer and is connected externally to.
Preferably, described chip package process also includes, after forming described weld layer, removes described package carrier, and cuts described nappe along presetting Cutting Road, to form at least one chip-packaging structure being coated with by described insulant.
Preferably, described chip package process, the method positioned by optical scanning obtains described position data.
Preferably, described chip package process, the method positioned by optical scanning is obtained the step of described position data and includes:
Make the color on the profile of all described chips or shape highlight, then obtain the contour images of described chip, finally described contour images is carried out image procossing to obtain described position data；
Or, make the color on all described electrode pad central points or shape highlight, then obtain the scattergram picture that the central point of all described electrode pads is constituted, finally described scattergram picture is carried out image procossing to obtain described position data.
Preferably, described chip package process also includes, by described chip attachment before described package carrier, on described electrode pad formed electric conductor,
After described nappe is carried out opening process, described electric conductor is exposed by described nappe.
Preferably, described chip package process, described electric conductor is copper ball, and described copper ball contacts with described electrode pad and electrically connects.
Preferably, described chip package process also includes, by described chip attachment before described package carrier, described package carrier is formed telltale mark described at least two, for determining a coordinate axes,
The most described specifically labelled relative position of described electrode pad is described electrode pad position in described coordinate axes.
Preferably, described chip package process, described telltale mark is hole, location or the pad for filled circles.
Preferably, described chip package process, the step that described nappe carries out opening process includes:
According to described position data and described telltale mark, orient the position at described electrode pad place,
Described in described electrode pad position utilize laser beam that described nappe is carried out opening process, to remove the described insulant on described electrode pad.
Preferably, described chip package process, described insulant is plastic packaging material, utilizes plastic package process to form described nappe.
A kind of according to the chip-packaging structure manufactured by the chip package process described in above-mentioned any one.
In the chip package process that the present invention provides, due to after chip attachment, the position data of the electrode pad in acquisition storage chip, comes positioning chip pad position according to obtained position data subsequently and nappe is carried out opening process, to realize the extraction of chip electrode.Therefore, in the chip package process that the present invention provides, the reliability of encapsulation will not be impacted by deviation during pasting chip, thus has higher package reliability.
Additionally, in the chip package process that the present invention provides, before the electrode drawing chip, be initially formed the nappe for protecting chip, the electrode of chip is drawn and external electrical connections by being positioned on body rewiring layer.Therefore, the chip package process that the present invention provides, without for underfill process, technique is simple and low cost, and due to without using conductive projection to electrically connect with lead frame, therefore the chip package process that the present invention provides adapts to the chip package of the electrode terminal of ultra dense spacing, is conducive to improving the integrated level of encapsulation chip.
Accompanying drawing explanation
By description to the embodiment of the present invention referring to the drawings, above-mentioned and other objects, features and advantages of the present invention will be apparent from, in the accompanying drawings:
Fig. 1 is a kind of flip-chip packaged structural representation；
Fig. 2 is the structural representation that chip affixes on package carrier；
Fig. 3 is the structural representation of lead frame；
Fig. 4 is chip back-off to the structural representation on lead frame；
Fig. 5 a～5e is the generalized section forming structure according to each processing step in the chip package process of the embodiment of the present invention.
Detailed description of the invention
It is more fully described the present invention hereinafter with reference to accompanying drawing.In various figures, identical ingredient uses similar reference to represent.For the sake of clarity, the various piece in accompanying drawing is not necessarily to scale.Furthermore, it is possible to not shown part known to some.For brevity, the structure that can obtain after several steps described in the width figure.Describe hereinafter the many specific details of the present invention, the structure of the most each ingredient, material, size, process technique and technology, in order to be more clearly understood that the present invention.But the most as the skilled person will understand, the present invention can not be realized according to these specific details.
Fig. 5 a～5e is the schematic diagram forming structure according to each processing step in the chip package process of the embodiment of the present invention.It is specifically described the chip package process that the present invention provides below in conjunction with Fig. 5 a～5e.In order to enable preferably to show the structure formed in each processing step, Fig. 5 a and Fig. 5 b is the top view forming structure in corresponding processing step, and Fig. 5 c, 5d and 5e are the part sectioned view forming structure in corresponding processing step.
The chip package process provided according to the embodiment of the present invention comprises the following steps:
Step 1: as shown in Figure 5 a, it forms the top view of structure for chip attachment process, is mounted on package carrier 11 in active supine mode by least chip piece 21, and the active face of chip is provided with electrode pad 211, additionally, be also provided with telltale mark 111 on package carrier 11.
Before chip 21 is mounted on package carrier 11, generally also need on package carrier 11, forming telltale mark 111 described at least two, for determining a coordinate axes.Such as telltale mark 111 in the present embodiment has four, lays respectively on four angles of package carrier 11.In this application, the relative position of electrode pad 211 relative localization labelling 111 refers to the electrode pad 211 position in the coordinate axes determined by telltale mark 111.Wherein, telltale mark 111 can be hole, location, it is also possible to for the pad of filled circles.
Step 2: obtain the position data of electrode pad relative localization labelling 111, and store described position data.
Described position data is the coordinate parameters in the coordinate axes that electrode pad 211 is described in step 1, which characterizes the relative position of electrode pad 211 relative localization labelling 111.In the present embodiment, the method positioned by optical scanning obtains described position data.Concrete, the method that positioned by optical scanning is obtained the step of described position data and includes:
Step 21a: make the color at the profile of all chips 21 or shape highlight.Such as, package carrier 11 after pasting chip 21 is placed on the optical scanning district in the equipment of optical scanning location, by the light-illuminating of optical scanning device, make light at the profile of chip 21 illuminate to or high, so that color or shape on the profile of chip 21 highlight than other region of contrast.
Step 22a: after the color on the profile of chip 21 highlights, obtains the contour images of chip 21.For example, it is possible to by taking pictures or obtaining described contour images by the way of optical scanning.
Step 23a: the contour images obtained is carried out image procossing, to obtain described position data.
In other embodiments, the method positioned by optical scanning obtains the step of described position data can also be for following steps:
Step 21b: make the color on all described electrode pad 211 central points or shape highlight.The method making the color on described electrode pad central point or shape highlight can be identical with step 21a.
Step 22b: after the color of electrode pad 211 central point highlights, obtains the scattergram picture that the central point of electrode pad 211 is constituted.For example, it is possible to by taking pictures or obtaining described scattergram picture by the way of optical scanning.
Step 23b: center dot image is carried out image procossing, to obtain described position data.
Step 3: as shown in Figure 5 b, covers on chip 21 with insulant, to form nappe 31, and makes the exposed telltale mark of nappe 31 111.Fig. 5 c is the cross-sectional view of an encapsulation unit structure in Fig. 5 b, and partial encapsulation carrier 11 that each described encapsulation unit described by a chip 21, is positioned under this chip 21 and the nappe 31 covering this chip 21 are constituted.
Can be plastic packaging material, such as epoxy-plastic packaging material for forming the insulant of nappe 31, nappe 31 can be formed by plastic package process.Additionally, as shown in Figure 5 c, chip 21 and package carrier 11 are directly additionally provided with adhesive linkage 213.Therefore, in step 1, chip 21 is pasted onto the pre-position on package carrier 11 by adhesive linkage 213.
Step 4: as fig 5d, according to the position data stored in step 2 and telltale mark 111 (for illustrating in Fig. 5 d), carries out opening process to nappe 31, to remove the insulant for being constituted nappe above electrode pad 211.
Owing to needing that nappe 31 is carried out opening process in step 4, during preventing opening, the electrode pad 211 being damaged on chip 21, thus damage the device in chip 21, as shown in Fig. 5 a～5e, the chip package process step that the present invention provides can further include: before chip 21 is mounted on package carrier 11, forms electric conductor 212 on the electrode pad 211 of chip 21, described electric conductor after step 3, is also coated to lid 31 and covers.Electric conductor 212 can be copper ball, and copper ball 212 is formed directly on electrode pad 211, i.e. contacts with electrode pad 211 and electrically connects.Owing to there being the protection of copper ball 212, even if nappe 31 is carried out opening, even if the somewhat deep point that opening depth ratio is presetting, also electrode pad 211 will not be caused damage.
In step 4, the concrete steps that nappe carries out opening include:
Step 41: according to the position data stored in step 2 and described telltale mark, orient the position at described electrode pad place.
Step 42: described in the electrode pad oriented position utilize laser beam that described nappe 31 is carried out opening process, to remove the described insulant on described electrode pad.
When nappe 31 being carried out opening and processing, in order to enable to guarantee to realize electrically connecting between chip with rewiring layer, must must ensure to remove all insulant on electrode pad 211, because of so that after opening, it is exposed that electric conductor 212 on electrode pad 211 is coated to lid 31, electrically connects for the rewiring layer being subsequently formed.
Step 5: as depicted in fig. 5e, at least forms one layer on nappe 31 and reroutes layer, such as, reroute layer 41, with the electrode position of rearrangement chip 21.
Step 6: the surface rerouting layer of the top rerouted in layer formed in step 5 forms weld layer (unmarked in Fig. 5 e), chip 21 passes through described weld layer and is connected externally to.Outside can refer to other device or circuit galley etc..
Step 7: after completing step 6, removes package carrier 11, and cuts described nappe 51 along presetting Cutting Road, thus form at least one chip-packaging structure by the cladding of insulant described in step 3, as depicted in fig. 5e.
Additionally, present invention also offers the chip-packaging structure that a kind of chip package process according to embodiments of the present invention is formed, this structure can be as depicted in fig. 5e.
In the chip package process that the present invention provides, due to after chip 21 mounts, the position data of the electrode pad 211 in acquisition storage chip, come positioning chip pad 211 position according to obtained position data subsequently and nappe 31 is carried out opening process, to realize the extraction of chip electrode.Therefore, in the chip package process that the present invention provides, the reliability of encapsulation will not be impacted by deviation during pasting chip 21.Such as, as shown in Figure 5 a, when the second chip block 21 of the first row and the 3rd chip block 21 of the second row are in attachment to package carrier 11, all deviate from predetermined mounting position, then the electrode pad 211 on chip 21 has also offset from position set in advance.But, the position data of the electrode pad 211 owing to obtaining in step 2 obtains after chip 21 mounts, therefore, when in step 4 nappe 31 is carried out opening process, can the position of electrode pad 211 at location accurately according to described position data and specifically labelled position, such that it is able to by exposed for the electrode terminal of chip 21 outside nappe 31, and then by rerouting layer and external electrical connections.As can be seen here, the chip-packaging structure that the chip package process using the present invention to provide is formed does not haves the phenomenon of short circuit or open circuit, thus has higher package reliability.
In addition; in the chip package process that the present invention provides; before the electrode drawing chip 21; it is initially formed the nappe 31 for protecting chip; the electrode of chip 21 is drawn and external electrical connections by being positioned on body 21 rewiring layer 41, and needs to be drawn out on lead frame by the electrode of chip by conductive projection unlike existing reverse installation process.Therefore, the chip package process that the present invention provides, without for underfill process, technique is simple and low cost, and due to without using conductive projection to electrically connect with lead frame, therefore the chip package process that the present invention provides adapts to the chip package of the electrode terminal of ultra dense spacing, is conducive to improving the integrated level of encapsulation chip.
Therefore, in the chip package process of present invention offer and structure, after chip attachment to package carrier, the first positional information of the electrode pad on acquisition chip, it is then covered by the nappe of chip, recycles the positional information of obtained electrode pad, nappe is carried out opening process, to expose the electrode terminal of chip, finally electrode terminal is drawn and electrically connect with external circuit.The most described packaging technology is simple, and the encapsulating structure low cost of manufacture formed by described technique, reliability and integrated level are the highest.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe, are not intended to the specific embodiment that this invention is only described yet.Obviously, as described above, can make many modifications and variations.These embodiments are chosen and specifically described to this specification, is to preferably explain the principle of the present invention and actual application, so that skilled artisan can utilize the present invention and amendment on the basis of the present invention to use well.The present invention is only limited by claims and four corner thereof and equivalent.
Claims (14)
1. a chip package process, it is characterised in that including:
At least chip piece is mounted on package carrier in active supine mode, described chip active
Electrode pad it is provided with on face；
Obtain the position data of described electrode pad, and store described position data；
Cover on the chip with insulant, to form nappe；
According to described position data, described nappe is carried out opening process, to remove on described electrode pad
The described insulant of side.
Chip package process the most according to claim 1, it is characterised in that set on described package carrier
Being equipped with telltale mark, described telltale mark is exposed by described nappe.
Described position data characterizes the most described specifically labelled relative position of described electrode pad.
Chip package process the most according to claim 2, it is characterised in that also include, to described
After nappe carries out opening process, on described nappe, at least form one layer reroute layer, again to arrange
The electrode position of chip described in cloth.
Chip package process the most according to claim 3, it is characterised in that also include, in top
The surface rerouting layer forms weld layer, and described chip passes through described weld layer and is connected externally to.
Chip package process the most according to claim 4, it is characterised in that also include, described being formed
After weld layer, remove described package carrier, and cut described nappe along presetting Cutting Road, with
Form at least one chip-packaging structure being coated with by described insulant.
Chip package process the most according to claim 1, it is characterised in that positioned by optical scanning
Method obtain described position data.
Chip package process the most according to claim 6, it is characterised in that positioned by optical scanning
Method obtain described position data step include:
Make the color on the profile of all described chips or shape highlight, then obtain the profile diagram of described chip
Picture, finally carries out image procossing to obtain described position data to described contour images；
Or, make the color on all described electrode pad central points or shape highlight, then obtain all institutes
State the scattergram picture that the central point of electrode pad is constituted, finally described scattergram picture is carried out image procossing
To obtain described position data.
Chip package process the most according to claim 1, it is characterised in that also include, by described
Chip attachment, before described package carrier, forms electric conductor on described electrode pad,
After described nappe is carried out opening process, described electric conductor is exposed by described nappe.
Chip package process the most according to claim 7, it is characterised in that described electric conductor is copper ball,
Described copper ball contacts with described electrode pad and electrically connects.
Chip package process the most according to claim 2, it is characterised in that also include, by institute
Stated chip attachment before described package carrier, described package carrier is formed location mark described at least two
Note, for determining a coordinate axes,
The most described specifically labelled relative position of described electrode pad is that described electrode pad is at described coordinate axes
In position.
11. chip package process according to claim 10, it is characterised in that described telltale mark is
Hole, location or be the pad of filled circles.
12. chip package process according to claim 2, it is characterised in that described nappe is entered
The step that row opening processes includes:
According to described position data and described telltale mark, orient the position at described electrode pad place,
Utilize laser beam that described nappe is carried out opening process in the position at described electrode pad place, with
Remove the described insulant on described electrode pad.
13. chip package process according to claim 1, it is characterised in that described insulant is
Plastic packaging material, utilizes plastic package process to form described nappe.
14. 1 kinds according to the core manufactured by the chip package process described in any one in claim 1 to 13
Chip package.
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| CN201610292703.5A CN105914157A (en) | 2016-04-28 | 2016-04-28 | Chip package technology and chip package structure |
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| CN201610292703.5A CN105914157A (en) | 2016-04-28 | 2016-04-28 | Chip package technology and chip package structure |
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Application publication date: 20160831 |