CN105895538A - Manufacture method for chip packaging structure and chip packaging structure - Google Patents
Manufacture method for chip packaging structure and chip packaging structure Download PDFInfo
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- CN105895538A CN105895538A CN201610292652.6A CN201610292652A CN105895538A CN 105895538 A CN105895538 A CN 105895538A CN 201610292652 A CN201610292652 A CN 201610292652A CN 105895538 A CN105895538 A CN 105895538A
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- rewiring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/811—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector the bump connector being supplied to the parts to be connected in the bonding apparatus
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention provides a manufacture method for a chip packaging structure and the chip packaging structure. The method comprises the steps that a first re-distribution layer is formed on a packaging carrier; N second re-distribution layers are then formed on the first re-distribution layer; a chip is electrically to the topmost second re-distribution layer; and finally, the packaging carrier is removed, and the first re-distribution layer is exposed on the surface of the chip packaging structure and can be used as an external pin for electric connection between the chip packaging structure and external equipment. The manufacture method is characterized in that the re-distribution layers are configured at first and then the chip is installed, so that scrapping of the chip does not happen even if errors appear during configuration of the re-distribution layers; and a yield rate of chip packaging is effectively increased, and cost for the chip packaging is effectively reduced.
Description
Technical field
The present invention relates to chip encapsulation technology field, particularly relate to a kind of chip-packaging structure manufacture method and
Chip-packaging structure.
Background technology
Along with the integrated level of integrated circuit improves, the electrode pad on semiconductor bare chip gets more and more, electrode
Spacing between pad is more and more less, in order to enable preferably to be drawn out to by the electrode on semiconductor bare chip envelope
The surface of assembling structure and external electrical connections, would generally be that quasiconductor is naked during encapsulation semiconductor bare chip
Chip configuring multi-layer reroute layer, with after the electrode of rearrangement semiconductor bare chip again with external electrical connections.
The existing packaging technology step for semiconductor bare chip configuration rewiring layer is: first by semiconductor bare chip
Sheet is arranged on chip bearing device, the active face of semiconductor bare chip upward, the most again in semiconductor bare chip
The configuration of the active face last layer layer of sheet reroutes layer.It is naked that this packaging technology first installs quasiconductor due to needs
Chip, then on the active face of semiconductor bare chip, configuration reroutes layer, if reroute the workshop section of layer in configuration
In occur in that mistake, it is possible to making bulk semiconductor bare chip scrap, process costs is high.
Summary of the invention
In view of this, the invention provides manufacture method and the chip-packaging structure of a kind of chip-packaging structure,
To improve the yield of chip package, reduce packaging cost.
The manufacture method of a kind of chip-packaging structure, it is characterised in that including:
Package carrier is formed the first rewiring layer of patterning,
Reroute described first and form the second rewiring layer of N shell patterning on layer, adjacent layer described
Second reroutes layer is electrically connected to each other, and described the second of the bottom reroutes layer and reroute layer with described first
Electrical connection,
Chip is electrically connected to described the second of top and reroutes on layer,
Remove described package carrier so that described first reroutes the exposed table at described chip-packaging structure of layer
Face, using the outer pin as described chip-packaging structure Yu external electrical connections.
Preferably, form the second step rerouting the 1st layer of second rewiring layer in layer described in N shell to include:
Cover described first with insulant and reroute layer, form the 1st layer of cover layer,
Described 1st layer of cover layer is carried out opening process, to expose described first rewiring layer,
Form the 1st layer on described 1st layer of cover layer described second reroutes layer so that the institute of the 1st layer
State the second rewiring layer to extend to that the opening of described 1st layer of cover layer reroutes layer with described first and electrically connect.
Preferably, i is more than 1, is formed and reroutes the described second rewiring layer of i-th layer in layer described in N shell
Step includes:
Cover with insulant and reroute on layer at described the i-th-1 layer second, form i-th layer of cover layer,
Described i-th layer of cover layer is carried out opening process, to expose described the i-th-1 layer described second rewiring
Layer,
Form i-th layer on described i-th layer of cover layer described second reroutes layer so that i-th layer described
Second reroutes layer extends to reroute layer electricity with described the i-th-1 layer second in the opening of described i-th layer of cover layer
Connect.
Preferably, the step described i-th layer of cover layer being carried out opening process includes:
Position according to described the i-th-1 layer second rewiring layer obtained before forming described i-th layer of cover layer
Data, position the position at described the i-th-1 layer second rewiring layer place,
Utilize laser beam to described i-th layer of cover layer in described the i-th-1 layer second position rerouting layer place
Carry out opening process, reroute layer with exposed described the i-th-1 layer second.
Preferably, form the second step rerouting the 1st layer of second rewiring layer in layer described in N shell to include:
Reroute described first and form the 1st layer of wiring projection,
Cover described first with insulant and reroute layer, to form the 1st layer of cover layer, described 1st layer of cloth
Line projection is exposed by described 1st layer of cover layer,
Described 1st layer of cover layer is formed the 1st pattern layers electrically connected with described 1st layer of wiring projection
Conductive layer,
Described 1st layer of wiring projection constitutes described 1st layer with described 1st pattern layers conductive layer and reroutes layer.
Preferably, i is more than 1, is formed and reroutes the described second rewiring layer of i-th layer in layer described in N shell
Step includes:
Reroute at described i-1 layer second and on layer, form i-th layer of wiring projection,
Cover described the i-th-1 layer second with insulant and reroute layer, to form i-th layer of cover layer, described the
I layer wiring projection is exposed by described i-th layer of cover layer,
Described i-th layer of cover layer is formed the i-th pattern layers electrically connected with described i-th layer of wiring projection lead
Electric layer,
Described i-th layer of wiring projection constitutes described i-th layer with described i-th pattern layers conductive layer and reroutes layer.
Preferably, described first reroutes layer is formed by multiple pin arrangements, in described 1st layer of wiring projection
Multiple 1st wiring projections lay respectively on multiple described pin, and each described pin is in the horizontal direction
Area of section more than be positioned at thereon described 1st wiring projection area of section in the horizontal direction.
Preferably, described i-th pattern layers conductive layer is rerouted district's arrangement by multiple i-th and forms, and described i-th
Multiple i-th wiring projections in floor wiring projection lay respectively at multiple i-th and reroute in district, and described in each
I-th reroutes district's area of section in described horizontal direction more than being positioned at described 1st wiring projection thereon at water
Square to area of section.
Preferably, described manufacture method also includes: form the first encapsulated member encapsulating described chip.
Preferably, described manufacture method also includes:
Described first encapsulated member is carried out opening process, reroutes layer with described the second of exposed part top,
Described first encapsulated member forms triple wiring layers so that described triple wiring layers extend to institute
State in the opening of the first encapsulated member with top described second reroute layer electrically connect,
Electronic component is electrically connected on triple wiring layers,
Form the second encapsulated member encapsulating described electronic component.
Preferably, the step step being electrically connected to by chip on described second wiring layer of top includes:
Described second wiring layer of top is formed interconnection bumps,
Weld layer is formed on described interconnection bumps surface；
By the active face of chip towards described weld layer, and electrically connected with described weld layer by electric conductor, institute
State electric conductor to be positioned on the pad of described active face.
Preferably, described manufacture method also includes: described chip is being passed through electric conductor and described weld layer
Before electrical connection, on described pad, form described electric conductor by salient point routing technique.
Preferably, described package carrier includes bearing substrate and the metal level being positioned on described bearing substrate,
Described metal level, as Seed Layer, utilizes electroplating technology to form described first weight cloth on described metal level
Line layer.
A kind of chip-packaging structure formed according to the manufacture method described in above-mentioned any one.
Therefore, in the manufacture method of the chip-packaging structure that the present invention provides, first shape on package carrier
Become the first rewiring layer, reroute formation N shell second on layer described first the most again and reroute layer, then
Chip being electrically connected to top second and reroutes on layer, remove described package carrier the most again, make is described
First reroutes the exposed surface at described chip-packaging structure of layer, using as described chip-packaging structure with outer
The outer pin of portion's electrical connection.Owing to described manufacture method first configures rewiring layer, then chip, even if
Configuration occurs in that mistake during rerouting layer, also will not cause scrapping of chip, effectively raise core
The yield of sheet encapsulation and the cost of reduction chip package.
Accompanying drawing explanation
By description to the embodiment of the present invention referring to the drawings, above-mentioned and other purposes of the present invention,
Feature and advantage will be apparent from, in the accompanying drawings:
Fig. 1 a to Fig. 1 h is that in the chip packaging method according to the embodiment of the present invention one, each processing step is formed
The generalized section of structure；
Fig. 2 a to Fig. 2 b is that in the chip packaging method according to the embodiment of the present invention two, some processes step is formed
The generalized section of structure；
Fig. 3 a to Fig. 3 g is that in the chip packaging method according to the embodiment of the present invention three, each processing step forms structure
Generalized section.
Detailed description of the invention
It is more fully described the present invention hereinafter with reference to accompanying drawing.In various figures, identical ingredient
Similar reference is used to represent.For the sake of clarity, the various piece in accompanying drawing is not drawn to paint
System.Furthermore, it is possible to not shown part known to some.For brevity, can be described in the width figure
The structure obtained after several steps.Additionally, in this application, all of chip refers both to semiconductor bare chip
Sheet.Describe hereinafter the many specific details of the present invention, the structure of the most each ingredient, material
Material, size, process technique and technology, in order to be more clearly understood that the present invention.But the technology as this area
Personnel it will be appreciated that as, the present invention can not be realized according to these specific details.
Embodiment one
Fig. 1 a to Fig. 1 h be the chip-packaging structure according to the embodiment of the present invention one manufacture method in each work
Skill step forms the generalized section of structure.It is specifically described the present invention below in conjunction with Fig. 1 a to Fig. 1 h to provide
Chip packaging method and chip-packaging structure.
The manufacture method of the chip package that embodiment one provides mainly comprises the steps that
Step 1: form the first rewiring layer of patterning on package carrier.
As shown in Figure 1a, package carrier 1 primarily serves the effect of mechanical support during chip package,
In the present embodiment, package carrier 1 includes bearing substrate 11 and the metal level 12 being positioned on bearing substrate.
In the present embodiment, as shown in Figure 1 b, using metal level 12 as Seed Layer, electroplating technology is utilized to exist
The first rewiring layer 12 of patterning is formed on metal level 2.Electroplating technology is utilized to be formed on package carrier 1
First reroutes concretely comprising the following steps of layer 2: first arrange the electroplating mask plate of patterning, institute on metal level 12
State electroplating mask plate and expose partial metal layers 12, then electroplating metal material on exposed metal level 12,
To form the first rewiring layer 2 of patterning on metal level 12.Metal level 12 and the first rewiring layer 2 exist
The present embodiment is layers of copper.First reroutes layer 2 has relative first surface and second surface, such as figure
Shown in 1b, the first first surface rerouting layer 2 contacts with metal level 12, and follow-up encapsulation step will be
Carry out on first second surface rerouting layer 2.
Step 2: reroute described first and form the second rewiring layer that N shell patterns on layer is adjacent
Described the second of layer reroutes layer and is electrically connected to each other, and described the second of the bottom reroutes layer and described first
Rewiring layer electrically connects.
Described N is more than or equal to 1, and when N is more than 1, the second connected rewiring layer is electrically connected to each other,
Electrode position for the follow-up packed chip of rearrangement.N is equal to 1 in the present embodiment, such as figure
Shown in 1e, the 1st layer (i.e. the bottom) second reroutes layer 3 and is formed on the first rewiring layer 2, and
Reroute layer 2 with first to electrically connect.
Formed the 1st layer second reroute layer 3 concrete steps as shown in Fig. 1 c to Fig. 1 e, key step is as follows:
First, as illustrated in figure 1 c, cover at the first rewiring layer with insulant (such as epoxy-plastic packaging material)
On 2, to form the 1st layer of cover layer 4.Concrete, plastic package process can be used to form the 1st layer of cover layer 4.
Then, as shown in Figure 1 d, the 1st layer of cover layer 4 is carried out opening process, to expose the first weight cloth
Line layer 2.
Finally, as shown in fig. le, the 1st layer of cover layer is formed the second rewiring layer 3 of the 1st layer, makes
The second rewiring layer 3 of the 1st layer extends to reroute layer 2 with first in the opening of the 1st layer of cover layer 4
Electrical connection.
In other embodiments, described N is more than or equal to 2, then form N shell second and reroute the in layer
1 layer of method rerouting layer can be identical with the present embodiment, is formed in addition to the 1st layer second reroutes layer
The step of i-th layer of rewiring layer (i.e. i be more than 1) as follows:
First, with insulant (such as epoxy-plastic packaging material) cover as described in the i-th-1 layer second reroute on layer,
Form i-th layer of cover layer, concrete, plastic package process can be used to form i-th layer of cover layer.
Then, i-th layer of cover layer is carried out opening process, to expose the i-th-1 layer second rewiring layer,
I-th layer of cover layer forms the second rewiring layer of i-th layer so that the second rewiring layer of i-th layer
Extend to that the opening of i-th layer of cover layer reroutes layer with the i-th-1 layer second electrically connect.
Wherein, present invention also offers the concrete steps that described i-th layer of cover layer is carried out opening process, this step
Suddenly specifically include that
First, layer is rerouted according to described the i-th-1 layer second obtained before forming described i-th layer of cover layer
Position data, position described the i-th-1 layer second reroute layer place position.Such as can be swept by optics
The mode retouching location obtains described position data.
Then, utilize laser beam to described i-th layer in described the i-th-1 layer second position rerouting layer place
Cover layer carries out opening process, reroutes layer with exposed described the i-th-1 layer second.
Same, in the present embodiment, the 1st layer of cover layer is carried out the step of process of opening the most such as
Shown on opening procedure, such as: formed before the 1st layer of cover layer 4, obtain the first rewiring layer 2
Position data, and store, after forming the 1st layer of cover layer 4, further according to the positional number of described storage
According to orienting the position at the first rewiring layer 2 place, finally reroute layer 2 position first and open
Mouth processes, to expose the first rewiring layer 2.
Step 3: chip is electrically connected to described the second of top and reroutes on layer.
As shown in Figure 1 f, due in the present embodiment, second reroutes layer only has one layer, therefore in step 3
Described the second of top reroutes layer namely the 1st layer of second rewiring layer 3.Chip is electrically connected to the 1st
Concretely comprising the following steps on layer the second rewiring layer 3:
First on the 1st layer of second wiring layer 3, form interconnection bumps 51.Electroplating technology such as can be utilized to exist
Forming multiple interconnection bumps 51 on 1st layer of second wiring layer 3, interconnection bumps 51 is copper billet.
Then, weld layer 52 is formed on interconnection bumps 51 surface, such as tin layers.
Finally, by the active face of chip 5 towards weld layer 52, and by electric conductor 53 and weld layer electricity 52
Connecting, electric conductor 53 is positioned in the pad (not shown) of described active face.Concrete, chip 5 is being led to
Cross before electric conductor 53 electrically connects with weld layer 52, formed on described pad by salient point routing technique and lead
Electricity body 53.
The concrete steps utilizing salient point routing technique to form electric conductor 53 include: first with capillary (salient point routing
Technique apparatus) form soldered ball, then described soldered ball is implanted on the pad of chip 5, then on pinch off soldered ball
Metal wire, thus on the pad of chip 5, define electric conductor 53.In the present embodiment, electric conductor
53 is copper ball.
Step 4: remove described package carrier so that described first reroutes that layer is exposed ties at described chip package
The surface of structure, using the outer pin as described chip-packaging structure Yu external electrical connections.
As shown in fig. le, remove the package carrier 1 as mechanical support effect, so that first reroutes layer
The exposed surface at chip-packaging structure as shown in fig. le of first surface of 2, using as described chip package
The outer pin of structure, is used for providing external connection.
Additionally, damage, in the present embodiment, in step 3 to reduce chip 5 to be affected by extraneous factor
And between step 4, it is also with plastic package process and forms the first encapsulated member 6 of encapsulating chip 5, such as Fig. 1 g institute
Show.
Embodiment two
Some processes step in enforcement two example of the manufacture method of the chip-packaging structure provided according to the present invention
The generalized section of rapid formation structure is as illustrated in figures 2a and 2b.
Embodiment two is with the difference of embodiment one, formed after the first encapsulated member 6 with walk
Before rapid 4, also carry out following steps:
First, the first encapsulated member 6 is carried out opening process, with the described second weight cloth of exposed part top
Line layer (i.e. the 1st layer second reroutes layer 3).Concrete, the first encapsulated member 6 is carried out the side of opening process
Method is identical with the method that the i-th cover layer carries out opening process.
Then, the first encapsulated member 6 forms triple wiring layers 7 so that triple wiring layers 7 extend to
In the opening of the first encapsulated member 6, the described second rewiring layer with top electrically connects.
Then, electronic component 8 is electrically connected on triple wiring layers 7.Electronic component can be naked with quasiconductor
The active devices such as chip, it is also possible to for passive devices such as electric capacity, inductance or resistance.In the present embodiment, electronics
Element 8 is selected from semiconductor bare chip.The mode being electrically connected on triple wiring layers 7 by electronic component 8 can
To be electrically connected in the way of the second of top reroutes on layer 3 identical, as shown in Figure 2 a, first with chip 5
Triple wiring layers 7 are formed interconnection bumps 81, on interconnection bumps 81, then form weld layer 82,
Finally make electronic component 8 by active face towards in the way of triple wiring layers 7, by electric conductor 83 with weld
Layer 82 electrical connection.Electric conductor 83 is positioned on the pad of electronic component 8, and it can pass through salient point routing technique shape
Become.
Finally, the second encapsulated member 9 of encapsulating electronic component 8 is formed.
As shown in Figure 2 b, after forming the second encapsulated member 9, then remove package carrier 1, to be formed such as figure
Chip-packaging structure shown in 3b.On electronic component 8, electrode is rerouted by triple wiring layers 7, second
Layer 3 and the first rewiring layer 2 are drawn out to the surface of chip-packaging structure, reroute layer eventually through first
With external electrical connections.
Embodiment three
Fig. 3 a to Fig. 3 g be the chip-packaging structure according to the embodiment of the present invention three manufacture method in each work
Skill step forms the generalized section of structure.It is specifically described the present invention below in conjunction with Fig. 3 a to Fig. 3 g to provide
Chip packaging method and chip-packaging structure.
As shown in Fig. 3 a to Fig. 3 g, the manufacture method of the chip-packaging structure that embodiment three provides and embodiment
The key step of one is essentially identical, its specifically include that first package carrier 1 (can by carrying basic 11 with
Metal level 12 is constituted) upper the first rewiring layer 2 forming patterning, then reroute shape on layer 2 second
Becoming N shell second to reroute layer, N shell described in the present embodiment second reroutes layer and includes the 1st layer of second weight cloth
Line layer 3 and the 2nd layer second reroute layer 3`, then after at the second rewiring layer core installed above of top
Sheet (as shown in 3e, first forms interconnection bumps 51, then in interconnection on the second rewiring layer 3` of top
Projection 51 surface forms weld layer 52, finally by the active face of chip 5 towards weld layer 52, and by leading
Electricity body 53 is connected with weld layer electricity 52), eventually form the first encapsulated member 6 of encapsulating chip 5 (such as Fig. 3 f institute
Show) and remove package carrier 1, thus form chip-packaging structure as shown in figure 3g.
Embodiment three and the difference of embodiment one are only rerouting the concrete of layer with formation described N shell second
Method is different, the most in the present embodiment, only to forming the step for that described N shell second reroutes layer tool
Body method elaborates, and remaining step can refer to embodiment one.
Form concretely comprising the following steps of the 1st layer of second rewiring layer 3 that described N shell second reroutes in layer:
Step a1: reroute first and form the 1st layer of wiring projection 31 on 2.
As shown in Figure 3 a, the first rewiring layer 2 includes that relative first surface and second surface (carry with encapsulation
The one side that body 1 contacts), and first reroute layer 2 formed by multiple pin arrangements, the 1st layer wiring projection
Multiple 1st wiring projections in 31 lay respectively on multiple described pin, and each described pin is in level
The area of section in direction connects up projection area of section in the horizontal direction more than being positioned at the thereon described 1st, from
And the weld zone of the outer pin of the chip-packaging structure shown in beneficially Fig. 3 g, thus improve itself and external electrical
The reliability of road welding electrical connection.Wherein, the first rewiring layer is vertical with the second rewiring layer stacking direction
Direction, described horizontal direction is vertical with described vertical direction.Wiring projection in 1st layer of wiring projection is permissible
For copper billet, its shape can be cuboid, cylinder etc..
Step b1: cover the first rewiring layer 2 with insulant, to form the 1st layer of cover layer the 4, the 1st
Layer wiring projection 31 is exposed, as shown in Figure 3 b by described 1st layer of cover layer 4.
Step c1: form the 1st layer of figure electrically connected with the 1st layer of wiring projection 31 on the 1st layer of cover layer 4
Case conductive layer 32 so that the 1st layer of wiring projection the 31 and the 1st pattern layers conductive layer 32 constitutes the 1st layer
Reroute layer 3, as shown in Figure 3 c.
Such as Fig. 3 d, form the concrete step of the 2nd layer of second rewiring layer 3` that described N shell second reroutes in layer
Suddenly it is:
Step a2: reroute at 1 layer second and form the 2nd layer of wiring projection 31` on layer 3；
Step b2: cover the 1st layer second with insulant and reroute layer 3, to form the 2nd layer of cover layer 4`,
2nd layer of wiring projection 31 is exposed by the 2nd layer of cover layer 4`,
Step c2: form the 2nd pattern layers electrically connected with the 2nd layer of wiring projection on the 2nd layer of cover layer
Conductive layer so that described 2nd layer of wiring projection constitutes the 2nd layer of weight cloth with described 2nd pattern layers conductive layer
Line layer 3`.
If in other embodiments, if described N shell second reroutes the N in layer is more than 2, i is more than 1, then
Form the step of the described second rewiring layer of i-th layer in rewiring layer described in N shell to include:
Step ai: reroute at described i-1 layer second and form i-th layer of wiring projection on layer；
Step bi: cover described the i-th-1 layer second with insulant and reroute layer, to form i-th layer of cover layer,
Described i-th layer of wiring projection is exposed by described the i-th-1 layer cover layer；
Step ci: form i-th layer electrically connected with described i-th layer of wiring projection on described i-th layer of cover layer
Patterned conductive layer so that described i-th layer of wiring projection constitutes described the with described i-th pattern layers conductive layer
I layer reroutes layer.
Wherein, described i-th pattern layers conductive layer is rerouted district's arrangement by multiple i-th and forms, described i-th layer
Multiple i-th wiring projections in wiring projection lay respectively at multiple i-th and reroute in district.For the ease of rerouting
The electrode of chip 5 and the reliability of raising chip package, and each described i-th rewiring district is at described water
Square to area of section more than be positioned at thereon described 1st wiring projection area of section in the horizontal direction.
Therefore, in the manufacture method of the chip-packaging structure that the present invention provides, first shape on package carrier
Become the first rewiring layer, reroute formation N shell second on layer described first the most again and reroute layer, then
Chip being electrically connected to top second and reroutes on layer, remove described package carrier the most again, make is described
First reroutes the exposed surface at described chip-packaging structure of layer, using as described chip-packaging structure with outer
The outer pin of portion's electrical connection.Owing to described manufacture method first configures rewiring layer, then chip, even if
Configuration occurs in that mistake during rerouting layer, also will not cause scrapping of chip, effectively raise core
The yield of sheet encapsulation and the cost of reduction chip package.
According to embodiments of the invention as described above, these embodiments do not have all of details of detailed descriptionthe,
Also the specific embodiment that this invention is only described it is not intended to.Obviously, as described above, a lot of repairing can be made
Change and change.These embodiments are chosen and specifically described to this specification, in order to preferably explain the present invention
Principle and actual application, so that skilled artisan can utilize the present invention and well at this
Amendment on the basis of invention uses.The present invention is only limited by claims and four corner thereof and equivalent.
Claims (14)
1. the manufacture method of a chip-packaging structure, it is characterised in that including:
Package carrier is formed the first rewiring layer of patterning,
Reroute described first and form the second rewiring layer of N shell patterning on layer, adjacent layer described
Second reroutes layer is electrically connected to each other, and described the second of the bottom reroutes layer and reroute layer with described first
Electrical connection,
Chip is electrically connected to described the second of top and reroutes on layer,
Remove described package carrier so that described first reroutes the exposed table at described chip-packaging structure of layer
Face, using the outer pin as described chip-packaging structure Yu external electrical connections.
Manufacture method the most according to claim 1, it is characterised in that form the second weight described in N shell
The step of the 1st layer of second rewiring layer in wiring layer includes:
Cover described first with insulant and reroute layer, form the 1st layer of cover layer,
Described 1st layer of cover layer is carried out opening process, to expose described first rewiring layer,
Form the 1st layer on described 1st layer of cover layer described second reroutes layer so that the institute of the 1st layer
State the second rewiring layer to extend to that the opening of described 1st layer of cover layer reroutes layer with described first and electrically connect.
Manufacture method the most according to claim 2, it is characterised in that i is more than 1, forms N shell institute
State the step of the described second rewiring layer of i-th layer in rewiring layer to include:
Cover with insulant and reroute on layer at described the i-th-1 layer second, form i-th layer of cover layer,
Described i-th layer of cover layer is carried out opening process, to expose described the i-th-1 layer described second rewiring
Layer,
Form i-th layer on described i-th layer of cover layer described second reroutes layer so that i-th layer described
Second reroutes layer extends to reroute layer electricity with described the i-th-1 layer second in the opening of described i-th layer of cover layer
Connect.
Manufacture method the most according to claim 3, it is characterised in that described i-th layer of cover layer is entered
The step that row opening processes includes:
Position according to described the i-th-1 layer second rewiring layer obtained before forming described i-th layer of cover layer
Data, position the position at described the i-th-1 layer second rewiring layer place,
Utilize laser beam to described i-th layer of cover layer in described the i-th-1 layer second position rerouting layer place
Carry out opening process, reroute layer with exposed described the i-th-1 layer second.
Manufacture method the most according to claim 1, it is characterised in that form the second weight cloth described in N shell
The step of the 1st layer of second rewiring layer in line layer includes:
Reroute described first and form the 1st layer of wiring projection,
Cover described first with insulant and reroute layer, to form the 1st layer of cover layer, described 1st layer of cloth
Line projection is exposed by described 1st layer of cover layer,
Described 1st layer of cover layer is formed the 1st pattern layers electrically connected with described 1st layer of wiring projection
Conductive layer,
Described 1st layer of wiring projection constitutes described 1st layer with described 1st pattern layers conductive layer and reroutes layer.
Manufacture method the most according to claim 5, it is characterised in that i is more than 1, forms N shell institute
State the step of the described second rewiring layer of i-th layer in rewiring layer to include:
Reroute at described i-1 layer second and on layer, form i-th layer of wiring projection,
Cover described the i-th-1 layer second with insulant and reroute layer, to form i-th layer of cover layer, described the
I layer wiring projection is exposed by described i-th layer of cover layer,
Described i-th layer of cover layer is formed the i-th pattern layers electrically connected with described i-th layer of wiring projection lead
Electric layer,
Described i-th layer of wiring projection constitutes described i-th layer with described i-th pattern layers conductive layer and reroutes layer.
Manufacture method the most according to claim 5, it is characterised in that described first reroutes layer by many
Individual pin arrangements forms, and the multiple 1st wiring projections in described 1st layer of wiring projection lay respectively at multiple institute
State on pin, and each described pin area of section in the horizontal direction is more than being positioned at the thereon described 1st
Wiring projection area of section in the horizontal direction.
Manufacture method the most according to claim 7, it is characterised in that described i-th pattern layers conduction
Floor is rerouted district's arrangement by multiple i-th and forms, and the multiple i-th wiring projections in described i-th layer of wiring projection divide
It is not positioned at multiple i-th to reroute in district, and each described i-th rewiring district is in the cross section of described horizontal direction
Area is more than being positioned at described 1st wiring projection area of section in the horizontal direction thereon.
Manufacture method the most according to claim 1, it is characterised in that also include: form encapsulating described
First encapsulated member of chip.
Manufacture method the most according to claim 9, it is characterised in that also include:
Described first encapsulated member is carried out opening process, reroutes layer with described the second of exposed part top,
Described first encapsulated member forms triple wiring layers so that described triple wiring layers extend to institute
State in the opening of the first encapsulated member with top described second reroute layer electrically connect,
Electronic component is electrically connected on triple wiring layers,
Form the second encapsulated member encapsulating described electronic component.
11. manufacture methods according to claim 1, it is characterised in that be electrically connected to chip push up most
Step step on described second wiring layer of layer includes:
Described second wiring layer of top is formed interconnection bumps,
Weld layer is formed on described interconnection bumps surface；
By the active face of chip towards described weld layer, and electrically connected with described weld layer by electric conductor, institute
State electric conductor to be positioned on the pad of described active face.
12. manufacture methods according to claim 11, it is characterised in that also include: by described core
Before sheet is electrically connected with described weld layer by electric conductor, formed on described pad by salient point routing technique
Described electric conductor.
13. manufacture methods according to claim 1, it is characterised in that described package carrier includes holding
Carried base board and the metal level being positioned on described bearing substrate,
Described metal level, as Seed Layer, utilizes electroplating technology to form described first weight cloth on described metal level
Line layer.
14. 1 kinds of chip packages formed according to the manufacture method described in any one in claim 1 to 13
Structure.
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| CN201610292652.6A CN105895538A (en) | 2016-04-28 | 2016-04-28 | Manufacture method for chip packaging structure and chip packaging structure |
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| CN108269745A (en) * | 2016-12-30 | 2018-07-10 | 群创光电股份有限公司 | Encapsulating structure and preparation method thereof |
| CN109786261A (en) * | 2018-12-29 | 2019-05-21 | 华进半导体封装先导技术研发中心有限公司 | A kind of packaging method and structure of integrated passive device |
| CN110739292A (en) * | 2019-09-02 | 2020-01-31 | 上海先方半导体有限公司 | 3D packaging structure and manufacturing method thereof |
| CN111200351A (en) * | 2018-10-31 | 2020-05-26 | 圣邦微电子（北京）股份有限公司 | Power module and packaging integration method thereof |
| CN111696870A (en) * | 2020-05-20 | 2020-09-22 | 广东佛智芯微电子技术研究有限公司 | Double-sided fan-out packaging method and double-sided fan-out packaging structure |
| CN113571422A (en) * | 2020-04-29 | 2021-10-29 | 群创光电股份有限公司 | Method for manufacturing electronic device |
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| CN111696870A (en) * | 2020-05-20 | 2020-09-22 | 广东佛智芯微电子技术研究有限公司 | Double-sided fan-out packaging method and double-sided fan-out packaging structure |
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