CN109786261A - A kind of packaging method and structure of integrated passive device - Google Patents

A kind of packaging method and structure of integrated passive device Download PDF

Info

Publication number
CN109786261A
CN109786261A CN201811640502.5A CN201811640502A CN109786261A CN 109786261 A CN109786261 A CN 109786261A CN 201811640502 A CN201811640502 A CN 201811640502A CN 109786261 A CN109786261 A CN 109786261A
Authority
CN
China
Prior art keywords
passive device
layer
conducting bridge
conductive metal
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811640502.5A
Other languages
Chinese (zh)
Inventor
姚大平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Center for Advanced Packaging Co Ltd
Original Assignee
National Center for Advanced Packaging Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Center for Advanced Packaging Co Ltd filed Critical National Center for Advanced Packaging Co Ltd
Priority to CN201811640502.5A priority Critical patent/CN109786261A/en
Publication of CN109786261A publication Critical patent/CN109786261A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto

Abstract

The invention discloses the packaging methods and structure of a kind of integrated passive device, the method comprise the steps that the first surface in support plate attaches conducting bridge and chip;Conducting bridge is the internal block at least one conductive metal wire, and conducting bridge is prepared by the following method: predetermined position punches and fills conductive metal in hole on the substrate of inorganic as needed;Cutting substrate as needed, obtains conducting bridge;Support plate first surface formed molding layer, the side wall of molding layer coating chip and conducting bridge, and in the pad and conducting bridge of exposed chip conductive metal wire both ends;Passive device layer is set toward or away from the side of support plate in molding layer, passive device layer is for being arranged at least one passive device.The present invention program can be improved the wiring density for rerouting layer, and the insertion passive device in rerouting layer is avoided to cause the larger-size problem of encapsulating structure.It can guarantee that chip and passive device stack interconnect yield with higher using conducting bridge.

Description

A kind of packaging method and structure of integrated passive device
Technical field
The present invention relates to integrated circuit Advanced Packaging fields, and in particular to a kind of integrated passive member of wafer scale fan-out-type The packaging method and structure of part.
Background technique
Passive device, such as capacitor, resistance, inductance etc. are all essential components inside many electronic devices, They inside each electronic-component module quantity number be chip and passive member depending on IC design requirement Part electrical connection, realizes the electrical functions of microelectronic component.However, the volume due to passive device is often smaller, if itself and encapsulation Good chip is using conducting wire connection, or connection is fanned out to around chip, then can make that chip periphery circuit is more scattered, wiring Complexity, package module are sufficiently bulky.For this purpose, currently advanced encapsulation technology would generally be in the encapsulation passive member integrated simultaneously of chip Part simplifies packaging technology, it is often more important that, integrated passive device can be prepared into smaller but with better function, collection It is more preferable at the package module performance of passive device.
The packaging method of existing integrated passive device includes the following steps: to form interim bonded layer on substrate;By chip 1 is attached on interim bonded layer;Molding layer 2 is formed on interim bonded layer;Passive device layer 3 is formed on the surface of molding layer 2; The first insulating layer 4 is formed on passive device layer 3;Plate body is overturn;Substrate and adhered layer are removed, knot as shown in Figure 1A is obtained Structure;Conductive metal column 5 is formed in molding layer 2;Formed on the surface of molding layer 2 and reroute layer 6, and soldered ball 7 is set, obtain as Structure shown in Figure 1B.Wherein, the step of conductive metal column 5 is formed in molding layer 2 includes: to use on the surface of molding layer 2 The mode of laser drill forms through-hole, then fills conductive material in the through hole.
However, it is found by the inventors that being accordingly used in filling since the thickness of molding layer is thicker (the typically larger than thickness of chip) The through-hole that conductive material forms conductive metal column 5 is usually relatively deep, and the material of molding layer is often the materials such as insulating resin, inconvenient In the through-hole of preparation high-aspect-ratio (namely the depth in hole and the ratio of diameter larger), therefore, the conductive metal in the above method Column is prepared into relatively slightly, and this severely limits the electric properties of passive device, also increases the conductor layouts' difficulty for rerouting layer.Example Such as, some passive devices are connect with chip needs to match thinner conductive metal wire and can play preferable electric property, but It is since above-mentioned technique can not make, passive device must just be made very big;On the other hand, there is electricity in conductive metal column 5 On the rewiring layer of connection relationship, for be not electrically connected near the end of conductive metal column 5 but with the conductive metal column 5 two Root conducting wire, wire spacing are at least greater than the end diameter of conductive metal column 5, can guarantee that the electric current of this two conducting wires will not It influencing each other, this reduces the wiring density for rerouting layer to a certain extent, the surface area for rerouting layer is increased, if therefore So that encapsulating structure surface area is smaller, the conductor layouts' difficulty for rerouting layer is further increased.
Summary of the invention
In view of this, the embodiment of the invention provides the packaging method and structure of a kind of integrated passive device, it is existing to solve There is the electric property of passive device in technology to be restricted, reroute the larger problem of the layout difficulty of layer.
According in a first aspect, the embodiment of the invention provides a kind of packaging methods of integrated passive device, comprising: in support plate First surface attach conducting bridge and chip;Molding layer is formed in the first surface of the support plate, described in molding layer cladding The side wall of chip and the conducting bridge, and expose the both ends of conductive metal wire in the pad and the conducting bridge of the chip;? Passive device layer is arranged toward or away from the side of the support plate in the molding layer, and the passive device layer is for being arranged at least one A passive device.
Optionally, the conducting bridge is the internal block at least one conductive metal wire, and the conducting bridge passes through Following methods make to obtain: predetermined position punches and fills conductive gold in the hole on the substrate of inorganic as needed Belong to;The substrate is cut as needed, obtains the conducting bridge.
Optionally, the pad of the chip is towards the direction of the support plate;The first surface in the support plate is formed After the step of molding layer, further includes: passive device layer is set backwards to a side surface of the support plate in the molding layer.
Optionally, after the step of first surface in the support plate forms molding layer, further includes: in the molding The predetermined surface setting of layer reroutes layer and/or soldered ball, wherein the predetermined surface and passive device layer are located at the mould The two sides of sealing.
Optionally, it is described the molding layer toward or away from the support plate side be arranged passive device layer the step of it Afterwards, further includes: protective layer is set in the passive device layer surface, to protect passive device.
According to second aspect, the embodiment of the invention provides a kind of encapsulating structures of integrated passive device, comprising: chip, Molding layer, coats the side wall of the chip, and exposes the pad of the chip;Conducting bridge has at least one conductive to be internal The block of metal wire;The conducting bridge penetrates through the molding layer, and in the conducting bridge conductive metal wire both ends respectively in institute The both side surface for stating molding layer is exposed;Passive device layer is set to the side of the molding layer;The passive device layer is for setting Set at least one passive device.
Optionally, the conducting bridge makes obtain by the following method: making a reservation on the substrate of inorganic as needed Position punches and fills conductive metal in the hole, cuts the substrate as needed to obtain the conducting bridge.
Optionally, the encapsulating structure further include: reroute layer and/or soldered ball, be set to the reservation chart of the molding layer Face, wherein the predetermined surface and passive device layer are located at the two sides of the molding layer.
Optionally, the encapsulating structure further include: protective layer is set to the surface of the passive device layer, for protecting Passive device.
The encapsulating structure that passive device is integrated provided by the embodiment of the present invention is replaced in the prior art using conducting bridge Conductive metal column realizes passive device layer and being electrically connected outside chip and packaging body, on the one hand, due to conducting bridge be Punching and fill conductive metal in hole on the substrate of inorganic and obtain, internal conductive metal wire can be made compared with Carefully, therefore, on the rewiring layer for having electrical connection with conductive metal wire, near the end of conductive metal wire but not Two conducting wires being electrically connected with conductive metal wire, wire spacing, which is arranged, can guarantee that the electric current of two conducting wires will not be mutual compared with urine It influences;On the other hand, in punching on the substrate of inorganic and the filling conductive metal in hole, it can according to need chip weldering The distribution situation of disk reroutes the layout scenarios of layer to determine the layout in hole, and above-mentioned two aspect, which can be improved, reroutes layer Wiring density reduces the surface area for rerouting layer.The insertion passive device in rerouting layer is avoided to cause to integrate multiple quilts simultaneously The larger-size problem of the encapsulating structure of dynamic element.Conductive gold is filled due to the punching on the substrate of inorganic and in hole When category, can according to the conductive metal wire of the requirement matched design different-diameter of passive device (capacitor, resistance, inductance etc.), because This, the passive device in packaging body can preferably play its electric property.
Detailed description of the invention
It, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical solution in the prior art Embodiment or attached drawing needed to be used in the description of the prior art be briefly described, it should be apparent that, it is described below Attached drawing is some embodiments of the present invention, for those of ordinary skill in the art, before not making the creative labor It puts, is also possible to obtain other drawings based on these drawings.
Figure 1A to Figure 1B shows the obtained structural representation of part steps of the packaging method of existing integrated passive device Figure;
Fig. 2 shows a kind of flow charts of the packaging method of integrated passive device according to an embodiment of the present invention;
Fig. 3 shows the flow chart of the packaging method of another integrated passive device according to an embodiment of the present invention;
Fig. 4 A to Fig. 4 G shows part steps institute in a kind of packaging method of integrated passive device of the embodiment of the present invention Obtained structural schematic diagram;
Appended drawing reference:
10 --- support plate;20 --- interim bonded layer;30 --- conducting bridge;
31 --- conductive metal wire;32 --- inorganic;40 --- chip;
50 --- molding layer;60 --- passive device layer;70 --- protective layer;
80 --- reroute layer;90 --- soldered ball.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art are not having Every other embodiment obtained under the premise of creative work is made, shall fall within the protection scope of the present invention.
Embodiment one
The embodiment of the invention provides a kind of encapsulating structures of integrated passive device, as shown in Figure 4 G, the integrated passive member The encapsulating structure of part includes chip 40, molding layer 50, conducting bridge 30 and passive device layer 60.
The side wall of 50 coating chip of molding layer, and the pad of exposed chip.
Conducting bridge 30 is the internal block at least one conductive metal wire, and conducting bridge 30 makes by the following method Obtain: predetermined position punches and in hole on the substrate of inorganic (for example, silicon, silica, glass, ceramics) as needed Fill conductive metal;Then cutting substrate as needed, obtains conducting bridge.The longitudinal sectional view of conducting bridge 30 refers in Fig. 4 A 30, top view refers to Fig. 4 B.It can be seen that conducting bridge 30 consists of two parts: conductive metal wire 31 and coated with conductive gold Belong to the inorganic 32 of line 31.
Conducting bridge 30 penetrate through molding layer 50, and in conducting bridge 30 conductive metal wire 31 both ends respectively the two of molding layer 50 Expose side surface.
Passive device layer 60 is set to the side of molding layer 50, and passive device layer 60 is for being arranged at least one passive member Part, such as be capacitor shown in the dotted line frame A of Fig. 4 G, be inductance coil shown in dotted line frame B, shown in dotted line frame C be resistance. The passive device of passive device layer can pass through conducting wire, the core of conductive metal wire 31 and 50 other side of molding layer in conducting bridge 30 Piece or element electrical connection.
The encapsulating structure of above-mentioned integrated passive device replaces conductive metal column in the prior art using conducting bridge to realize Passive device layer and being electrically connected outside chip and packaging body, on the one hand, since conducting bridge is on the substrate of inorganic It punches and fills what conductive metal obtained, internal conductive metal wire can be made relatively thin, therefore, have with conductive metal wire On the rewiring layer of electrical connection, for two not be electrically connected near the end of conductive metal wire but with conductive metal wire Conducting wire, wire spacing, which is arranged, can guarantee that the electric current of two conducting wires will not influence each other compared with urine;On the other hand, in inorganic Substrate on when punching and filling conductive metal, can according to need the distribution situation of chip bonding pad or reroute the layout of layer Situation determines that the layout in hole, above-mentioned two aspect can be improved the wiring density for rerouting layer, reduce the surface area for rerouting layer; The insertion passive device in rerouting layer is avoided to cause to integrate the larger-size problem of the encapsulating structure of multiple passive devices.By It, can be according to passive device (capacitor, resistance, electricity when punching on the substrate in inorganic and the filling conductive metal in hole Sense etc.) requirement matched design different-diameter conductive metal wire, therefore, the passive device in packaging body can be played preferably Its electric property.
Optionally, as shown in Figure 4 G, encapsulating structure further include: reroute layer 80 and/or soldered ball 90, be set to molding layer 50 predetermined surface, wherein predetermined surface and passive device layer 60 are located at the two sides of molding layer 50.Wherein, in conducting bridge 30 Conductive metal wire one end can with reroute layer 80 at least one conducting wire be electrically connected, the other end can be with passive device layer 60 at least one passive device electrical connection, reroutes layer 80 so as to which the pad of integrated passive device to be drawn out to On, so that the soldered ball of the passive device is further arranged.When one end of the conductive metal wire in conducting bridge 30 and passive device electricity When connection, the conducting wire rerouted on layer 80 can be electrically connected with one end with the conductive metal wire, the pad of the other end and chip 40 Connection, to realize being electrically connected for chip 40 and passive device.
Optionally, as shown in Figure 4 G, which further includes protective layer 70, is set to the surface of passive device layer, is used In protection passive device.
Embodiment two
Fig. 2 shows a kind of flow chart of the packaging method of integrated passive device according to an embodiment of the present invention, the encapsulation Method can be used for making encapsulating structure described in embodiment one, embodiment two or its any one optional embodiment.Such as Shown in Fig. 2, this method comprises the following steps:
S101: conducting bridge and chip are attached in the first surface of support plate;There is at least one conductive metal inside conducting bridge The block of line, and conducting bridge makes obtain by the following method: predetermined position is punched on the substrate of inorganic as needed And conductive metal is filled in hole;Cutting substrate as needed, obtains conducting bridge.
As shown in Figure 4 C, 10 be support plate, and 30 be conducting bridge, and 40 be chip.In step S101, conducting bridge 30 and core are attached The method of piece 40 can be as shown in Figure 4 A and 4 B shown in FIG.: first be arranged interim bonded layer 20 on the surface of support plate 10, then by conducting bridge 30 and chip 40 be attached on interim bonded layer 20;It can also be by other means by 40 Direct Bonding of conducting bridge 30 and chip On support plate 10.The application does not limit specific attaching method herein.
Specific descriptions about conducting bridge 30 refer to embodiment one.
S102: molding layer, the side wall of molding layer coating chip and conducting bridge are formed in the first surface of support plate, and exposes core The both ends of conductive metal wire in the pad and conducting bridge of piece.
As shown in Figure 4 C, 50 be molding layer.The pad of chip 40 can be towards support plate 10, can also be directed away from support plate 10 direction, the present embodiment is it is not limited here.
It should be pointed out that step S102 is after the first surface of support plate 10 forms molding layer 50, the molding layer 50 is not Must in the pad and conducting bridge 30 of exposed chip 40 conductive metal wire 31 both ends, its dew can be made by other means at this time Out, it such as first passes through and grinds the mode that (as shown in Figure 4 D) is thinned and remove most of molding material, then by laser (such as Fig. 4 D In arrow shown in) mode of drilling is removed at 40 pad of chip and 31 end of conductive metal wire is covered in conducting bridge 30 Molding layer material.The application does not do the method for exposing " 31 end of conductive metal wire in 40 pad of chip and conducting bridge 30 " It limits.
S103: passive device layer is set toward or away from the side of support plate in molding layer, passive device layer is for being arranged extremely A few passive device.
For example, can in figure 4 c shown in molding layer 50 upper surface be arranged passive device layer 60, support plate 10 remove It is settable after preceding or dismounting;Can also in figure 4 c shown in molding layer 50 lower surface be arranged passive device layer 60, at this time It must be arranged after the dismounting of support plate 10, or be arranged before attaching chip and conducting bridge on support plate.
The packaging method of above-mentioned integrated passive device replaces conductive metal column in the prior art using conducting bridge to realize Passive device layer and being electrically connected outside chip and packaging body, and first attach conducting bridge and re-form molding layer (in the prior art Even first attaching conductive metal column re-forms molding layer, for the ease of attaching, the end cross-sectional of conductive metal column is often required that The larger namely conductive metal column of product is thicker), on the one hand, since conducting bridge is punched on the substrate of inorganic and in hole Filling conductive metal obtains, and internal conductive metal wire can be made relatively thin, therefore, is electrically connected with conductive metal wire In the wiring of relationship, for two conducting wires not being electrically connected near the end of conductive metal wire but with conductive metal wire, between conducting wire It can guarantee that the electric current of two conducting wires will not influence each other compared with urine away from being arranged;On the other hand, it is beaten on the substrate of inorganic Hole simultaneously when filling conductive metal, can according to need the distribution situation of chip bonding pad or reroutes the layout scenarios of layer in hole To determine that the layout in hole, above-mentioned two aspect can be improved the wiring density for rerouting layer, reduce the surface area for rerouting layer;It avoids Insertion passive device causes to integrate the larger-size problem of the encapsulating structure of multiple passive devices in rerouting layer.Due to It, can be according to passive device (capacitor, resistance, inductance etc.) when being punched on the substrate of inorganic and filling conductive metal in hole Requirement matched design different-diameter conductive metal wire, therefore, the passive device in packaging body can preferably play its electricity Learn performance.
Embodiment three
Fig. 3 shows the flow chart of the packaging method of another integrated passive device according to an embodiment of the present invention, the envelope Dress method can be used for making encapsulating structure described in embodiment one or its any one optional embodiment.As shown in figure 3, This method comprises the following steps:
S201: attaching conducting bridge and chip in the first surface of support plate, and wherein the pad of chip is towards the direction of support plate;It leads There is the block of at least one conductive metal wire, and conducting bridge makes obtain by the following method inside electric bridge: existing as needed Predetermined position punches and fills conductive metal in hole on the substrate of inorganic;Cutting substrate as needed, obtains conducting bridge.
The step specifically refers to step S101.
S202: molding layer, the side wall of molding layer coating chip and conducting bridge are formed in the first surface of support plate, and exposes core The both ends of conductive metal wire in the pad and conducting bridge of piece.
The step specifically refers to step S102.
S203: passive device layer is set backwards to a side surface of support plate in molding layer, passive device layer is for being arranged at least One passive device.
As shown in Figure 4 E, 60 be passive device layer.
S204: protective layer is set in passive device layer surface, to protect passive device.
As described in Fig. 4 E, 70 be protective layer.
S205: support plate is removed.As illustrated in figure 4f.
S206: layer and/or soldered ball are rerouted in the predetermined surface setting of molding layer, wherein predetermined surface and passive device layer It is located at the two sides of molding layer.As shown in Figure 4 G, layer 80 and/or weldering can be rerouted in the surface setting for originally attaching support plate Ball 90.
The packaging method of above-mentioned integrated passive device can be improved the wiring density for rerouting layer, reduces and reroutes layer Surface area;The insertion passive device in rerouting layer is avoided to cause to integrate the larger-size of the encapsulating structure of multiple passive devices Problem.It ensure that chip and the interconnection of passive device stack have very high yield, quilt using previously prepared conducting bridge technology Dynamic element also can preferably play its electric property.Specifically refer to embodiment three.
Although being described in detail about example embodiment and its advantage, those skilled in the art can not departed from Various change, replacement are carried out to these embodiments in the case where spirit of the invention and protection scope defined in the appended claims And modification, such modifications and variations are each fallen within be defined by the appended claims within the scope of.For other examples, ability The those of ordinary skill in domain should be readily appreciated that the order of processing step can become while keeping in the scope of the present invention Change.
In addition, application range of the invention is not limited to the technique, mechanism, system of specific embodiment described in specification It makes, material composition, means, method and step.From the disclosure, will be easy as those skilled in the art Ground understands, for current technique that is existing or will developing later, mechanism, manufacture, material composition, means, method or Step, wherein they execute the function that the corresponding embodiment described with the present invention is substantially the same or the knot that acquisition is substantially the same Fruit can apply them according to the present invention.Therefore, appended claims of the present invention are intended to these techniques, mechanism, system It makes, material composition, means, method or step are included in its protection scope.

Claims (9)

1. a kind of packaging method of integrated passive device characterized by comprising
Conducting bridge and chip are attached in the first surface of support plate;The conducting bridge is internal at least one conductive metal wire Block;
Molding layer is formed in the first surface of the support plate, the molding layer coats the side wall of the chip and the conducting bridge, And expose the both ends of conductive metal wire in the pad and the conducting bridge of the chip;
Passive device layer is set toward or away from the side of the support plate in the molding layer, the passive device layer is for being arranged At least one passive device.
2. the packaging method of integrated passive device according to claim 1, which is characterized in that the conducting bridge passes through following Method makes to obtain: predetermined position punches and fills conductive metal in the hole on the substrate of inorganic as needed; The substrate is cut as needed, obtains the conducting bridge.
3. the packaging method of integrated passive device according to claim 1, which is characterized in that the pad direction of the chip The direction of the support plate;After the step of first surface in the support plate forms molding layer, further includes:
Passive device layer is set backwards to a side surface of the support plate in the molding layer.
4. fan-out-type stacking encapsulation method according to claim 1, which is characterized in that first table in the support plate Face was formed after the step of molding layer, further includes:
Layer and/or soldered ball are rerouted in the predetermined surface setting of the molding layer, wherein the predetermined surface and passive device layer It is located at the two sides of the molding layer.
5. the packaging method of integrated passive device according to claim 1, which is characterized in that described in molding layer court To or backwards to the support plate side be arranged passive device layer the step of after, further includes:
Protective layer is set in the passive device layer surface, to protect passive device.
6. a kind of encapsulating structure of integrated passive device characterized by comprising
Chip,
Molding layer, coats the side wall of the chip, and exposes the pad of the chip;
Conducting bridge, for the internal block at least one conductive metal wire;The conducting bridge penetrates through the molding layer, and described The both ends of conductive metal wire are exposed in the both side surface of the molding layer respectively in conducting bridge;
Passive device layer is set to the side of the molding layer;The passive device layer is for being arranged at least one passive device.
7. the packaging method of integrated passive device according to claim 6, which is characterized in that the conducting bridge passes through following Method makes to obtain: predetermined position punches and fills conductive metal in the hole on the substrate of inorganic as needed; The substrate is cut as needed, obtains the conducting bridge.
8. the encapsulating structure of integrated passive device according to claim 6, which is characterized in that further include:
Layer and/or soldered ball are rerouted, the predetermined surface of the molding layer is set to, wherein the predetermined surface and passive device layer It is located at the two sides of the molding layer.
9. the encapsulating structure of integrated passive device according to claim 6, which is characterized in that further include:
Protective layer is set to the surface of the passive device layer, for protecting passive device.
CN201811640502.5A 2018-12-29 2018-12-29 A kind of packaging method and structure of integrated passive device Pending CN109786261A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811640502.5A CN109786261A (en) 2018-12-29 2018-12-29 A kind of packaging method and structure of integrated passive device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811640502.5A CN109786261A (en) 2018-12-29 2018-12-29 A kind of packaging method and structure of integrated passive device

Publications (1)

Publication Number Publication Date
CN109786261A true CN109786261A (en) 2019-05-21

Family

ID=66499204

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811640502.5A Pending CN109786261A (en) 2018-12-29 2018-12-29 A kind of packaging method and structure of integrated passive device

Country Status (1)

Country Link
CN (1) CN109786261A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113451161A (en) * 2021-06-29 2021-09-28 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104795354A (en) * 2014-01-17 2015-07-22 中芯国际集成电路制造(上海)有限公司 Chip integration method
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN106449547A (en) * 2010-11-11 2017-02-22 日月光半导体制造股份有限公司 Wafer level semiconductor package and manufacturing methods thereof
CN107708300A (en) * 2016-08-09 2018-02-16 矽品精密工业股份有限公司 Electronic stack structure and method for fabricating the same
CN107799490A (en) * 2016-09-05 2018-03-13 矽品精密工业股份有限公司 Electronic package and manufacturing method thereof
CN108172551A (en) * 2016-11-29 2018-06-15 Pep创新私人有限公司 Chip packaging method and encapsulating structure

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106449547A (en) * 2010-11-11 2017-02-22 日月光半导体制造股份有限公司 Wafer level semiconductor package and manufacturing methods thereof
CN104795354A (en) * 2014-01-17 2015-07-22 中芯国际集成电路制造(上海)有限公司 Chip integration method
CN105895538A (en) * 2016-04-28 2016-08-24 合肥祖安投资合伙企业(有限合伙) Manufacture method for chip packaging structure and chip packaging structure
CN107708300A (en) * 2016-08-09 2018-02-16 矽品精密工业股份有限公司 Electronic stack structure and method for fabricating the same
CN107799490A (en) * 2016-09-05 2018-03-13 矽品精密工业股份有限公司 Electronic package and manufacturing method thereof
CN108172551A (en) * 2016-11-29 2018-06-15 Pep创新私人有限公司 Chip packaging method and encapsulating structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113451161A (en) * 2021-06-29 2021-09-28 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure
CN113451161B (en) * 2021-06-29 2023-08-25 矽磐微电子(重庆)有限公司 Semiconductor packaging method and semiconductor packaging structure

Similar Documents

Publication Publication Date Title
CN103219309B (en) Multi-chip fan-out package and forming method thereof
US6838776B2 (en) Circuit device with at least partial packaging and method for forming
KR101233751B1 (en) Micropede stacked die component assembly
JP5042623B2 (en) Semiconductor device
JP5651608B2 (en) Microelectronic assembly having impedance controlled wire bonds and conductive reference components
JP6061937B2 (en) Microelectronic package having stacked microelectronic devices and method of manufacturing the same
JPH07509104A (en) Method for encapsulating semiconductor chips, device obtained by this method, and application to three-dimensional chip interconnection
US20100203677A1 (en) Method for fabricating semiconductor packages with discrete components
KR100926002B1 (en) Semiconductor package device and method of formation and testing
CN104615979A (en) Fingerprint identification module and encapsulation method thereof, and fingerprint identification module group and encapsulation method thereof
CN109148431B (en) Distance sensor chip packaging structure and wafer level packaging method thereof
JP2002057241A (en) Semiconductor package including transplantable conductive pattern, and manufacturing method thereof
CN108962840A (en) Electronic package and manufacturing method thereof
CN105731354A (en) Wafer level package for a mems sensor device and corresponding manufacturing process
CN102153045B (en) Packaging structure with micro-electromechanical element and manufacturing method thereof
CN104396008B (en) Semiconductor package substrate, the package system using semiconductor package substrate and the method for manufacturing package system
CN109801883A (en) A kind of fan-out-type stacking encapsulation method and structure
CN107507816A (en) Fan-out-type wafer scale multilayer wiring encapsulating structure
CN109786261A (en) A kind of packaging method and structure of integrated passive device
CN209276148U (en) A kind of hybrid package system based on fan-out package structure
CN109817589A (en) The encapsulating structure and method of electromagnetic shielding are realized to chip
CN103985684A (en) Chip scale package structure and manufacturing method thereof
CN108630626A (en) Without substrate encapsulation structure
KR100511926B1 (en) Semiconductor chip package and method for forming the same
TW201724612A (en) Lid structure and semiconductor device package including the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20190521

RJ01 Rejection of invention patent application after publication