CN106601635B - Chip package process and chip-packaging structure - Google Patents
Chip package process and chip-packaging structure Download PDFInfo
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- CN106601635B CN106601635B CN201610723214.0A CN201610723214A CN106601635B CN 106601635 B CN106601635 B CN 106601635B CN 201610723214 A CN201610723214 A CN 201610723214A CN 106601635 B CN106601635 B CN 106601635B
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 238000012545 processing Methods 0.000 claims abstract description 26
- 229920002120 photoresistant polymer Polymers 0.000 claims description 38
- 239000002184 metal Substances 0.000 claims description 30
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- 238000005538 encapsulation Methods 0.000 description 14
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
- H01L2224/82035—Reshaping, e.g. forming vias by heating means
- H01L2224/82039—Reshaping, e.g. forming vias by heating means using a laser
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
Abstract
The present invention provides a kind of chip package process and chip-packaging structures, in chip package process provided by the invention, first obtain the position data of the electrode pad on chip, then opening processing is carried out to the encapsulated member for encapsulating the chip using the position data of obtained electrode pad, to expose the electrode terminal of chip, finally electrode terminal is drawn and is electrically connected with external circuit.Therefore the packaging technology is simple, and the encapsulating structure manufacturing cost formed by the technique is low, and reliability and integrated level are high.
Description
Technical field
The present invention relates to chip encapsulation technology field more particularly to a kind of chip package process and chip-packaging structure.
Background technique
When manufacturing integrated circuit, chip usually with other electronic assemblies it is integrated before be packaged.Early stage is applied
Wide chip package process is wire bond package technique, i.e., by the way that the electrode terminal on chip is passed through metal lead wire key
It closes on lead frame, then the packaged type of plastic packaging.However the face of the encapsulating structure formed by wire bond package technique
Product is larger, and encapsulation performance receives the influence of metal lead wire resistance and parasitic capacitance and cannot effectively improve.Therefore, it then falls
Dress packaging technology is come into being, and the flip-chip packaged structure formed by flip-chip packaged technique is since package dimension is small, encapsulation performance
It is high and be concerned.
Fig. 1 is the flip-chip packaged structural schematic diagram formed by flip-chip packaged technique, and chip 02 is by being located at its active face
On conductive bump 021 be electrically connected on lead frame 01, plastic packaging material 03 encapsulates chip 02 and exposes the bottom of lead frame 01
Portion is using as the pin being electrically connected with external circuit.The flip-chip packaged processing step for forming this flip-chip packaged structure includes chip
Stickup, back-off and plastic packaging.As shown in Fig. 2, muti-piece chip 02 is pasted the pre-position on package carrier 00, wherein often
In the electrical terminal of the active face of chip piece 02 be arranged conductive bump 021, then, by the chip on package carrier 00 be buckled to
On the lead frame 01 set as shown in Figure 3, so that the pad pair on conductive bump 021 and lead frame 01
It should be electrically connected, finally carry out plastic packaging and form plastic-sealed body 03.However, as shown in Fig. 2, segment chip 02 cannot accurately be pasted very much
Pre-position (at dotted line) on to package substrate 00, when this stickup, inevitable deviation can make the back-off of chip 02 extremely
When on lead frame 01, as shown in figure 4, conductive bump 021 cannot be electrically connected with pad corresponding on lead frame, so as to
The phenomenon for causing short circuit or the open circuit of encapsulating structure, affects the reliability of encapsulation.
In addition, being moulded again in above-mentioned flip-chip packaged technique since chip 02 to be electrically connected to after lead frame 01
Envelope, therefore, when the size of conductive bump 021 is smaller, plastic packaging material is difficult to be filled between chip 02 and lead frame 01
In gap, the underfill process big using technology difficulty is needed, to increase technology difficulty and manufacturing cost.Moreover, by
It needs to be electrically connected using conductive bump realization between chip 02 and lead frame 01, however due to being located at 02 active face of chip
Conductive bump tool has the dimensions (the typically larger than size of pad), when the electrode terminal quantity on the face of chip active face is got over
When coming more, the spacing between the pad and pad of these electrode terminals also can be smaller and smaller, to can not make on pad
Soldered ball or conductive bump are electrically connected to realize with external circuit.
Summary of the invention
In view of this, the present invention provides a kind of chip package process and chip-packaging structure, to simplify complex process
Degree, the cost for reducing encapsulation, the reliability for improving chip package and the integrated level for increasing encapsulation chip.
A kind of chip package process characterized by comprising
At least chip piece is mounted on package carrier in active face-up mode, is set on the active face of the chip
It is equipped with electrode pad；
Form the encapsulated member for encapsulating the chip；
The position data of the electrode pad is obtained, and stores the position data:
According to the position data, opening processing is carried out to the encapsulated member, with the electrode pad on the exposed chip.
Preferably, the chip package process further include:
Before obtaining the position data, and the packet is formed after the package carrier in the chip attachment
Feng Ti.
Preferably, before obtaining the position data, through the visual electrode pad of the encapsulated member.
Preferably, the chip is encapsulated with transparent insulating materials, to form the encapsulated member.
Preferably, telltale mark is provided on the package carrier.
The position data characterizes the relative position of the relatively described telltale mark of the electrode pad.
Preferably, the chip package process further includes, after carrying out opening processing to the encapsulated member, in the packet
One layer of rewiring layer is at least formed on envelope body, with the electrode position of chip described in rearrangement.
Preferably, forming the step of rerouting layer described in first layer on the encapsulated member includes:
One layer of metal layer is formed on the encapsulated member,
A layer photoresist is formed in the layer on surface of metal,
It treats exposure figure according to the position data to be modified, so that revised exposure figure and the electrode weld
The position of disk matches, and is exposed according to revised exposure figure to the photoresist, to obtain patterned photoetching
Glue-line,
Using the patterned photoresist layer as mask, the photoresist layer is removed after being etched to the metal layer,
To form the first layer from wiring layer.
Preferably, forming the step of rerouting layer described in first layer on the encapsulated member includes:
Metal layer is formed on the encapsulated member,
A layer photoresist is formed in the layer on surface of metal,
It treats exposure figure according to the position data to be modified, so that revised exposure figure and the electrode weld
The position of disk matches, and is exposed according to revised exposure figure to the photoresist, to obtain patterned photoetching
Glue-line,
It using the patterned photoresist layer as mask, is electroplated on the metal layer, to form patterned electricity
Then coating removes the photoresist layer,
It etches away by the metal layer of the electroplated layer exposed part, reroutes layer to form the first layer.
Preferably, the figure to be exposed is the figure to be exposed in laser direct imaging machine, the laser direct imaging
After machine carries out institute's amendment to the figure to be exposed according to the position data, and revised exposure figure is directly scanned into
Picture is on the photoresist, to obtain the patterned photoresist layer.
Preferably, the chip package process further includes forming welding layer on the surface that top reroutes layer, described
Chip is communicated with the outside by the welding layer.
Preferably, the package carrier includes package substrate and the insulating layer on the package substrate, is forming institute
After stating welding layer, the package substrate is removed, and cut the encapsulated member and insulating layer along presetting Cutting Road, with shape
At an at least chip-packaging structure being coated by an insulating material.
Preferably, the position data is obtained by the method that optical scanner positions.
Preferably, include: by the step of method acquisition position data of optical scanner positioning
Color or shape on the profile of all chips are highlighted, then obtains the contour images of the chip, most
Image procossing is carried out to obtain the position data to the contour images afterwards；
Alternatively, highlighting color or shape on all electrode pad central points, all electrodes are then obtained
The scattergram picture that the central point of pad is constituted finally carries out image procossing to the scattergram picture to obtain the positional number
According to.
Preferably, the chip package process further includes, by the chip attachment before the package carrier,
Electric conductor is formed on the electrode pad,
After the encapsulated member is carried out opening processing, the electric conductor is exposed by the encapsulated member.
Preferably, the electric conductor is copper ball, and the copper ball is contacted and is electrically connected with the electrode pad.
Preferably, the chip package process further includes, by the chip attachment before the package carrier,
At least two telltale marks are formed on the package carrier, to be used to determine a reference axis,
The relative position of the relatively described telltale mark of the electrode pad is the electrode pad in the reference axis
Position.
Preferably, the telltale mark be location hole or be filled circles pad.
Preferably, carrying out the step of opening is handled to the encapsulated member includes:
According to the position data and the telltale mark, the position where the electrode pad is oriented,
Opening processing is carried out to the encapsulated member using laser beam at the position where the electrode pad, to remove
State the insulating materials on electrode pad.
Preferably, the chip package process further includes after obtaining the position data, forming the encapsulating
Body.
Preferably, the opening processing is carried out to the encapsulated member using laser drilling machine, the encapsulated member is opened
Mouthful processing the step of include:
The laser drilling machine corrects hole pattern to be drilled according to the position data, and according to the revised drill drawing
Shape drills to the encapsulated member, the revised drillhole pattern is transferred on the encapsulated member, thus described
The opening of the exposed electrode pad is formed on encapsulated member.
Chip-packaging structure manufactured by a kind of chip package process according to above-mentioned any one.
Therefore in chip package process provided by the invention and structure, after chip attachment to package carrier, first
The position data of the electrode pad on chip is obtained, then using the position data of obtained electrode pad to the encapsulating chip
Encapsulated member carry out opening processing, to expose the electrode terminal of chip, finally electrode terminal is drawn and is electrically connected with external circuit
It connects.Therefore the packaging technology is simple, and the encapsulating structure manufacturing cost formed by the technique is low, and reliability and integrated level are equal
It is high.
In addition, before the electrode for drawing chip, being initially formed for protecting core in chip package process provided by the invention
The electrode of the encapsulated member of piece, chip reroutes layer extraction and external electrical connections by being located on encapsulated member.Therefore, the present invention provides
Chip package process, without the need for arriving underfill process, simple process and at low cost, and due to without using conductive stud
Block is electrically connected with lead frame, therefore chip package process provided by the invention adapts to the chip envelope of the electrode terminal of ultra dense spacing
Dress is conducive to the integrated level for improving encapsulation chip.
Detailed description of the invention
By referring to the drawings to the description of the embodiment of the present invention, above-mentioned and other purposes of the invention, feature and
Advantage will be apparent from, in the accompanying drawings:
Fig. 1 is a kind of flip-chip packaged structural schematic diagram；
Fig. 2 is that chip affixes to the structural schematic diagram on package carrier；
Fig. 3 is the structural schematic diagram of lead frame；
Fig. 4 is that chip is buckled to the structural schematic diagram to lead frame；
Fig. 5 a~5e is the section that structure is formed according to processing step each in the chip package process of the embodiment of the present invention
Schematic diagram.
Specific embodiment
Hereinafter reference will be made to the drawings, and the present invention will be described in more detail.In various figures, identical component part is using similar
Appended drawing reference indicate.For the sake of clarity, the various pieces in attached drawing are not necessarily to scale.Furthermore, it is possible to be not shown
Certain well known parts.For brevity, the structure obtained after several steps can be described in a width figure.Below
In describe many specific details of the invention, such as structure, material, size, treatment process and the skill of each component part
Art, to be more clearly understood that the present invention.But it just as the skilled person will understand, can not be according to these
Specific details realizes the present invention.
Fig. 5 a~5e is the signal that structure is formed according to processing step each in the chip package process of the embodiment of the present invention
Figure.Chip package process provided by the invention is specifically described below in conjunction with Fig. 5 a~5e.In order to preferably show each work
The structure formed in skill step, Fig. 5 a is the top view that structure is formed in corresponding processing step with Fig. 5 b, and Fig. 5 c, 5d and 5e
For the partial cutaway view for forming structure in corresponding processing step.
The chip package process that there is provided according to an embodiment of the present invention the following steps are included:
Step 1: as shown in Figure 5 a, for chip attachment process formed structure top view, will at least chip piece 21 with
Active face-up mode is mounted on package carrier 11, and the active face of chip is provided with electrode pad 211, in addition, encapsulation carries
Telltale mark 111 is also provided on body 11.
Before chip 21 is mounted on package carrier 11, usually also need forming at least two on package carrier 11
The telltale mark 111, for determining a reference axis.Such as there are four the telltale marks 111 in the present embodiment, difference position
In on four angles of package carrier 11.In this application, the relative position of 211 relative positioning label 111 of electrode pad refers to electricity
Position of the pole pad 211 in the reference axis determined by telltale mark 111.Wherein, telltale mark 111 can be location hole,
It can be the pad of filled circles.
Step 2: obtaining the position data of electrode pad relative positioning label 111, and store the position data.
The position data is the coordinate parameters in the reference axis described in step 1 of electrode pad 211, and which characterizes electricity
The relative position of 211 relative positioning label 111 of pole pad.In the present embodiment, institute is obtained by the method that optical scanner positions
State position data.Specifically, the step of obtaining the position data by the method that optical scanner positions includes:
Step 21a: highlight color or shape at the profile of all chips 21.For example, by the envelope after pasting chip 21
It loads body 11 and is placed on the optical scanner area in optical scanner positioning device, by the light-illuminating of optical scanning device, so that
Bright pair of illumination or contrast are higher than other regions at the profile of chip 21, to make the color or shape on the profile of chip 21
Shape highlights.
Step 22a: after the color on the profile of chip 21 highlights, the contour images of chip 21 are obtained.For example, can lead to
It crosses and takes pictures or the mode of optical scanner obtains the contour images.
Step 23a: image procossing is carried out to contour images obtained, to obtain the position data.
In other embodiments, the step of obtaining the position data by the method that optical scanner positions may be such as
Lower step:
Step 21b: highlight color or shape on all 211 central points of the electrode pad.Make the electrode pad
The method that color or shape on central point highlight can be identical as in step 21a.
Step 22b: after the color of 211 central point of electrode pad highlights, the central point for obtaining electrode pad 211 is constituted
Scattergram picture.For example, can take pictures or optical scanner by way of obtain the scattergram picture.
Step 23b: image procossing is carried out to center point image, to obtain the position data.
Step 3: as shown in Figure 5 b, being encapsulated on chip 21 with insulating materials, to form encapsulated member 31, and make encapsulated member 31
Exposed telltale mark 111.Fig. 5 c is the schematic diagram of the section structure of an encapsulation unit structure in Fig. 5 b, each described described envelope
Unit is filled by a chip 21, the partial encapsulation carrier 11 under the chip 21 and 31 structure of encapsulated member for encapsulating the chip 21
At.
The insulating materials for being used to form encapsulated member 31 can be plastic packaging material, such as epoxy-plastic packaging material, can pass through plastic packaging work
Skill forms encapsulated member 31.In addition, as shown in Figure 5 c, chip 21 and package carrier 11 are directly additionally provided with adhesive layer 213, and at this
In embodiment, package carrier 11 includes package substrate 112 and the insulating layer 113 on the package substrate, the insulating layer
It can be plastic packaging material, i.e., the described insulating layer 113 can be identical with the forming material of the encapsulated member 31.Therefore, in step 1,
Chip 21 is pasted onto the pre-position on package carrier 11 by adhesive layer 213.In the present embodiment, encapsulated member 31 is formed
Material is opaque plastic packaging material, then encapsulated member 31 is opaque, therefore, before forming encapsulated member, needs first to obtain electrode
The position data of pad relative positioning label 111.
And in another embodiment according to the present invention, encapsulated member 31 can also obtain 211 relative positioning mark of electrode pad
Before the position data of note 111, and chip 21 is mounted on after package carrier 11 and is formed, i.e., the step 2 in above-described embodiment with
The sequence of step 3 can exchange.In this case, in order to preferably obtain the position data, the encapsulated member 31 is extremely
A part is transparent less, and described at least part includes this part on the electrode pad 211, so that
Before obtaining the position data, through the visual electrode pad of the encapsulated member 31, in order to energy in subsequent process steps
Preferably obtain the position data.It, can be in order to practise through the visual described electrode pad this purpose of the encapsulated member 31
Chip 21 is encapsulated, using transparent insulating materials to form encapsulated member 31.In some other embodiments, encapsulated member 31 is formed
Mode can be with are as follows: be first first encapsulated the formation of (i.e. endless total incapsulation) chip 21 with opaque insulating materials and be encapsulated body, the capsule
Envelope body exposes the electrode pad 211, is then encapsulated on body described again, forms one layer of covering electrode weldering with transparent material
The nappe of disk 211, it is described to be encapsulated body and nappe collectively forms the encapsulated member 31.Step 4: as fig 5d, according to step
The position data and telltale mark 111 (showing in Fig. 5 d) stored in rapid 2, carries out opening processing to encapsulated member 31, to go
Except 211 top of electrode pad is for constituting the insulating materials of encapsulated member.
Due to needing to carry out opening processing to encapsulated member 31 in step 4, during being open in order to prevent, can be damaged to
Electrode pad 211 on chip 21, so that the device in chip 21 is damaged, as shown in Fig. 5 a~5e, chip provided by the invention
Packaging technology step can further include: before chip 21 is mounted on package carrier 11, weld in the electrode of chip 21
Electric conductor 212 is formed on disk 211, the electric conductor after step 3, is also encapsulated body 31 and encapsulates.Electric conductor 212 can be copper
Ball, copper ball 212 are formed directly on electrode pad 211, i.e., are in contact and are electrically connected with electrode pad 211.Due to there is copper ball 212
Protection, even if be open to encapsulated member 31, even if opening depth will not weld electrode than presetting slightly deep point
Disk 211 damages.
In step 4, include: to the specific steps that encapsulated member is open
Step 41: according to the position data and the telltale mark stored in step 2, orienting the electrode pad institute
Position.
Step 42: described in the electrode pad oriented position at using laser beam the encapsulated member 31 is carried out
Opening processing, to remove the insulating materials on the electrode pad.
When carrying out opening processing to encapsulated member 31, it is electrically connected to enable to ensure to realize between chip and rewiring layer
It connects, it is necessary to must guarantee to remove all insulating materials on electrode pad 211, after so that being open, on electrode pad 211
Electric conductor 212 be encapsulated that body 31 is exposed, for being electrically connected with the rewiring layer being subsequently formed.
In another embodiment according to the present invention, the opening is carried out to encapsulated member 31 using laser drilling machine
Reason, the specific steps are that: so that the laser drilling machine is corrected hole pattern to be drilled according to the position data, and according to the amendment
Drillhole pattern afterwards drills to encapsulated member 31, and the revised drillhole pattern is transferred on encapsulated member 31, thus
The opening of bare electrode pad 211 is formed on encapsulated member 31.
Step 5: as depicted in fig. 5e, one layer of rewiring layer is at least formed on encapsulated member 31, such as reroute layer 41, with weight
The electrode position of new arrangement chip 21.Each layer rewiring layer is patterned metal layer, two layers connected of rewiring
It is electrically connected to each other between layer, wherein the rewiring layer of the bottom is electrically connected with the electrode pad 211.In encapsulated member 31
On formed first layer described in rewiring layer specific steps may include:
Step 51a: forming one layer of metal layer on encapsulated member 31, which includes at least one layer of metal, and the metal
Layer is electrically connected by the opening being encapsulated on body 31 with electrode pad 211.
Step 52a: a layer photoresist is formed in the layer on surface of metal that step 51 is formed.
Step 53a: treating exposure figure according to the position data and be modified, so that revised exposure figure and institute
The position for stating electrode pad matches, and is exposed according to revised exposure figure to the photoresist, to obtain pattern
The photoresist layer of change.
Step 54a: using the patterned photoresist layer as mask, the light is removed after being etched to the metal layer
Photoresist layer, to form the first layer from wiring layer.
In addition, forming the specific steps of rewiring layer described in first layer on encapsulated member 31 can also include:
Step 51b: forming one layer of metal layer on encapsulated member 31, which includes at least one layer of metal, and the metal
Layer is electrically connected by the opening being encapsulated on body 31 with electrode pad 211.
Step 52b: a layer photoresist is formed in the layer on surface of metal that step 51 is formed.
Step 53b: treating exposure figure according to the position data and be modified, so that revised exposure figure and institute
The position for stating electrode pad matches, and is exposed according to revised exposure figure to the photoresist, to obtain pattern
The photoresist layer of change.
Step 54b: using the patterned photoresist layer as mask, being electroplated on the metal layer, to be formed
Then patterned electroplated layer removes the photoresist layer,
Step 55b: it etches away by the metal layer of the electroplated layer exposed part, is rerouted with forming the first layer
Layer.
It should be noted that figure to be exposed described in step 53a and 53b is pre-set for being mapped to light
Figure on photoresist layer can be that the figure on egative film is passed through the figure in projection mapping to photoresist, or laser
Direct imaging machine is scanned to the laser direct imaging figure on the photoresist, and correcting figure to be exposed according to position data is
Refer to: the offset (position that chip 21 actually mounts that chip 21 is mounted on package carrier 11 is obtained according to the position data
And the deviation of default mounting position), then after obtaining the offset, the figure to be exposed is subjected to corresponding positional shift,
So that the position for the exposure figure being mapped on the photoresist is more matched with the position of the electrode pad 211 of chip 21, mention
The high Aligning degree for rerouting layer relative to electrode pad 211.
Exposure figure is drawn using egative film, then the exposure figure on egative film is passed through into the mode in image transfer to photoresist
Complex process and production efficiency is low.Therefore, it in order to simplify technique, improves efficiency, in the present embodiment, using laser direct imaging
Machine directly forms the exposure figure.The figure to be exposed exposure diagram pre-set in laser direct imaging machine
Shape, after the laser direct imaging machine carries out institute's amendment to the figure to be exposed according to the position data, and will be after amendment
The direct scanning imagery of exposure figure on the photoresist, to obtain the patterned photoresist layer.
Step 6: what is formed in step 5 reroutes surface formation welding layer (Fig. 5 e of the rewiring layer of the top in layer
In it is unmarked), chip 21 is communicated with the outside by the welding layer.Outside can refer to other devices or circuit galley etc..
Step 7: after completing step 6, removing package substrate 112, and cut the encapsulated member along presetting Cutting Road
31 and insulating layer 113, so that the chip-packaging structure of an at least insulating materials described in step 3 cladding is formed, such as Fig. 5 e
It is shown.
In addition, the present invention also provides a kind of chip package knots that chip package process according to an embodiment of the present invention is formed
Structure, which can be as depicted in fig. 5e.
In chip package process provided by the invention, due to obtaining the electricity on simultaneously storage chip after the attachment of chip 21
The position data of pole pad 211, then according to obtained position data come 211 position of positioning chip pad come to encapsulated member
31 carry out opening processing, to realize the extraction of chip electrode.Therefore, in chip package process provided by the invention, core is mounted
Deviation when piece 21 will not impact the reliability of encapsulation.For example, as shown in Figure 5 a, second piece of chip 21 of the first row with
The third block chip 21 of second row deviates from scheduled mounting position, then on chip 21 when in attachment to package carrier 11
Electrode pad 211 also offset from preset position.But due to the position of the electrode pad 211 obtained in step 2
Data are obtained after the attachment of chip 21, therefore, when carrying out opening processing to encapsulated member 31 in step 4, according to institute's rheme
Set data and telltale mark position can accurately at positioning electrode pad 211 position, so as to by the electricity of chip 21
Extreme son is exposed except encapsulated member 31, and then by rerouting layer and external electrical connections.It can be seen that being provided using the present invention
The chip-packaging structure that is formed of chip package process be not in short circuit or open circuit phenomenon, thus encapsulation with higher can
By property.
In addition, before the electrode for drawing chip 21, being initially formed for protecting in chip package process provided by the invention
The electrode of the encapsulated member 31 of chip, chip 21 reroutes the extraction of layer 41 and external electrical connections by being located on encapsulated member 21, without
It needs that the electrode of chip is drawn out on lead frame by conductive bump as existing reverse installation process.Therefore, of the invention
The chip package process of offer, without the need for arriving underfill process, simple process and at low cost, and due to without using leading
Electric convex block is electrically connected with lead frame, therefore chip package process provided by the invention adapts to the core of the electrode terminal of ultra dense spacing
Piece encapsulation is conducive to the integrated level for improving encapsulation chip.
Therefore in chip package process provided by the invention and structure, after chip attachment to package carrier, first obtain
The position data of the electrode pad of coring on piece, then using the position data of obtained electrode pad to the encapsulating chip
Encapsulated member carries out opening processing, to expose the electrode terminal of chip, finally draws electrode terminal and is electrically connected with external circuit.
Therefore the packaging technology is simple, and the encapsulating structure manufacturing cost formed by the technique is low, and reliability and integrated level are high.
It is as described above according to the embodiment of the present invention, these embodiments details all there is no detailed descriptionthe, also not
Limiting the invention is only the specific embodiment.Obviously, as described above, can make many modifications and variations.This explanation
These embodiments are chosen and specifically described to book, is principle and practical application in order to better explain the present invention, thus belonging to making
Technical field technical staff can be used using modification of the invention and on the basis of the present invention well.The present invention is only by right
The limitation of claim and its full scope and equivalent.
Claims (18)
1. a kind of chip package process characterized by comprising
At least chip piece is mounted on package carrier in active face-up mode, is provided on the active face of the chip
Electrode pad；
The encapsulated member for encapsulating the chip is formed, the encapsulated member is located on the package carrier, and covers having for the chip
Source face, the electrode pad are located inside the encapsulated member,
After forming the encapsulated member, the position data of the electrode pad is obtained, and store the position data；
According to the position data, opening processing is carried out to the encapsulated member for encapsulating the chip, with the electricity on the exposed chip
Pole pad,
Wherein, at least part of the encapsulated member is transparent, and described at least part includes being located on the electrode pad
Part, before obtaining the position data, through the visual electrode pad of the encapsulated member.
2. chip package process according to claim 1, which is characterized in that encapsulate the core with transparent insulating materials
Piece, to form the encapsulated member.
3. chip package process according to claim 1, which is characterized in that be provided with positioning mark on the package carrier
Note,
The position data characterizes the relative position of the relatively described telltale mark of the electrode pad.
4. chip package process according to claim 1, which is characterized in that further include being opened to the encapsulated member
After mouth processing, one layer of rewiring layer is formed, at least on the encapsulated member with the electrode position of chip described in rearrangement.
5. chip package process according to claim 4, which is characterized in that form first layer institute on the encapsulated member
Stating the step of rerouting layer includes:
Metal layer is formed on the encapsulated member, the metal layer includes at least one layer of metal,
A layer photoresist is formed in the layer on surface of metal,
It treats exposure figure according to the position data to be modified, so that revised exposure figure and the electrode pad
Position matches, and is exposed according to revised exposure figure to the photoresist, to obtain patterned photoresist layer,
Using the patterned photoresist layer as mask, the photoresist layer is removed after being etched to the metal layer, with shape
At the first layer from wiring layer.
6. chip package process according to claim 4, which is characterized in that form first layer institute on the encapsulated member
Stating the step of rerouting layer includes:
Metal layer is formed on the encapsulated member,
A layer photoresist is formed in the layer on surface of metal,
It treats exposure figure according to the position data to be modified, so that revised exposure figure and the electrode pad
Position matches, and is exposed according to revised exposure figure to the photoresist, to obtain patterned photoresist layer,
Using the patterned photoresist layer as mask, it is electroplated on the metal layer, to form patterned electroplated layer,
Then the photoresist layer is removed,
It etches away by the metal layer of the electroplated layer exposed part, reroutes layer to form the first layer.
7. chip package process according to claim 5 or 6, which is characterized in that
The figure to be exposed is the figure to be exposed in laser direct imaging machine, and the laser direct imaging machine is according to institute's rheme
After data are set to figure progress institute's amendment to be exposed, and by the direct scanning imagery of revised exposure figure in the photoetching
On glue, to obtain the patterned photoresist layer.
8. chip package process according to claim 4, which is characterized in that further include rerouting the table of layer in top
Face forms welding layer, and the chip is communicated with the outside by the welding layer.
9. chip package process according to claim 8, which is characterized in that the package carrier includes package substrate and position
Insulating layer on the package substrate removes the package substrate, and along presetting after forming the welding layer
Cutting Road cuts the encapsulated member and insulating layer, to form an at least chip-packaging structure being coated by an insulating material.
10. chip package process according to claim 1, which is characterized in that obtained by the method that optical scanner positions
The position data.
11. chip package process according to claim 10, which is characterized in that obtained by the method that optical scanner positions
The step of position data includes:
Color or shape on the profile of all chips are highlighted, the contour images of the chip are then obtained, it is finally right
The contour images carry out image procossing to obtain the position data；
Alternatively, highlighting color or shape on all electrode pad central points, all electrode pads are then obtained
Central point constitute scattergram picture, finally to the scattergram picture carry out image procossing to obtain the position data.
12. chip package process according to claim 1, which is characterized in that further include, by the chip attachment in institute
Before stating package carrier, electric conductor is formed on the electrode pad,
After the encapsulated member is carried out opening processing, the electric conductor is exposed by the encapsulated member.
13. chip package process according to claim 12, which is characterized in that the electric conductor is copper ball, the copper ball
It contacts and is electrically connected with the electrode pad.
14. chip package process according to claim 3, which is characterized in that further include, by the chip attachment in institute
Before stating package carrier, at least two telltale marks are formed on the package carrier, to be used to determine a reference axis,
The relative position of the relatively described telltale mark of the electrode pad is position of the electrode pad in the reference axis.
15. chip package process according to claim 14, which is characterized in that the telltale mark is location hole or is
The pad of filled circles.
16. chip package process according to claim 3, which is characterized in that carry out opening processing to the encapsulated member
Step includes:
According to the position data and the telltale mark, the position where the electrode pad is oriented,
Opening processing is carried out to the encapsulated member using laser beam at the position where the electrode pad, to remove the electricity
The encapsulated member on the pad of pole.
17. chip package process according to claim 1, which is characterized in that using laser drilling machine to the encapsulated member
The opening processing is carried out, carrying out the step of opening is handled to the encapsulated member includes:
The laser drilling machine corrects hole pattern to be drilled according to the position data, and according to the revised drillhole pattern pair
The encapsulated member drills, and the revised drillhole pattern is transferred on the encapsulated member, thus in the encapsulating
The opening of the exposed electrode pad is formed on body.
18. chip-packaging structure manufactured by a kind of chip package process according to claim 1.
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| US11018030B2 (en) * | 2019-03-20 | 2021-05-25 | Semiconductor Components Industries, Llc | Fan-out wafer level chip-scale packages and methods of manufacture |
| CN113894445B (en) * | 2021-12-09 | 2022-02-15 | 广东佛智芯微电子技术研究有限公司 | Chip surface punching method based on integration of optical detection and automatic correction |
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| CN104347434A (en) * | 2013-08-06 | 2015-02-11 | 英飞凌科技股份有限公司 | Method for manufacturing a chip arrangement, and a chip arrangement |
| CN105140191A (en) * | 2015-09-17 | 2015-12-09 | 中芯长电半导体（江阴）有限公司 | Packaging structure and manufacturing method for redistribution leading wire layer |
| CN105206539A (en) * | 2015-09-01 | 2015-12-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package preparation method |
| CN105826247A (en) * | 2016-05-05 | 2016-08-03 | 上海集成电路研发中心有限公司 | Chip interconnection wiring method based on fluidic self assembly technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9165841B2 (en) * | 2008-09-19 | 2015-10-20 | Intel Corporation | System and process for fabricating semiconductor packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104347434A (en) * | 2013-08-06 | 2015-02-11 | 英飞凌科技股份有限公司 | Method for manufacturing a chip arrangement, and a chip arrangement |
| CN105206539A (en) * | 2015-09-01 | 2015-12-30 | 华进半导体封装先导技术研发中心有限公司 | Fan-out package preparation method |
| CN105140191A (en) * | 2015-09-17 | 2015-12-09 | 中芯长电半导体（江阴）有限公司 | Packaging structure and manufacturing method for redistribution leading wire layer |
| CN105826247A (en) * | 2016-05-05 | 2016-08-03 | 上海集成电路研发中心有限公司 | Chip interconnection wiring method based on fluidic self assembly technology |
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