CN106601634B - Chip packaging process and chip packaging structure - Google Patents

Chip packaging process and chip packaging structure Download PDF

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Publication number
CN106601634B
CN106601634B CN201610723159.5A CN201610723159A CN106601634B CN 106601634 B CN106601634 B CN 106601634B CN 201610723159 A CN201610723159 A CN 201610723159A CN 106601634 B CN106601634 B CN 106601634B
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chip
layer
electrode pad
position data
pattern
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CN106601634A (en
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谭小春
陆培良
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HEFEI ZUAN INVESTMENT PARTNERSHIP ENTERPRISE
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Hefei Zuan Investment Partnership Enterprise
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73267—Layer and HDI connectors
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect

Abstract

In the chip packaging process provided by the invention, after a chip is mounted on a packaging carrier, position data of an electrode pad on the chip is obtained, and then a rewiring layer is formed on an encapsulating body encapsulating the chip by utilizing the obtained position data of the electrode pad so as to rearrange electrodes of the chip, so that the formed rewiring layer is higher in direct alignment with the chip, the packaging process is simple, the packaging structure formed by the process is low in manufacturing cost, and the reliability and the integration level are high.

Description

Chip packaging process and chip packaging structure
Technical Field
The invention relates to the technical field of chip packaging, in particular to a chip packaging process and a chip packaging structure.
Background
In the manufacture of integrated circuits, chips are typically packaged prior to integration with other electronic assemblies. An early chip packaging process widely used is a wire bonding packaging process, that is, a packaging manner in which electrode terminals on a chip are bonded to a lead frame through metal wires and then plastic-packaged. However, the area of the package structure formed by the wire bonding packaging process is large, and the package performance cannot be effectively improved due to the influence of the metal lead resistance and the parasitic capacitance. Therefore, a subsequent flip-chip packaging process has been developed, and a flip-chip packaging structure formed by the flip-chip packaging process is receiving attention due to a small package size and a high packaging performance.
Fig. 1 is a schematic diagram of a flip-chip package structure formed by a flip-chip packaging process, in which a chip 02 is electrically connected to a lead frame 01 through conductive bumps 021 located on an active surface of the chip, and a molding compound 03 encapsulates the chip 02 and exposes the bottom of the lead frame 01 to serve as leads electrically connected to an external circuit. The flip-chip packaging process for forming the flip-chip packaging structure comprises the steps of chip pasting, back-off and plastic packaging. As shown in fig. 2, a plurality of chips 02 are adhered to predetermined positions on the package carrier 00, wherein a conductive bump 021 is disposed on an electronic terminal of an active surface of each chip 02, then the chip on the package carrier 00 is flipped over to the set lead frame 01 as shown in fig. 3, so that the conductive bump 021 is electrically connected to a pad on the lead frame 01 correspondingly, and finally plastic encapsulation is performed to form a plastic encapsulated body 03. However, as shown in fig. 2, part of the chip 02 cannot be attached to a predetermined position (dotted line) on the package substrate 00 very precisely, and such unavoidable deviation during the attachment may cause the chip 02 to be flipped over onto the lead frame 01, as shown in fig. 4, the conductive bump 021 cannot be electrically connected to a corresponding pad on the lead frame, which may cause a short circuit or an open circuit of the package structure, thereby affecting the reliability of the package.
In addition, in the prior art, when electrodes on the chip 02 need to be rearranged by using a redistribution layer, the redistribution layer is formed on the chip 02 by using a preset pattern, however, the chip 02 deviates from a preset position in the process of being mounted on a package carrier, so that the position of an electrode pad on the chip 02 also deviates from the preset position correspondingly, and the formed redistribution layer and the chip 02 cannot be aligned accurately, thereby affecting the reliability of chip packaging.
Disclosure of Invention
In view of the above, the present invention provides a chip packaging process and a chip packaging structure, so as to simplify the process complexity, reduce the packaging cost, improve the reliability of chip packaging, and increase the integration of packaged chips.
A chip packaging process, comprising:
attaching at least one chip on a packaging carrier in an active surface upward mode, wherein an electrode pad is arranged on the active surface of the chip;
acquiring position data of the electrode pad, and storing the position data:
and forming at least one rewiring layer on an encapsulating body for encapsulating the chip according to the position data so as to rearrange the electrode positions of the chip.
Preferably, the step of forming a first layer of the redistribution layer over the encapsulation comprises:
forming a metal layer on the encapsulation body, wherein the metal layer at least comprises a metal layer,
forming a layer of photoresist on the surface of the metal layer,
correcting the pattern to be exposed according to the position data to make the corrected exposure pattern matched with the position of the electrode pad, exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer,
and taking the patterned photoresist layer as a mask, etching the metal layer and then removing the photoresist layer to form the first secondary wiring layer.
Preferably, the step of forming a first layer of the redistribution layer over the encapsulation comprises:
forming a metal layer on the encapsulation body,
forming a layer of photoresist on the surface of the metal layer,
correcting the pattern to be exposed according to the position data to make the corrected exposure pattern matched with the position of the electrode pad, exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer,
electroplating the metal layer using the patterned photoresist layer as a mask to form a patterned electroplated layer, removing the photoresist layer,
etching away the metal layer exposed by the plating layer to form the first redistribution layer.
Preferably, the pattern to be exposed is a pattern to be exposed in a laser direct imaging machine, and the laser direct imaging machine corrects the pattern to be exposed according to the position data and directly scans and images the corrected exposure pattern on the photoresist to obtain the patterned photoresist layer.
Preferably, the chip packaging process further includes forming a solder layer on a surface of the topmost redistribution layer, and the chip is connected to the outside through the solder layer.
Preferably, the chip packaging process further includes: form the said
And an encapsulation body exposing the electrode pad before the redistribution layer is formed.
Preferably, the encapsulation is formed before the position data is acquired and after the chip is mounted on the package carrier, and the electrode pads are visible through the encapsulation.
Preferably, the chip is encapsulated with a transparent insulating material to form the encapsulation body.
Preferably, the envelope is formed after the position data is acquired.
Preferably, the encapsulation body is subjected to an opening process according to the position data before the redistribution layer is formed to expose the electrode pad.
Preferably, the package carrier is provided with a positioning mark.
The position data characterizes a relative position of the electrode pad with respect to the positioning mark.
Preferably, the package carrier includes a package substrate and an insulating layer on the package substrate, and after the soldering layer is formed, the package substrate is removed, and the encapsulant and the insulating layer are cut along a predetermined cutting path to form at least one chip package structure covered by an insulating material.
Preferably, the position data is acquired by a method of optical scanning positioning.
Preferably, the step of acquiring the position data by a method of optical scanning positioning comprises:
highlighting the color or shape on the outline of all the chips, then acquiring the outline image of the chip, and finally carrying out image processing on the outline image to obtain the position data;
or, the color or the shape on the center point of all the electrode pads is highlighted, then a center point image formed by the center points of all the electrode pads is obtained, and finally the center point image is subjected to image processing to obtain the position data.
Preferably, the chip packaging process further comprises forming an electrical conductor on the electrode pad before mounting the chip on the package carrier,
after the opening processing is carried out on the packaging body, the electric conductor is exposed by the packaging body.
Preferably, the conductive body is a copper ball, and the copper ball is in contact with and electrically connected to the electrode pad.
Preferably, the chip packaging process further includes forming at least two positioning marks on the package carrier for determining a coordinate axis before the chip is mounted on the package carrier,
the relative position of the electrode pad relative to the positioning mark is the position of the electrode pad in the coordinate axis.
Preferably, the positioning mark is a positioning hole or a pad which is a solid circle.
Preferably, the step of opening the enclosure comprises:
positioning the electrode pad according to the position data and the positioning mark,
and opening the packaging body by using laser beams at the position of the electrode pad so as to remove the insulating material on the electrode pad.
Preferably, the opening processing is performed on the enclosing body by using a laser drilling machine, and the step of performing the opening processing on the enclosing body comprises:
and the laser drilling machine corrects a pattern to be drilled according to the position data, and drills the packaging body according to the corrected drilling pattern so as to transfer the corrected drilling pattern to the packaging body, thereby forming an opening exposing the electrode pad on the packaging body.
A chip packaging structure manufactured according to the chip packaging process described in any one of the preceding claims.
Therefore, in the chip packaging process and the chip packaging structure provided by the invention, after the chip is attached to the packaging carrier, the position data of the electrode bonding pad on the chip is firstly acquired, and then the obtained position data of the electrode bonding pad is utilized to form the rewiring layer on the packaging body packaging the chip so as to rearrange the electrodes of the chip, so that the formed rewiring layer has higher direct alignment degree with the chip, the packaging process is simple, and the packaging structure formed by the process has low manufacturing cost and high reliability and integration degree.
In addition, in the chip packaging process provided by the invention, before the electrode of the chip is led out, an encapsulating body for protecting the chip is formed, and the electrode of the chip is led out through a rewiring layer on the encapsulating body to be electrically connected with the outside. Therefore, the chip packaging process provided by the invention does not need to be used for an underfill process, has simple process and low cost, and is suitable for chip packaging of electrode terminals with ultra-dense intervals because the conductive bumps are not needed to be electrically connected with the lead frame, thereby being beneficial to improving the integration level of packaged chips.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:
FIG. 1 is a schematic view of a flip-chip package structure;
FIG. 2 is a schematic diagram of a chip attached to a package carrier;
FIG. 3 is a schematic structural diagram of a lead frame;
FIG. 4 is a schematic view of a chip flipped onto a lead frame;
fig. 5a to 5e are schematic cross-sectional views illustrating structures formed in various process steps in a chip packaging process according to an embodiment of the invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like components are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques for each component, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
Fig. 5a to 5e are schematic views of the structure formed in each process step in the chip packaging process according to the embodiment of the invention. The chip packaging process provided by the invention will be specifically described with reference to fig. 5a to 5 e. To better illustrate the structures formed in the various process steps, fig. 5a and 5b are top views of structures formed in corresponding process steps, and fig. 5c, 5d, and 5e are partial cross-sectional views of structures formed in corresponding process steps.
The chip packaging process provided by the embodiment of the invention comprises the following steps:
step 1: as shown in fig. 5a, which is a top view of a chip mounting process forming structure, at least one chip 21 is mounted on a package carrier 11 with an active surface facing upward, the active surface of the chip is provided with an electrode pad 211, and the package carrier 11 may be further provided with a positioning mark 111.
Before mounting the chip 21 on the package carrier 11, it is usually necessary to form at least two positioning marks 111 on the package carrier 11 for determining a coordinate axis. For example, four positioning marks 111 are provided in the present embodiment, and are respectively located at four corners of the package carrier 11. In the present application, the relative position of the electrode pad 211 with respect to the positioning mark 111 refers to the position of the electrode pad 211 in the coordinate axis defined by the positioning mark 111. The positioning mark 111 may be a positioning hole or a pad of a solid circle.
Step 2: position data of the electrode pad with respect to the positioning mark 111 is acquired and stored.
The position data is coordinate parameters of the electrode pad 211 in the coordinate axes described in step 1, and represents the relative position of the electrode pad 211 with respect to the positioning mark 111. In the present embodiment, the position data is acquired by a method of optical scanning positioning. Specifically, the step of acquiring the position data by an optical scanning positioning method includes:
step 21 a: the color or shape at the outline of all the chips 21 is highlighted. For example, the package carrier 11 with the chip 21 mounted thereon is placed in an optical scanning area of an optical scanning positioning device, and is irradiated by light of the optical scanning device, so that the light at the outline of the chip 21 is brighter or has higher contrast than other areas, thereby highlighting the color or shape on the outline of the chip 21.
Step 22 a: after the color on the outline of the chip 21 is highlighted, an outline image of the chip 21 is acquired. The profile image may be obtained, for example, by photographing or by optical scanning.
Step 23 a: image processing is performed on the obtained contour image to obtain the position data.
In other embodiments, the step of acquiring the position data by the optical scanning positioning method may also be the following steps:
and step 21b, highlighting the color or shape on the center point of all the electrode pads 211. The method of highlighting the color or shape on the center point of the electrode pad may be the same as that in step 21 a.
And step 22b, acquiring a central point image formed by the central point of the electrode pad 211 after the color of the central point of the electrode pad 211 is highlighted. For example, the center point image may be obtained by photographing or optical scanning.
Step 23 b: and carrying out image processing on the central point image to obtain the position data.
And step 3: as shown in fig. 5b, the chip 21 is encapsulated with an insulating material to form an encapsulation body 31, and the encapsulation body 31 exposes the positioning mark 111. Fig. 5c is a schematic cross-sectional structure view of a package unit structure in fig. 5b, where each package unit is composed of a chip 21, a portion of the package carrier 11 under the chip 21, and an encapsulant 31 encapsulating the chip 21.
The insulating material used for forming the encapsulating body 31 may be a molding compound, such as an epoxy molding compound, and the encapsulating body 31 may be formed through a molding process. In addition, as shown in fig. 5c, the chip 21 and the package carrier 11 are directly provided with an adhesive layer 213, and in this embodiment, the package carrier 11 includes a package substrate 112 and an insulating layer 113 located on the package substrate, and the insulating layer may be a molding compound, that is, the insulating layer 113 and the encapsulant 31 may be formed of the same material. Thus, in step 1, the chip 21 is stuck at a predetermined position on the package carrier 11 through the adhesive layer 213. In the embodiment, the material forming the encapsulating body 31 is an opaque plastic encapsulating material, and the encapsulating body 31 is opaque, so before forming the encapsulating body, the position data of the electrode pad relative to the positioning mark 111 needs to be acquired.
In another embodiment according to the present invention, the encapsulation 31 may also be formed before acquiring the position data of the electrode pads 211 relative to the positioning marks 111 and after the chip 21 is mounted on the package carrier 11, that is, the sequence of step 2 and step 3 in the above embodiments may be changed. In this case, in order to better acquire the position data, at least a portion of the encapsulation 31 is transparent, including the portion on the electrode pad 211, so that the electrode pad is visible through the encapsulation 31 before the position data is acquired, thereby facilitating better acquisition of the position data in subsequent process steps. For the purpose of viewing the electrode pads through the encapsulation 31, a transparent insulating material may be used to encapsulate the chip 21 to form the encapsulation 31. In some other embodiments, the enclosure 31 may be formed by: the chip 21 is encapsulated (i.e., incompletely encapsulated) with an opaque insulating material to form an encapsulation body, the electrode pads 211 are exposed from the encapsulation body, and then a cover body covering the electrode pads 211 is formed on the encapsulation body with a transparent material, wherein the encapsulation body and the cover body together form the encapsulation body 31. And 4, step 4: as shown in fig. 5d, according to the position data and the positioning mark 111 (not shown in fig. 5 d) stored in step 2, the encapsulant 31 is subjected to an opening process to remove the insulating material constituting the encapsulant over the electrode pad 211.
Since the step 4 requires opening the encapsulant 31, in order to prevent the electrode pads 211 on the chip 21 from being damaged in the opening process, and thus damage the devices in the chip 21, as shown in fig. 5a to 5e, the chip packaging process provided by the present invention may further include: before the chip 21 is attached to the package carrier 11, an electrical conductor 212 is formed on the electrode pad 211 of the chip 21, which is also encapsulated by the encapsulation 31 after step 3. The conductive body 212 may be a copper ball, and the copper ball 212 is directly formed on the electrode pad 211, i.e., contacts and is electrically connected to the electrode pad 211. Due to the protection of the copper balls 212, even when the encapsulant 31 is opened, the electrode pads 211 are not damaged even if the opening depth is slightly deeper than a predetermined depth.
In step 4, the specific step of opening the enclosure comprises:
step 41: and positioning the position of the electrode pad according to the position data and the positioning mark stored in the step 2.
Step 42: the encapsulant 31 is subjected to an opening process with a laser beam at the position of the located electrode pad to remove the insulating material on the electrode pad.
In order to ensure that the chip can be electrically connected to the redistribution layer when the encapsulant 31 is subjected to the opening process, it is necessary to ensure that all the insulating material on the electrode pad 211 is removed, so that after the opening, the conductive body 212 on the electrode pad 211 is exposed by the encapsulant 31 for electrical connection with the redistribution layer formed later.
In another embodiment of the present invention, the opening process may be performed on the enclosing body 31 by using a laser drilling machine, which comprises the following steps: the laser drilling machine corrects the pattern to be drilled according to the position data, and drills the encapsulation body 31 according to the corrected drilling pattern, so that the corrected drilling pattern is transferred to the encapsulation body 31, and an opening exposing the electrode pad 211 is formed on the encapsulation body 31.
And 5: as shown in fig. 5e, at least one redistribution layer, such as a redistribution layer 41, is formed on the encapsulation 31 to rearrange the electrode positions of the chip 21. Each of the redistribution layers is a patterned metal layer, and two connected redistribution layers are electrically connected to each other, wherein the redistribution layer at the bottommost layer is electrically connected to the electrode pad 211. The specific step of forming the first layer of the redistribution layer on the encapsulation 31 may include:
step 51 a: a metal layer is formed on the encapsulant 31, the metal layer includes at least one metal, and the metal layer is electrically connected to the electrode pad 211 through the opening on the encapsulant 31.
Step 52 a: a layer of photoresist is formed on the surface of the metal layer formed in step 51.
Step 53 a: and correcting the pattern to be exposed according to the position data to enable the corrected exposure pattern to be matched with the position of the electrode bonding pad, and exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer.
Step 54 a: and taking the patterned photoresist layer as a mask, etching the metal layer and then removing the photoresist layer to form the first secondary wiring layer.
In addition, the specific step of forming the first redistribution layer on the encapsulation 31 may further include:
step 51 b: a metal layer is formed on the encapsulant 31, the metal layer includes at least one metal, and the metal layer is electrically connected to the electrode pad 211 through the opening on the encapsulant 31.
Step 52 b: a layer of photoresist is formed on the surface of the metal layer formed in step 51.
Step 53 b: and correcting the pattern to be exposed according to the position data to enable the corrected exposure pattern to be matched with the position of the electrode bonding pad, and exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer.
Step 54 b: electroplating on the metal layer using the patterned photoresist layer as a mask to form a patterned electroplated layer, and removing the photoresist layer,
step 55 b: etching away the metal layer exposed by the plating layer to form the first redistribution layer.
It should be noted that the pattern to be exposed in steps 53a and 53b is a preset pattern for mapping onto the photoresist layer, and may be a pattern for mapping the pattern on the negative film onto the photoresist layer by projection, or may be a pattern directly imaged by the laser scanned onto the photoresist by the laser direct imaging machine, and the correcting the pattern to be exposed according to the position data means: and acquiring the offset (the deviation between the actual mounting position of the chip 21 and the preset mounting position) of the chip 21 mounted on the packaging carrier 11 according to the position data, and after acquiring the offset, performing corresponding position offset on the pattern to be exposed, so that the position of the exposure pattern mapped on the photoresist is more matched with the position of the electrode pad 211 of the chip 21, and the alignment degree of the redistribution layer relative to the electrode pad 211 is improved.
The method of adopting the negative to draw the exposure figure and then transferring the exposure figure on the negative to the photoresist through the image has complex process and low production efficiency. Therefore, in order to simplify the process and improve the efficiency, in the present embodiment, a laser direct imaging machine is used to directly form the exposure pattern. And the pattern to be exposed is a preset exposure pattern in a laser direct imaging machine, the laser direct imaging machine corrects the pattern to be exposed according to the position data, and the corrected exposure pattern is directly scanned and imaged on the photoresist to obtain the patterned photoresist layer.
Step 6: the surface of the topmost redistribution layer among the redistribution layers formed in step 5 forms a solder layer (not labeled in fig. 5 e) through which the chip 21 is connected to the outside. The outside may refer to other devices or circuit printing plates, etc.
And 7: after step 6, the package substrate 112 is removed, and the encapsulant 31 and the insulating layer 113 are cut along a predetermined cutting path, so as to form at least one chip package structure encapsulated by the insulating material in step 3, as shown in fig. 5 e.
In addition, the invention also provides a chip packaging structure formed by the chip packaging process according to the embodiment of the invention, and the structure can be shown as fig. 5 e.
In the chip packaging process provided by the invention, after the chip 21 is mounted, the position data of the electrode pad 211 on the chip is acquired and stored, and then the position of the chip pad 211 is positioned according to the acquired position data to perform opening processing on the encapsulation body 31, so that the extraction of the chip electrode is realized. Therefore, in the chip packaging process provided by the invention, the deviation when the chip 21 is mounted does not influence the reliability of the package. For example, as shown in fig. 5a, when the second chip 21 in the first row and the third chip 21 in the second row are both deviated from the predetermined mounting positions when mounted on the package carrier 11, the electrode pads 211 on the chips 21 are also deviated from the predetermined positions. However, since the position data of the electrode pad 211 obtained in step 2 is obtained after the chip 21 is mounted, when the opening process is performed on the package body 31 in step 4, the position of the electrode pad 211 can be accurately located according to the position data and the position of the locating mark, so that the electrode terminal of the chip 21 can be exposed outside the package body 31 and further electrically connected to the outside through the redistribution layer. Therefore, the chip packaging structure formed by the chip packaging process provided by the invention has no short circuit or open circuit phenomenon, so that the chip packaging structure has higher packaging reliability.
In addition, in the chip packaging process provided by the invention, before the electrodes of the chip 21 are led out, the encapsulating body 31 for protecting the chip is formed, the electrodes of the chip 21 are led out through the rewiring layer 41 on the encapsulating body 21 to be electrically connected with the outside, and the electrodes of the chip are not led out to a lead frame through conductive bumps as in the existing flip chip process. Therefore, the chip packaging process provided by the invention does not need to be used for an underfill process, has simple process and low cost, and is suitable for chip packaging of electrode terminals with ultra-dense intervals because the conductive bumps are not needed to be electrically connected with the lead frame, thereby being beneficial to improving the integration level of packaged chips.
Therefore, in the chip packaging process provided by the invention, after the chip is mounted on the packaging carrier, the position data of the electrode pad on the chip is firstly acquired, and then the obtained position data of the electrode pad is utilized to form the redistribution layer on the packaging body packaging the chip so as to rearrange the electrodes of the chip.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (20)

1. A chip packaging process, comprising:
attaching at least one chip on a packaging carrier in an active surface upward mode, wherein an electrode pad is arranged on the active surface of the chip, a conductor is arranged on the electrode pad, and the packaging carrier comprises a packaging substrate and an insulating layer positioned on the packaging substrate;
encapsulating the chip by using an encapsulating body, wherein at least the part of the encapsulating body, which is positioned on the electrode pad, is transparent;
the electrode pad can be seen through the transparent part of the packaging body, the position data of the electrode pad is obtained, and the position data is stored;
correcting the pattern to be exposed according to the position data, and forming at least one rewiring layer on an encapsulating body for encapsulating the chip so as to rearrange the electrode positions of the chip;
removing the packaging substrate to enable the chip to be wrapped by the insulating layer and the encapsulating body together,
wherein the pattern to be exposed is a preset pattern for mapping onto a photoresist layer, and the correcting the pattern to be exposed according to the position data comprises:
obtaining the offset of the chip mounted on the packaging carrier according to the position data,
after the offset is obtained, the corresponding position offset is carried out on the pattern to be exposed, so that the position of the exposure pattern mapped on the photoresist is matched with the position of an electrode bonding pad of a chip,
the method for forming the first redistribution layer comprises the following steps:
forming a metal layer on the encapsulation body, wherein the metal layer at least comprises a layer of metal;
forming a layer of photoresist on the surface of the metal layer,
patterning the photoresist according to the pattern to be exposed, forming the first redistribution layer according to the patterned photoresist,
before the first metal layer is formed, opening processing is carried out on the packaging body so that the packaging body exposes the electrode pad, and the first metal layer is electrically connected with the electrode pad through the electric conductor.
2. The chip packaging process according to claim 1, wherein the step of forming the first layer of the redistribution layer over the encapsulation further comprises:
correcting the pattern to be exposed according to the position data to make the corrected exposure pattern matched with the position of the electrode pad, exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer,
and taking the patterned photoresist layer as a mask, etching the metal layer, and removing the photoresist layer to form the first redistribution layer.
3. The chip packaging process according to claim 1, wherein the step of forming the first layer of the redistribution layer over the encapsulation further comprises:
correcting the pattern to be exposed according to the position data to make the corrected exposure pattern matched with the position of the electrode pad, exposing the photoresist according to the corrected exposure pattern to obtain a patterned photoresist layer,
electroplating the metal layer using the patterned photoresist layer as a mask to form a patterned electroplated layer, removing the photoresist layer,
etching away the metal layer exposed by the plating layer to form the first redistribution layer.
4. The chip packaging process according to claim 2 or 3,
and the pattern to be exposed is a pattern to be exposed in a laser direct imaging machine, and the laser direct imaging machine corrects the pattern to be exposed according to the position data and directly scans and images the corrected exposure pattern on the photoresist to obtain the patterned photoresist layer.
5. The chip packaging process according to claim 4, further comprising forming a solder layer on a surface of the topmost redistribution layer before removing the package substrate, wherein the chip is connected to the outside through the solder layer.
6. The chip packaging process according to claim 1, further comprising: forming the encapsulation body, and exposing the encapsulation body to the electrode pad before forming the redistribution layer.
7. The chip packaging process according to claim 6, wherein the encapsulant is formed before the position data is obtained and after the chip is mounted on the package carrier.
8. The chip packaging process according to claim 7, wherein the chip is encapsulated with a transparent insulating material to form the encapsulation body.
9. The chip packaging process according to claim 1, wherein the encapsulant is subjected to an opening process according to the position data before the redistribution layer is formed to expose the electrode pad.
10. The chip packaging process according to claim 1, wherein the package carrier is provided with a positioning mark thereon,
the position data characterizes a relative position of the electrode pad with respect to the positioning mark.
11. The chip packaging process according to claim 5, wherein after the bonding layer is formed, the encapsulant and the insulating layer are cut along a predetermined cutting path to form at least one chip package structure covered by an insulating material.
12. The chip packaging process according to claim 1, wherein the position data is obtained by a method of optical scanning positioning.
13. The chip packaging process according to claim 12, wherein the step of acquiring the position data by an optical scanning positioning method comprises:
highlighting the color or shape on the outline of all the chips, then acquiring the outline image of the chip, and finally carrying out image processing on the outline image to obtain the position data;
or, the color or the shape on the center point of all the electrode pads is highlighted, then a center point image formed by the center points of all the electrode pads is obtained, and finally the center point image is subjected to image processing to obtain the position data.
14. The chip packaging process according to claim 1, further comprising, before mounting the chip on the package carrier, forming the electrical conductor on the electrode pad,
after the opening processing is carried out on the packaging body, the electric conductor is exposed by the packaging body.
15. The chip packaging process according to claim 1, wherein the electrical conductors are copper balls, and the copper balls are in contact with and electrically connected to the electrode pads.
16. The chip packaging process according to claim 10, further comprising forming at least two of the positioning marks on the package carrier for determining a coordinate axis before mounting the chip on the package carrier,
the relative position of the electrode pad relative to the positioning mark is the position of the electrode pad in the coordinate axis.
17. The chip packaging process according to claim 16, wherein the positioning mark is a positioning hole or a pad of a solid circle.
18. The chip packaging process according to claim 10, wherein the step of opening the encapsulation body comprises:
positioning the electrode pad according to the position data and the positioning mark,
and opening the packaging body by using a laser beam at the position of the electrode pad so as to remove the packaging body on the electrode pad.
19. The chip packaging process according to claim 1, wherein the opening processing is performed on the encapsulant by using a laser drill, and the step of opening processing the encapsulant comprises:
and the laser drilling machine corrects a pattern to be drilled according to the position data, and drills the packaging body according to the corrected drilling pattern so as to transfer the corrected drilling pattern to the packaging body, thereby forming an opening exposing the electrode pad on the packaging body.
20. A chip package structure manufactured by the chip packaging process according to claim 1.
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CN110517961B (en) * 2019-08-21 2021-08-27 上海交通大学 Method and device for reducing position deviation of chip embedding and photoetching pattern
WO2022188859A1 (en) * 2021-03-12 2022-09-15 京东方科技集团股份有限公司 Semiconductor apparatus and manufacturing method therefor

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104347434A (en) * 2013-08-06 2015-02-11 英飞凌科技股份有限公司 Method for manufacturing a chip arrangement, and a chip arrangement
CN105143985A (en) * 2013-03-29 2015-12-09 株式会社阿迪泰克工程 Lithographic device, lithographic exposure device, recording medium having program recorded thereon, and lithographic process
CN105140191A (en) * 2015-09-17 2015-12-09 中芯长电半导体（江阴）有限公司 Packaging structure and manufacturing method for redistribution leading wire layer
CN105206539A (en) * 2015-09-01 2015-12-30 华进半导体封装先导技术研发中心有限公司 Fan-out package preparation method
CN105826247A (en) * 2016-05-05 2016-08-03 上海集成电路研发中心有限公司 Chip interconnection wiring method based on fluidic self assembly technology

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165841B2 (en) * 2008-09-19 2015-10-20 Intel Corporation System and process for fabricating semiconductor packages

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105143985A (en) * 2013-03-29 2015-12-09 株式会社阿迪泰克工程 Lithographic device, lithographic exposure device, recording medium having program recorded thereon, and lithographic process
CN104347434A (en) * 2013-08-06 2015-02-11 英飞凌科技股份有限公司 Method for manufacturing a chip arrangement, and a chip arrangement
CN105206539A (en) * 2015-09-01 2015-12-30 华进半导体封装先导技术研发中心有限公司 Fan-out package preparation method
CN105140191A (en) * 2015-09-17 2015-12-09 中芯长电半导体（江阴）有限公司 Packaging structure and manufacturing method for redistribution leading wire layer
CN105826247A (en) * 2016-05-05 2016-08-03 上海集成电路研发中心有限公司 Chip interconnection wiring method based on fluidic self assembly technology

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