CN105826247A - Chip interconnection wiring method based on fluidic self assembly technology - Google Patents
Chip interconnection wiring method based on fluidic self assembly technology Download PDFInfo
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- CN105826247A CN105826247A CN201610292920.4A CN201610292920A CN105826247A CN 105826247 A CN105826247 A CN 105826247A CN 201610292920 A CN201610292920 A CN 201610292920A CN 105826247 A CN105826247 A CN 105826247A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
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- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a chip interconnection wiring method based on a fluidic self assembly technology. After a step of installing chips on target substrates with a fluidic self assembly technology is completed, a pattern recognition method of image scanning is adopted to determine the rotation directions of the chips, so as to determine a rotation error of each chip, data related with correction positions of lead contact hole perforation and a metal wiring circuit are calculated accordingly, thereby ensuring correctness of subsequent perforation and wiring, and avoiding too many requirements for chip circuit and layout design to overcome the rotation errors generated during fluidic self assembly, special redundancy design is not needed, a packaging chip does not need to have selection symmetry in function, the difficulty of chip design is lowered, and the area of the chip is saved, thereby reducing related cost, and improving applicability of the fluidic self assembly technology.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacturing technology field, utilize current self-assembling technique to carry out the implementation method of metal interconnection between microchip more particularly, to a kind of.
Background technology
Current self-assembling technique (FluidicSelfAssembly, FSA) is the chip encapsulation technology of a kind of low cost high yield.Document " Hsi-JenJ.Yeh; JohnS.Smith; etal.FluidicSelf-AssemblyfortheIntegrationofGaAsLight-Em ittingDiodesonSiSubstrates.IEEEPHOTONICSTECHNOLOGYLETTER S; VOL.6; NO.6; RTNE1994 " and United States Patent (USP) US5549291 disclose a kind of FSA method, after a large amount of chips to be packaged are peeled off from original wafer substrate, it is suspended in solution, then flow through target substrate, and be deposited on target substrate.The feature that current self-assembling technique has low cost, yield is high, the encapsulation of the less chip of, pin less especially for area and array thereof has significant cost advantage.Meanwhile, current self-assembling technique will be also possible to apply in flexible package technology future.FSA technology is applied in the encapsulation of RFID chip by Alien company at present, and the yield of RFID is greatly improved.
Current self assembly chip lost efficacy possible for the chip installation existence of symmetric figure.There are 180 degree of rotationally symmetrical errors in such as rectangular dies, then there are 90 degree of rotation errors for square chip.Referring to Fig. 1 a-Fig. 1 b, Fig. 1 a-Fig. 1 b is to cause the explanation of wiring error in FSA encapsulation because there are 90 degree of rotation errors.Figure illustrates two chips after being arranged on substrate by FSA technology, need to be realized by later stage encapsulation wiring the interconnection of chip chamber.As shown in Figure 1a, the wire laying mode that its display is correct, respective lead pad P4 of two of which chip and lead pad P1 need to connect together respectively, and lead pad P3 of left side chip needs lead pad P2 of chip on the right of connection.As shown in Figure 1 b, owing to the right chip occurs in that 90 degree of rotation errors when being arranged on substrate, cause when follow-up wiring, occur in that a series of connection errors that lead pad P1 of left side chip is connected with lead pad P4 of the right chip, lead pad P4 of left side chip is connected with lead pad P3 of the right chip and lead pad P3 of left side chip is connected with lead pad P1 of the right chip respectively.
For overcoming this problem, usually require that rational circuit design so that chip layout possesses function symmetrical structure thus allows the rotation error of correspondence.United States Patent (USP) US6291896 (B1) discloses concrete solution, but this generally requires Redundancy Design, can bring the difficulty in design, also result in the waste of chip area simultaneously.
Summary of the invention
It is an object of the invention to the drawbacks described above overcoming prior art to exist, it is provided that a kind of chip interconnection wiring method based on current self-assembling technique, the chip redundancy design problem brought because of chip rotation error with elimination, save chip area.
For achieving the above object, technical scheme is as follows:
A kind of chip interconnection wiring method based on current self-assembling technique, comprises the following steps:
Step S01: utilize current self-assembling technique, is arranged in target substrate formation array by chip to be packaged；
Step S02: chip array is carried out image recognition scanning, determines the rotation error of each chip；
Step S03: sequentially form protecting film and dielectric layer on chip array；
Step S04: according to rotation error, calculates the tram of each chip lead contact hole, and accordingly dielectric layer and protecting film is carried out the perforate of wire contacts hole；
Step S05: carry out contact metal filling and interconnection metal layer deposit；
Step S06: according to rotation error, calculate the wiring pattern of chip array, and pattern interconnection metal layer accordingly, forms metal line.
Preferably, in step S02, by the identification labelling made in advance on chip is carried out image recognition scanning, to improve the image recognition rate to chip rotation error.
Preferably, in step S04, laser direct writing method is utilized to output wire contacts hole.
Preferably, in step S04, form the photoengraving pattern of position of opening first with laser direct writing method, then output wire contacts hole by lithographic method.
Preferably, in step S06, form wiring photoengraving pattern first with laser direct writing method, then form metal line by lithographic method.
Preferably, step S01 specifically includes: stripped down from wafer substrate by chip to be packaged, is placed in water or other solution；Target substrate is held successfully installing hole in advance；Utilize a current self assembly equipment so that a large amount of chips in the solution that suspend flow through target substrate, and automatically insert to installing hole；The circulation chip array repeatedly to guarantee that all installing holes are fitted with chip, needed for being formed.
Preferably, mechanical hand is utilized to assist the installation of chip to be packaged.
Preferably, described target substrate is made up of upper and lower double-layer structure polyimides and aluminum, and described installing hole is offered at polyimide layer.
Preferably, in step S03, target substrate uses spin-on polyimide form described protecting film, and make it surface flattening by mechanical compression mode.
Preferably, step S07 is also included: repeat step S03-step S06, to form multilayer wiring.
Can be seen that from technique scheme, the present invention by after completing to be installed on chip the step of target substrate with current self-assembling technique, the pattern recognition mode using image scanning determines the direction of rotation of chip, to determine the rotation error of each chip, and calculate the tram related data of the perforate of wire contacts hole and metal wiring lines accordingly, ensure that the correctness of follow-up perforate and wiring, the rotation error produced when avoiding as overcoming current self assembly, and to the too much requirement of chip circuit and layout design, also without special Redundancy Design, make to encapsulate the selection symmetry that chip need not possess functionally, reduce the difficulty of chip design, save chip area, thus reduce relevant cost, improve the applicability of current self-assembling technique.
Accompanying drawing explanation
Fig. 1 a-Fig. 1 b is to cause the explanation of wiring error in FSA encapsulation because there are 90 degree of rotation errors；
Fig. 2 is a kind of chip interconnection wiring method flow diagram based on current self-assembling technique of the present invention；
Fig. 3-Fig. 9 is that in a preferred embodiment of the present invention, method according to Fig. 2 carries out chip and installs the process chart of encapsulation wiring；
Figure 10-Figure 17 is the situation citing that two chip chambers interconnect when there is rotation error；
Figure 18-Figure 19 is the situation citing that head and the tail chip interconnects when there is rotation error.
Detailed description of the invention
Below in conjunction with the accompanying drawings, the detailed description of the invention of the present invention is described in further detail.
It should be noted that, in following detailed description of the invention, when describing embodiments of the present invention in detail, in order to clearly show that the structure of the present invention is so that explanation, special to the structure in accompanying drawing not according to general scale, and carried out partial enlargement, deformed and simplification process, therefore, should avoid being understood in this, as limitation of the invention.
In detailed description of the invention of the invention below, referring to Fig. 2, Fig. 2 is a kind of chip interconnection wiring method flow diagram based on current self-assembling technique of the present invention；Refer to Fig. 3-Fig. 9, Fig. 3-Fig. 9 is that in a preferred embodiment of the present invention, method according to Fig. 2 carries out chip and installs the process chart of encapsulation wiring simultaneously, and the process structure formed in Fig. 3-Fig. 9 can be corresponding with each step in Fig. 2 respectively.As in figure 2 it is shown, a kind of based on current self-assembling technique the chip interconnection wiring method of the present invention, comprise the following steps:
Step S01: utilize current self-assembling technique, is arranged in target substrate formation array by chip to be packaged.
Refer to Fig. 3-Fig. 5.When utilizing current self-assembling technique to carry out chip installation, it may include step in detail below:
1) chip is peeled off.As it is shown on figure 3, the bare chip 201-203 that first will encapsulate strips down from wafer substrate 101.The kind of wafer substrate does not limits, and can be silicon substrate, can also be the substrate such as GaAs, gallium nitride.Stripping means can be chemical etching, can also use thinning after carry out the methods such as cut.Die size is about at 50-500 micron, thus can be referred to as microchip.The chip stripped down is placed in water or other solution.
2) target substrate perforate.As shown in Figure 4, the target substrate 102 and 103 carry out chip installation holds installing hole in advance successfully.Target substrate material can use the multiple substrates such as such as silicon, aluminium sheet, RF magnetron sputtering and combinations thereof.The method of perforate can have difference for different substrates, as pressed hole mode to use chemical etching, machinery, it would however also be possible to employ laser beam drilling mode.Such as, target substrate can be constituted upper and lower double-layer structure by polyimide layer 103 and aluminium lamination 102, and installing hole is opened in polyimide layer.The shape that installing hole falls in is the most consistent with chip, it is simple to chip is installed in installing hole.The installing hole of chip can be outputed at polyimide layer by the method in heated mechanical pressure hole.
3) chip current self assembly.As it is shown in figure 5, existing current self assembly equipment can be used, by current self assembly mode, chip 201-202 is installed in the installing hole of target substrate polyimide layer 103.Making a large amount of chips suspended in the solution flow through target substrate during installation, chip will automatically insert in installing hole, the chip array needed for formation.The circulation of this process repeatedly (is typically at least flowed through target substrate twice), to guarantee that all installing holes all fill in chip.Finally mechanical hand can be used to have assisted chip to be placed into the installing hole of a small amount of non-chip that may be present.
Step S02: chip array is carried out image recognition scanning, determines the rotation error of each chip.
Refer to Fig. 6.Mounted chip array is carried out image recognition scanning, and determines the rotation error of each chip according to image.As it can be seen, in order to improve image recognition rate, identification labelling 301,302 can be produced when chip manufacture by rear road metal line technique.
Step S03: sequentially form protecting film and dielectric layer on chip array.
Refer to Fig. 7.Layer protecting film 104 can be deposited at the most mounted Chip array surface by conventional technology mode, and makes surfacing.Then redeposited one layer of dielectric layer 105.Such as, in target substrate, spin-on polyimide 104 as protecting film, and surface more smooth can be made by mechanical compression mode；Then redeposited SiO2Dielectric layer 105.
Step S04: according to rotation error, calculates the tram of each chip lead contact hole, and accordingly dielectric layer and protecting film is carried out the perforate of wire contacts hole.
Refer to Fig. 8.The rotation error drawn according to step S02, calculates the tram of perforate needed for each chip, forms the data of laser direct-writing perforate.Then according to different dielectric layer material, laser direct writing method can be used directly to output wire contacts hole；Can also first use laser direct writing method to make position of opening by lithography, i.e. form the photoengraving pattern of position of opening, then output wire contacts hole, photoresist unnecessary after then removing photoetching by lithographic method.In the present embodiment, the rotation error that chip exists has no effect on the position of opening in wire contacts hole, therefore can directly use photoetching and lithographic method to output wire contacts hole.If producing skew because chip rotates, then can accurately determine position of opening by the side-play amount calculating perforate.
Step S05: carry out contact metal filling and interconnection metal layer deposit.
Please continue to refer to Fig. 8.It follows that the various methods such as plating or sputtering can be used, filling contact hole metal and deposit wiring metal 106 in the wire contacts hole outputed.Such as, wire contacts hole can be filled up by the method deposit copper 106 of chemical plating as contact metal and wiring metal, and continuously forms interconnection metal layer.
Step S06: according to rotation error, calculate the wiring pattern of chip array, and pattern interconnection metal layer accordingly, forms metal line.
Refer to Fig. 9.The rotation error drawn by step S02, is calculated the wiring pattern of chip array, and forms laser direct-write photoetching desired data.Then form wiring photoengraving pattern by laser direct writing method, then form metal line, and photoresist unnecessary after removing photoetching by etching.
For the chip that pin is more, it is impossible to complete the situation of all chip interconnection demand in single-layer metal, it may be necessary to multilayer wiring, then may also include step S07: need to repeat above step S03-step S06, to form multilayer wiring.At this moment, the data for laser direct-writing can be different, simultaneously need to the technique using twice wiring.
The invention described above chip based on current self-assembling technique interconnection wiring method, improves the flow process of current self assembly, overcomes chip rotation error problem；After utilizing current self assembly to complete chip installation, use the direction of rotation of the method identification chip of pattern recognition, calculate the laser direct-write photoetching desired data that perforate is relevant with wiring route accordingly, and utilize laser writing technology to complete perforate and wiring, ensure that the correctness of photoetching and follow-up perforate and wiring, it is to avoid the wiring error that in the past caused because of rotation error.
The most again the data forming metal line are done one to illustrate.
Referring to Figure 10-Figure 17, Figure 10-Figure 17 is the situation citing that two chip chambers interconnect when there is rotation error.In this example, it is assumed that 4 pins (lead pad) silicon microchip is arranged in the two-level architecture target substrate that polyimides+aluminium base is constituted, and formed the array of 8 chip interconnection by metal line.As shown in Figure 10, the requirement of this microchip interconnection is that the pin P1 of adjacent two chips is connected with pin P1, pin P4 is connected with pin P4, and the outfan pin P3 of previous chip (chip on the left of diagram) is the input pin P2 of a rear chip (chip on the right side of diagram)；Simultaneously, also the chipset of 8 group is linked on the pin M1-M4 of target substrate, it is specially pin P1 to be connected with pin M1, pin P4 is connected with pin M4, the input pin P2 of first chip is connected with pin M2 and input pin M2, the outfan pin P3 of last chip as whole chipset is connected with pin M3 and as the output of whole chipset.
First, for there is the situation of various rotation error, in the present embodiment, the interconnection existence 16 kinds of any two chip chambers may, may according to these 16 kinds, can associated laser direct write layout data be pre-stored among equipment, after determined the rotation error of each microchip by scanning and image recognition, the laser direct-writing data of the interconnection wiring of each two chip chamber are also assured that, thus can obtain all data of two chip chamber interconnection wirings.That is, pass through image recognition technology, judge the rotation error of microchip, for every kind of rotation error, corresponding contact hole opening and the data of metal line can be prepared in advance by calculating, when the time comes according to the rotation error of each chip, select corresponding data, eventually form laser direct-writing desired data.Figure 10-Figure 17 only illustrates and gives the possible case of wherein 8 kinds of rotation errors, and the interconnection wiring mode of correspondence；It is previous chip 4 kinds of situations there is not rotation error the most respectively, and previous chip exists 4 kinds of situations of 90 degree of rotation errors.Additionally, the situation that previous chip exists 180 degree and 270 degree rotation errors can in like manner provide (this example is slightly).
Secondly because be 8 chips one group during final encapsulation, two chips need to be connected with the pin in target substrate from beginning to end.It practice, what the pin M1-M4 in target substrate was also adopted by is wiring metal, they are fixing in the position of target substrate.The so corresponding head and the tail pin of chip respectively exists 4 kinds with the connection mode of target substrate pin may.Figure 18-Figure 19 citing gives the possible wire laying mode of one that head and the tail two chips exist rotation error, and its associated laser direct write layout data can be pre-stored among equipment.Determined the rotation error of head and the tail chip by scanning and image recognition after, then the laser lithography data of the metal connecting line between head and the tail two chips and target substrate pin can also determine.
Laser direct-write photoetching data needed for the chip interconnection that just can obtain the chip package form of 8 chip one group eventually through said method and the wiring being connected with target substrate pin.Scanning target complete substrate then can obtain the total data of this laser direct-write photoetching.
In sum, the present invention by after completing to be installed on chip the step of target substrate with current self-assembling technique, the pattern recognition mode using image scanning determines the direction of rotation of chip, to determine the rotation error of each chip, and calculate the tram related data of the perforate of wire contacts hole and metal wiring lines accordingly, ensure that the correctness of follow-up perforate and wiring, the rotation error produced when avoiding as overcoming current self assembly, and to the too much requirement of chip circuit and layout design, also without special Redundancy Design, make to encapsulate the selection symmetry that chip need not possess functionally, reduce the difficulty of chip design, save chip area, thus reduce relevant cost, improve the applicability of current self-assembling technique.
Above-described only the preferred embodiments of the present invention; described embodiment is also not used to limit the scope of patent protection of the present invention; the equivalent structure change that the description of the most every utilization present invention and accompanying drawing content are made, in like manner should be included in protection scope of the present invention.
Claims (10)
1. a chip interconnection wiring method based on current self-assembling technique, it is characterised in that comprise the following steps:
Step S01: utilize current self-assembling technique, is arranged in target substrate formation array by chip to be packaged；
Step S02: chip array is carried out image recognition scanning, determines the rotation error of each chip；
Step S03: sequentially form protecting film and dielectric layer on chip array；
Step S04: according to rotation error, calculates the tram of each chip lead contact hole, and accordingly dielectric layer and protecting film is carried out the perforate of wire contacts hole；
Step S05: carry out contact metal filling and interconnection metal layer deposit；
Step S06: according to rotation error, calculate the wiring pattern of chip array, and pattern interconnection metal layer accordingly, forms metal line.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that in step S02, by carrying out image recognition scanning to the identification labelling made in advance on chip, to improve the image recognition rate to chip rotation error.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that in step S04, utilize laser direct writing method to output wire contacts hole.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that in step S04, forms the photoengraving pattern of position of opening, then outputs wire contacts hole by lithographic method first with laser direct writing method.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that in step S06, forms wiring photoengraving pattern first with laser direct writing method, then forms metal line by lithographic method.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that step S01 specifically includes: stripped down from wafer substrate by chip to be packaged, is placed in water or other solution；Target substrate is held successfully installing hole in advance；Utilize a current self assembly equipment so that a large amount of chips in the solution that suspend flow through target substrate, and automatically insert to installing hole；The circulation chip array repeatedly to guarantee that all installing holes are fitted with chip, needed for being formed.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 6, it is characterised in that utilize mechanical hand to assist the installation of chip to be packaged.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 6, it is characterised in that described target substrate is made up of upper and lower double-layer structure polyimides and aluminum, and described installing hole is offered at polyimide layer.
Chip interconnection wiring method based on current self-assembling technique the most according to claim 1, it is characterised in that in step S03, uses spin-on polyimide to form described protecting film in target substrate, and makes it surface flattening by mechanical compression mode.
10. according to the chip interconnection wiring method based on current self-assembling technique described in claim 1-9 any one, it is characterised in that also include step S07: repeat step S03-step S06, to form multilayer wiring.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601634A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
| CN106601635A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging process and chip packaging structure |
| CN110349865A (en) * | 2018-04-04 | 2019-10-18 | 上海瑞章物联网技术有限公司 | The packaging method of chip |
| CN110517961A (en) * | 2019-08-21 | 2019-11-29 | 上海交通大学 | Reduce the embedding method and device with litho pattern position deviation of chip |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291896B1 (en) * | 1999-02-16 | 2001-09-18 | Alien Technology Corporation | Functionally symmetric integrated circuit die |
| CN1485884A (en) * | 2002-09-27 | 2004-03-31 | ���µ�����ҵ��ʽ���� | Method for fabricating semiconductor device |
| CN101083222A (en) * | 2006-05-31 | 2007-12-05 | 财团法人工业技术研究院 | Apparatus for positioning microcomponent to the substrate and method therefor |
| US20110300668A1 (en) * | 2010-06-02 | 2011-12-08 | Maxim Integrated Products, Inc. | Use of device assembly for a generalization of three-dimensional metal interconnect technologies |
-
2016
- 2016-05-05 CN CN201610292920.4A patent/CN105826247B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6291896B1 (en) * | 1999-02-16 | 2001-09-18 | Alien Technology Corporation | Functionally symmetric integrated circuit die |
| CN1485884A (en) * | 2002-09-27 | 2004-03-31 | ���µ�����ҵ��ʽ���� | Method for fabricating semiconductor device |
| CN101083222A (en) * | 2006-05-31 | 2007-12-05 | 财团法人工业技术研究院 | Apparatus for positioning microcomponent to the substrate and method therefor |
| US20110300668A1 (en) * | 2010-06-02 | 2011-12-08 | Maxim Integrated Products, Inc. | Use of device assembly for a generalization of three-dimensional metal interconnect technologies |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106601634A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
| CN106601635A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging process and chip packaging structure |
| CN106601635B (en) * | 2016-08-25 | 2019-07-09 | 合肥祖安投资合伙企业(有限合伙) | Chip package process and chip-packaging structure |
| CN106601634B (en) * | 2016-08-25 | 2021-04-02 | 合肥祖安投资合伙企业(有限合伙) | Chip packaging process and chip packaging structure |
| CN110349865A (en) * | 2018-04-04 | 2019-10-18 | 上海瑞章物联网技术有限公司 | The packaging method of chip |
| CN110517961A (en) * | 2019-08-21 | 2019-11-29 | 上海交通大学 | Reduce the embedding method and device with litho pattern position deviation of chip |
| CN110517961B (en) * | 2019-08-21 | 2021-08-27 | 上海交通大学 | Method and device for reducing position deviation of chip embedding and photoetching pattern |
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| Publication number | Publication date |
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| CN105826247B (en) | 2018-11-09 |
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