CN110517961A - Reduce the embedding method and device with litho pattern position deviation of chip - Google Patents
Reduce the embedding method and device with litho pattern position deviation of chip Download PDFInfo
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- CN110517961A CN110517961A CN201910776078.5A CN201910776078A CN110517961A CN 110517961 A CN110517961 A CN 110517961A CN 201910776078 A CN201910776078 A CN 201910776078A CN 110517961 A CN110517961 A CN 110517961A
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- 238000000034 method Methods 0.000 title claims abstract description 33
- 238000005259 measurement Methods 0.000 claims abstract description 22
- 238000001259 photo etching Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000011161 development Methods 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 230000009467 reduction Effects 0.000 claims description 4
- 230000003287 optical effect Effects 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 238000012545 processing Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000004026 adhesive bonding Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000011536 re-plating Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The present invention reduces the embedding method and device with litho pattern position deviation of chip, includes the following steps: step 1, buries chip on substrate；Step 2, the measurement data of chip is obtained；Step 3, the mask edition territory of upper layer pattern is drawn using measurement data；Step 4, layer pattern is obtained.Compared with prior art, the present invention is with following the utility model has the advantages that after embedding chip, use precise observations equipment, measure size and the relative position of chip and its pin, it reuses measurement data or picture draws photoresist mask, the error embedding because of chip is solved, chip pin and the photoetching offset plate figure on its upper layer is caused to generate deviation, so as to cause the problem of component short circuit or open circuit；The increased processing step of institute of the invention is simple, greatly improves the heterogeneous integrated packaging technology of wafer scale.
Description
Technical field
The present invention relates to the three-dimensional heterogeneous integrated technique of wafer scale, especially a kind of reductions chip is embedding and litho pattern position
The method and device of deviation.
Background technique
The three-dimensional heterogeneous integrated technique of wafer scale is packaged chip and passive device directly on wafer and is routed again, can
Directly to utilize semiconductor manufacturing equipment, disposably integrate an even more chips up to a hundred, be greatly improved packaging efficiency,
It reduces costs, is the important way for realizing system in package.Wafer-level packaging generallys use embedding mode and encapsulates chip, envelope
The basic structure that dress uses is metal-dielectric-metal, as shown in Figure 1, etching SiO first2Film 101 opens a window, and is to cover with windowing
Film etches chip cavity in silicon-based substrate 102, and re-plating metal ground layer 103 applies a small amount of conductive silver paste 104 for fixing
And conduction, chip 105 and 106 is embedded into chip cavity.In view of inherently there is several microns of mismachining tolerance in chip,
And chip cavity is etched according to wet process mode, cavity wall has 54.74 ° of inclination angle, and chip is caused not fix effectively, embedding
Chip is difficult to be placed exactly in the center of chip cavity；It is etched according to dry method mode, although inclination angle is very big, is bound to stay certain
Surplus avoids chip from embedding can not entering, and is equipped with certain error compared with its ideal bit when this also results in embedding chip.If need to be
Encapsulation simultaneously generates certain deviation to different directions, finally amplifies this error, such as compared with multi-chip, each chip on one piece of wafer
Chip 105 is located at chip cavity compared with left side, and chip 106 is located at chip cavity compared with right side, such as traditionally first draws system
One mask, then carry out embedding chip and subsequent gluing, photoetching, development, then will lead to segment chip pin with thereon
The figures such as through-hole can not accurate alignment, or even occur leading to open circuit to upper figure or touch wrong figure do not cause it is short
Road.As chip 105 pin 107 and 108 and chip 106 pin 109 and 110 with and its dielectric layer 111 through-hole and
Cabling on metal layer 112 has a degree of offset, if offset adds up, rear larger and chip pin is leaned on close, may
Cause through-hole and cabling on script pin 108 not to contact completely with pin 108, leads to open circuit；Or it is located on pin 112 originally
Through-hole and cabling contacted with pin 111, cause short circuit.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide a kind of reduction chips for solving above-mentioned technical problem
The embedding method and device with litho pattern position deviation.
In order to solve the above-mentioned technical problem, the present invention reduces the embedding method with litho pattern position deviation of chip, including
Following steps:
Step 1, chip is buried on substrate；
Step 2, the measurement data of chip is obtained；
Step 3, the mask edition territory of upper layer pattern is drawn using measurement data；
Step 4, layer pattern is obtained.
Preferably, step 1 includes:
Step 1.1, chip slot is opened up in silicon substrate；
Step 1.2, chip is buried in chip slot.
Preferably, shielded layer containing metal ground layer is equipped in chip slot.
Preferably, in step 2, the measurement data of chip is obtained using observation device.
Preferably, measurement data includes size and the position of chip and pin.
Preferably, observation device is optical three-dimensional microscope.
Preferably, in step 3, using measurement data calculate or directly measurement picture on described point mode, draw upper layer
The mask edition territory of figure.
Preferably, step 4 includes:
Step 4.1, spin coating photoetching；
Step 4.2, photoetching development obtains layer pattern.
A kind of device, device are prepared by the embedding method with litho pattern position deviation of reduction chip.
Compared with prior art, the present invention is set with following the utility model has the advantages that after embedding chip using precise observations
It is standby, size and the relative position of chip and its pin are measured, measurement data is reused or picture draws photoresist mask, solve
Because of the embedding error of chip, chip pin and the photoetching offset plate figure on its upper layer is caused to generate deviation, so as to cause component short circuit or
The problem of open circuit；The increased processing step of institute of the invention is simple, greatly improves the heterogeneous integrated packaging technology of wafer scale.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon.
Fig. 1 is using the technique improved without the method for the present invention, the basic structure of made wafer scale MCM package；
Fig. 2 is the technique improved using the method for the present invention, the basic structure of made wafer scale MCM package；
Fig. 3 is the technical process figure of this patent improvement part.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
As shown in Figure 2 and Figure 3, often it is slightly larger than chip size for chip cavity, embedding chip is difficult to be placed exactly in core
The center of piece cavity, cause segment chip pin and figures such as through-hole thereon can not accurate alignment, or even occur not to upper figure
Shape leads to open circuit or touches the figure of mistake to lead to the problem of short circuit, and the present invention proposes after embedding chip, uses accurate see
Measurement equipment measures size and the relative position of chip and its pin, reuses measurement data or picture draws photoresist mask,
The photoetching development that layer pattern on chip is carried out with this mask, effectively reduces the error of chip and its pin and upper layer pattern.
Specific process step are as follows:
(1) the embedding chip in the chip slot of the shielded layer containing metal ground layer, this step are slightly larger than chip, chip due to chip slot
It is difficult to be embedded in chip slot center, every piece of chip and chip slot is caused to have certain unpredictable error；
(2) use but be not limited to the precise observations equipment of optical three-dimensional microscope, measure chip and its pin size and
The position of opposite chip slot, this step come out the error measure that every piece of chip introduces when embedding；
(3) calculated using measurement data or directly on measurement picture described point mode, the mask of layer pattern in drafting,
Since the mask of drafting is all the customized version to embedding chip, therefore the embedding caused error of chip can be eliminated；
(4) gluing carries out photoetching development using the mask of drafting, obtains layer pattern, carry out subsequent technique later；
In conclusion the present invention is characterized in that, using precise observations equipment, measuring chip after embedding chip and its drawing
The size of foot and relative position, reuse measurement data or picture draws photoresist mask, solve the error embedding because of chip,
Chip pin and the photoetching offset plate figure on its upper layer is caused to generate deviation, so as to cause the problem of component short circuit or open circuit；The present invention
The increased processing step of institute is simple, greatly improves the heterogeneous integrated packaging technology of wafer scale.
Although there are still chips 205 to be located at chip cavity compared with left side, chip 206 is located at the case where chip cavity is compared with right side,
After being embedding chip due to the mask plate of upper layer pattern, reuses precision instrument and observe obtaining data and picture, and drawn with this
, therefore chip only exists the error of minimum measurement error and photoetching process, far smaller than chip pin with layer pattern thereon
Size, also avoid that traditional method is likely to occur can not accurate alignment the problem of leading to short interruption, such as chip 205
The pin (209,210) of pin (207,208) and chip 206 with and its through-hole and metal layer 212 of dielectric layer 211 on
Cabling be aligned completely.Method proposed by the present invention further improves the yield rate and volume production of the heterogeneous integrated technique of wafer scale
Rate.
Embodiment
(a) using 3 cun of 500 μ m-thick of high resistant circle silicon wafer as substrate 202, SiO is etched2Film 201 opens a window, and makes chip slot
With plating metal stratum 203, a small amount of conductive silver paste 204 is applied for fixed and conductive, and embedding chip (205,206), it is all
Chip and silicon chip surface are substantially flush, as shown in Fig. 3 (a)；
(b) visible light three-dimensional microscope is used, the picture of all embedding chips is shot under 20 times of amplifications, by shooting
Picture imports AutoCAD mapping software, describes chip and its pin after proportionally reducing, and be with the chip slot of each chip
Each embedding chip and its pin are plotted on the mask of whole wafer by benchmark, draw layer pattern on chip later
The mask of medium through hole mask and metal layer routes and passive device；
(c) photoresist is applied, as shown in Fig. 3 (b), and medium through hole mask photoetching development is used, is generated on chip
Dielectric layer comprising via hole image, since dielectric layer mask is that described point is drawn, therefore through-hole can accurately be opened in chip pin
Top, as shown in Fig. 3 (c)；
(d) sputtering seed layer Cr/Cu, and metal layer mask version photoetching development is used, later by being electroplated and going seed
Layer process generates the metal layer comprising wiring and passive device on dielectric layer, since metal layer mask version is also that described point is drawn
, therefore metal wire and passive device can accurately be connect with chip pin, as shown in Fig. 3 (d).
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (9)
1. a kind of reduce the embedding method with litho pattern position deviation of chip, which comprises the steps of:
Step 1, chip is buried on substrate；
Step 2, the measurement data of chip is obtained；
Step 3, the mask edition territory of upper layer pattern is drawn using measurement data；
Step 4, layer pattern is obtained.
2. according to claim 1 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that step
1 includes:
Step 1.1, chip slot is opened up in silicon substrate；
Step 1.2, chip is buried in chip slot.
3. according to claim 2 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that in core
Shielded layer containing metal ground layer is equipped in film trap.
4. according to claim 1 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that step
In 2, the measurement data of chip is obtained using observation device.
5. according to claim 1 or 4 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that
Measurement data includes size and the position of chip and pin.
6. according to claim 4 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that observation
Equipment is optical three-dimensional microscope.
7. according to claim 1 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that step
In 3, calculated using measurement data or directly on measurement picture described point mode, the lay photoetching mask plate version of layer pattern in drafting
Figure.
8. according to claim 1 reduce the embedding method with litho pattern position deviation of chip, which is characterized in that step
4 include:
Step 4.1, spin coating photoetching；
Step 4.2, photoetching development obtains layer pattern.
9. a kind of device, which is characterized in that device reduction chip as described in claim 1 to 8 any one claim buries
It sets and is prepared with the method for litho pattern position deviation.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910776078.5A CN110517961B (en) | 2019-08-21 | 2019-08-21 | Method and device for reducing position deviation of chip embedding and photoetching pattern |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910776078.5A CN110517961B (en) | 2019-08-21 | 2019-08-21 | Method and device for reducing position deviation of chip embedding and photoetching pattern |
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| Publication Number | Publication Date |
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| CN110517961A true CN110517961A (en) | 2019-11-29 |
| CN110517961B CN110517961B (en) | 2021-08-27 |
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| CN201910776078.5A Active CN110517961B (en) | 2019-08-21 | 2019-08-21 | Method and device for reducing position deviation of chip embedding and photoetching pattern |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613539A (en) * | 2020-05-22 | 2020-09-01 | 上海交通大学 | Multilayer preparation method and system of wafer-level three-dimensional heterogeneous integrated device |
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| CN106601634A (en) * | 2016-08-25 | 2017-04-26 | 合肥祖安投资合伙企业(有限合伙) | Chip package technology and chip package structure |
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2019
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| US20090236703A1 (en) * | 2008-03-20 | 2009-09-24 | Geng-Shin Shen | Chip package structure and the method thereof |
| US20140106507A1 (en) * | 2008-09-19 | 2014-04-17 | Intel Mobile Communications GmbH | System and process for fabricating semiconductor packages |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111613539A (en) * | 2020-05-22 | 2020-09-01 | 上海交通大学 | Multilayer preparation method and system of wafer-level three-dimensional heterogeneous integrated device |
| CN111613539B (en) * | 2020-05-22 | 2024-02-06 | 上海交通大学 | Multilayer preparation method and system of wafer-level three-dimensional heterogeneous integrated device |
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| Publication number | Publication date |
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| CN110517961B (en) | 2021-08-27 |
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