CN109378294A - The packaging method of semiconductor structure - Google Patents
The packaging method of semiconductor structure Download PDFInfo
- Publication number
- CN109378294A CN109378294A CN201811166761.9A CN201811166761A CN109378294A CN 109378294 A CN109378294 A CN 109378294A CN 201811166761 A CN201811166761 A CN 201811166761A CN 109378294 A CN109378294 A CN 109378294A
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- China
- Prior art keywords
- semiconductor structure
- plastic
- film
- chip
- circuit layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
The present invention provides a kind of packaging method of semiconductor structure, replaces conductive glue slice to paste with the wafer using extensible film before wafer cutting, after wafer cutting, the extensible film is not cut off, and stretches the extensible film, and multiple chips can be made to be separated from each other, it is easy to operate and at low cost.
Description
Technical field
The present invention relates to field of semiconductor package more particularly to a kind of packaging methods of semiconductor structure.
Background technique
Semiconductor packages generally comprises three step process of semiconductor chip manufacturing process, Electrical Test Procedure and encapsulation process
Manufacture.Semiconductor chip manufacturing process generates the chip for constituting such as device of transistor, register and capacitor.The electrical testing
Process electric power testing semiconductor piece and each chip is divided into excellent or undesirable semiconductor chip.The encapsulation process is protected
Fragile semiconductor chip is protected not by external aggression and/or vibration.Semiconductor packages including semiconductor devices has also been employed that
In the device of such as personal computer, television receiver, consumer appliances and information communication machine.
The step of conventional method for packaging semiconductor is at present: (1) planting metal ball or plating metal column in crystal column surface；
(2) wafer cuts to form single chip；(3) in substrate surface point or the non-conductive glue of spray；(4) single chip is attached to and put glue
On substrate；(5) encapsulating and cloth circuits are carried out.The disadvantages of this method is, in substrate surface point or the non-conductive glue of spray, is packaged into
Originally it greatly improves, and is unfavorable for environmental protection.
Summary of the invention
It is easy to operate the technical problem to be solved by the invention is to provide a kind of packaging method of semiconductor structure, and
Save the cost.
To solve the above-mentioned problems, the present invention provides a kind of packaging method of semiconductor structure, include the following steps: to mention
For a wafer, the wafer includes the front and the back side being oppositely arranged, and the front is active face；It is set at the back side of the wafer
Set an extensible film；Cut the wafer, by the wafer be divided into it is multiple be arranged in the extensible film each other solely
Vertical chip；The extensible film is stretched, so that multiple chips are separated to a preset distance；One carrier, the load are provided
Body is connect with the front of all chips；Remove the extensible film；Encapsulation forms semiconductor structure.
In one embodiment, the carrier is selected from one of pyrolysis film, UV film or baltimore groove.
In one embodiment, the extensible film is selected from polyethylene film, pyrolysis one of film or UV film.
In one embodiment, after stretching the extensible film, on the carrier by chip back-off.
In one embodiment, after the step of removing the extensible film, further include the steps that a position is scanned.
In one embodiment, the encapsulation includes the following steps: chip described in plastic packaging, forms the first plastic-sealed body；Removal institute
Carrier is stated, the front of the chip is exposed；At least one metal salient point is formed in the front of each chip；Described in plastic packaging
The front of chip forms the second plastic-sealed body, and the one side exposure for connecting the metal salient point with the front of the chip
Except second plastic-sealed body；A circuit layer is formed on second plastic-sealed body surface；It is formed in the circuit layer surface more
A outer pin, the outer pin are connect by the circuit layer with the metal salient point.
In one embodiment, the method for forming the circuit layer includes the following steps: in second plastic-sealed body surface shape
Layer is rerouted at least one；Reroute layer described in plastic packaging, form the circuit layer, the circuit layer not with second plastic packaging
The one side of body connection, the weld pad of the circuit layer are exposed.
In one embodiment, the outer pin is formed on the weld pad of the circuit layer.
It in one embodiment, further include a cutting step after the step of forming the outer pin.
It is an advantage of the current invention that replace conducting resinl to paste with the wafer using extensible film before wafer cutting,
After wafer cutting, the extensible film is not cut off, and stretches the extensible film, and multiple chips can be made to be separated from each other, and is operated
Simply, and the price of the extensible film be only conducting resinl price 1/50~1/10, greatly reduce cost.
Detailed description of the invention
Fig. 1 is the step schematic diagram of the packaging method of semiconductor structure of the present invention；
Fig. 2A~Fig. 2 G is the process flow chart of the packaging method of semiconductor structure of the present invention；
Fig. 3 A~Fig. 3 G is the process flow chart of an embodiment of the method for the encapsulation step.
Specific embodiment
The specific embodiment of the packaging method of semiconductor structure provided by the invention is done specifically with reference to the accompanying drawing
It is bright.
Fig. 1 is the step schematic diagram of the packaging method of semiconductor structure of the present invention.Referring to Fig. 1, semiconductor junction of the present invention
The packaging method of structure includes the following steps: step S10, provides a wafer, and the wafer includes the front and the back side being oppositely arranged,
The front is active face；Step S11, one extensible film is set at the back side of the wafer；Step S12, the wafer is cut,
The wafer is divided into multiple chips independent of each other being arranged in the extensible film；It step S13, can described in stretching
Tensile membrane, so that multiple chips are separated to a preset distance；Step S14, provide a carrier, the carrier with it is all described
The front connection of chip；Step S15, the extensible film is removed；Step S16, it encapsulates, forms semiconductor structure.
Fig. 2A~Fig. 2 G is the process flow chart of the packaging method of semiconductor structure of the present invention.
Please refer to step S10 and Fig. 2A, a wafer 200 be provided, the wafer 200 include the front 201 being oppositely arranged and
The back side 202.Described positive 201 be active face.The active face refers to that the wafer 200 is provided with the one side of the weld pad of circuit,
Circuit welding pad needs are electrically connected with external structure, and then the chip is electrically connected with external structure.
Step S11 and Fig. 2 B is please referred to, an extensible film 210 is set at the back side 202 of the wafer 200.It is described to prolong
Exhibition film 210 refers to the film layer structure that can extend under the effect of external force.For example, the extensible film includes but is not limited to poly- second
Alkene film (PO film), pyrolysis film or UV film.Wherein, 210 surface of extensible film has viscosity, can be adhered directly to the wafer
The back side 202.
Step S12 and Fig. 2 C is please referred to, the wafer 200 is cut, the wafer 200 is divided into multiple be arranged in institute
State the chip independent of each other 220 in extensible film 210.Specifically, can be used described in the method cutting of laser or machinery
Wafer 200, wherein the extensible film 210 is not cut, and structure is still integral.In this step, the chip
220 independently of one another, but connect with the extensible film 210.
Step S13 and Fig. 2 D is please referred to, the extensible film 210 is stretched, so that multiple chips 220 are separated to one in advance
Set a distance.Specifically, 210 stress of extensible film extends using extensible film 210 described in force-extension.It is described can
After 210 stress of tensile membrane extends, the multiple chips 220 being connect with the extensible film 210 each other natural separation to a pre- spacing
From.The preset distance can be determined according to the performance of the extensible film 210, can also encapsulate needs according to subsequent chip 220
And it determines.
Step S14 and Fig. 2 E is please referred to, a carrier 230, the front of the carrier 230 and all chips 220 are provided
201 connections.The carrier 230 is selected from one of pyrolysis film, UV film or baltimore groove, plays the role of support.Wherein, at this
In embodiment, chip 220 is tipped upside down on into institute by method that the carrier 230 is connect with the front 201 of all chips 220
It states on carrier 230.
Step S15 and Fig. 2 F is please referred to, the extensible film 210 is removed.It in this step, can be according to the extensible film
210 characteristic is removed using different methods, such as mechanical stripping, laser lift-off or chemical stripping etc..
Further, after the step of removing extensible film 210, further include the steps that a position is scanned, in the step
In rapid, the confirmation of chip position coordinate and record are carried out by laser scanning, in order to determine circuit configuration in later process
When, by importing the chip position of laser scanning, circuit position arrangement is carried out, is existing processing step, repeats no more.
Step S16 and Fig. 2 G is please referred to, is encapsulated, semiconductor structure is formed.Wherein, ability can be used in the method for the encapsulation
The packaging method of domain routine.
Fig. 3 A~Fig. 3 G is the process flow chart of an embodiment of the method for the encapsulation.In the present embodiment, the envelope
The method of dress includes the following steps:
Fig. 3 A is please referred to, chip 220 described in plastic packaging forms the first plastic-sealed body 300.Specifically, in this step, can adopt
The method for being coated or being laminated with plastic packaging material forms first plastic-sealed body 300.First plastic-sealed body 300 coats the chip
220 back side 202 and side.Since the front 201 of the chip 220 is blocked by the carrier 230, so the chip 220
Front 201 do not coated by first plastic-sealed body 300.
Fig. 3 B is please referred to, the carrier 230 is removed, exposes the front 201 of the chip 220.Specifically, can be used
The methods of mechanical stripping, the laser lift-off or stripper removing removal carrier 230.After removing the carrier 230, the core
The front 201 of piece 220 is exposed.
Fig. 3 C is please referred to, forms at least one metal salient point 240 in the front 201 of each chip 220.In this implementation
In example, four metal salient points 240 schematically are formed in the front of each chip 220.The metal salient point 240 and the chip
The weld pad in 220 front 201 connects, and the circuit of the chip 220 is connect by the metal salient point 240 with external structure.Its
In, the method for forming the metal salient point 240 includes but is not limited to mask method.
Fig. 3 D is please referred to, the front of chip 220 described in plastic packaging forms one second plastic-sealed body 250, and makes the metal salient point
240 do not connect with the front 201 of the chip 220 be exposed to except second plastic-sealed body 250 on one side.In the step
In, the method that plastic packaging material cladding or lamination can be used forms second plastic-sealed body 250.Wherein, make the metal salient point 240
The method being exposed to except second plastic-sealed body 250 on one side not connecting with the front of the chip 220 can be to be formed
After second plastic-sealed body 250, second plastic-sealed body 250 is ground or in the corresponding position of the metal salient point 240 to described the
Two plastic-sealed bodies drill, to expose the metal salient point 240.
Fig. 3 E is please referred to, forms a circuit layer 260 on 250 surface of the second plastic-sealed body.The effect of the circuit layer 260
It is to be fanned out to the chip 220, in order to the connection of the chip 220 and external structure.Wherein, the circuit layer 260 is formed
Method include but is not limited to, 250 surface of the second plastic-sealed body formed at least one reroute layer, for example, in the present embodiment
In, two layers of rewiring layer 261 is formed on 250 surface of the second plastic-sealed body；Layer 261 is rerouted described in plastic packaging, forms the electricity
Road floor 260.It is (attached in the weld pad of the one side that the circuit layer 260 is not connect with second plastic-sealed body 250, the circuit layer 260
It is not painted in figure) it is exposed.The weld pad of the circuit layer 260 can be used as the outer pin connecting with the external world.
If not needing then to independently form outer pin using the weld pad of the circuit layer 260 as outer pin.Please refer to figure
3F forms multiple outer pins 270 on 260 surface of circuit layer, the outer pin 270 by the circuit layer 260 with it is described
Metal salient point 240 connects.The outer pin 270 is formed on the weld pad of the circuit layer 260.The outer pin 270 can pass through
It plants ball or metal cladding and is formed.In the present embodiment, ball is planted on the weld pad of the circuit layer 260 form the outer pin
270.The chip 220 passes sequentially through metal salient point 240, circuit layer 260 and outer pin 270 and connect with external structure.It is described outer
Portion's structure includes but is not limited to printed circuit board.
It further, further include a cutting step after the step of forming outer pin 270.Fig. 3 G is please referred to, is used
The methods of laser or machine cuts cut the encapsulating structure, form multiple encapsulating structures 400 independent of each other, each encapsulation knot
Structure 400 includes at least one chip 220.
The packaging method of semiconductor structure of the present invention replaces conductive glue slice and institute using extensible film before wafer cutting
Wafer is stated to paste, wafer cutting after, the extensible film is not cut off, and stretches the extensible film, can make multiple chips that
This is separated, easy to operate and at low cost.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
Member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications also should be regarded as
Protection scope of the present invention.
Claims (9)
1. a kind of packaging method of semiconductor structure, which comprises the steps of:
A wafer is provided, the wafer includes the front and the back side being oppositely arranged, and the front is active face；
At the back side of the wafer, one extensible film is set；
The wafer is cut, the wafer is divided into multiple chips independent of each other being arranged in the extensible film；
The extensible film is stretched, so that multiple chips are separated to a preset distance；
A carrier is provided, the carrier is connect with the front of all chips；
Remove the extensible film；
Encapsulation forms semiconductor structure.
2. the packaging method of semiconductor structure according to claim 1, which is characterized in that the carrier be selected from pyrolysis film,
One of UV film or baltimore groove.
3. the packaging method of semiconductor structure according to claim 1, which is characterized in that the extensible film is selected from poly-
Vinyl film, pyrolysis one of film or UV film.
4. the packaging method of semiconductor structure according to claim 1, which is characterized in that after stretching the extensible film,
On the carrier by chip back-off.
5. the packaging method of semiconductor structure according to claim 1, which is characterized in that removing the extensible film
After step, further include the steps that a position is scanned.
6. the packaging method of semiconductor structure according to claim 1, which is characterized in that the encapsulation includes following step
Rapid: chip described in plastic packaging forms the first plastic-sealed body；
The carrier is removed, the front of the chip is exposed；
At least one metal salient point is formed in the front of each chip；
The front of chip described in plastic packaging forms the second plastic-sealed body, and connect the metal salient point with the front of the chip
Be exposed to except second plastic-sealed body on one side；
A circuit layer is formed on second plastic-sealed body surface；
Multiple outer pins are formed in the circuit layer surface, the outer pin is connected by the circuit layer and the metal salient point
It connects.
7. the packaging method of semiconductor structure according to claim 6, which is characterized in that the method for forming the circuit layer
Include the following steps:
At least one, which is formed, on second plastic-sealed body surface reroutes layer；
Layer is rerouted described in plastic packaging, forms the circuit layer, in the one side that the circuit layer is not connect with second plastic-sealed body,
The weld pad of the circuit layer is exposed.
8. the packaging method of semiconductor structure according to claim 7, which is characterized in that on the weld pad of the circuit layer
Form the outer pin.
9. the packaging method of semiconductor structure according to claim 6, which is characterized in that in the step for forming the outer pin
It further include a cutting step after rapid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811166761.9A CN109378294A (en) | 2018-10-08 | 2018-10-08 | The packaging method of semiconductor structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811166761.9A CN109378294A (en) | 2018-10-08 | 2018-10-08 | The packaging method of semiconductor structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109378294A true CN109378294A (en) | 2019-02-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811166761.9A Pending CN109378294A (en) | 2018-10-08 | 2018-10-08 | The packaging method of semiconductor structure |
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| Country | Link |
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| CN (1) | CN109378294A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110783327A (en) * | 2019-10-24 | 2020-02-11 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| CN113571461A (en) * | 2021-07-02 | 2021-10-29 | 矽磐微电子(重庆)有限公司 | Method for forming chip packaging structure |
| CN113770557A (en) * | 2021-10-22 | 2021-12-10 | 无锡韦感半导体有限公司 | Method for removing static electricity of laser cutting wafer |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582639A (en) * | 1991-09-19 | 1993-04-02 | Nec Kansai Ltd | Ultraviolet ray hardening-type adhesive sheet |
| CN1731560A (en) * | 2004-08-05 | 2006-02-08 | 株式会社迪斯科 | Method and apparatus for dividing an adhesive film mounted on a wafer |
| CN207353224U (en) * | 2017-07-06 | 2018-05-11 | Eo科技股份有限公司 | Wafer processing apparatus |
| CN108321113A (en) * | 2018-01-29 | 2018-07-24 | 合肥矽迈微电子科技有限公司 | Fan-out package method |
-
2018
- 2018-10-08 CN CN201811166761.9A patent/CN109378294A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0582639A (en) * | 1991-09-19 | 1993-04-02 | Nec Kansai Ltd | Ultraviolet ray hardening-type adhesive sheet |
| CN1731560A (en) * | 2004-08-05 | 2006-02-08 | 株式会社迪斯科 | Method and apparatus for dividing an adhesive film mounted on a wafer |
| CN207353224U (en) * | 2017-07-06 | 2018-05-11 | Eo科技股份有限公司 | Wafer processing apparatus |
| CN108321113A (en) * | 2018-01-29 | 2018-07-24 | 合肥矽迈微电子科技有限公司 | Fan-out package method |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110783327A (en) * | 2019-10-24 | 2020-02-11 | 中芯集成电路（宁波）有限公司 | Wafer level system packaging method and packaging structure |
| CN113571461A (en) * | 2021-07-02 | 2021-10-29 | 矽磐微电子(重庆)有限公司 | Method for forming chip packaging structure |
| CN113770557A (en) * | 2021-10-22 | 2021-12-10 | 无锡韦感半导体有限公司 | Method for removing static electricity of laser cutting wafer |
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Application publication date: 20190222 |
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