CN107845600A - A kind of bonded wafer level packaging structure and its technological process - Google Patents

A kind of bonded wafer level packaging structure and its technological process Download PDF

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Publication number
CN107845600A
CN107845600A CN201710946381.6A CN201710946381A CN107845600A CN 107845600 A CN107845600 A CN 107845600A CN 201710946381 A CN201710946381 A CN 201710946381A CN 107845600 A CN107845600 A CN 107845600A
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base material
bonding wire
pad
layer
chip
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CN107845600B (en
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马军
刘鹏
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Taiji Semiconductor (suzhou) Co Ltd
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Taiji Semiconductor (suzhou) Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Micromachines (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention discloses a kind of bonded wafer level packaging structure for being combined silicon support plate technology with traditional wire soldering technology and its technological process, by advanced silicon support plate technology, the technology for applying of chip and wafer, with reference to traditional bonding wire interconnection technique, it can effectively integrate and utilize existing factory resources, such as WB bonding wires board, while ensureing the package application of secret chip, the financial cost of encapsulation is reduced again.

Description

A kind of bonded wafer level packaging structure and its technological process
Technical field
It is specifically a kind of by silicon support plate technology and traditional wire soldering technology knot the present invention relates to integrated antenna package field The bonded wafer level packaging structure of conjunction and its technological process.
Background technology
Traditional integrated antenna package scheme, it is to be pasted onto chip-stacked on package substrate or encapsulating lead, By wire bonding, conjunction is filled out in injection, plants ball, and cutting separates a kind of encapsulation interconnection technique of unification again；Traditional scheme have into Ripe technique, takes substrate or lead frame, but threshold bottom, and rival is easy to imitate duplicate circuit design, is unsuitable for Secret chip package scheme.
Advanced integrated antenna package scheme, wafer-level packaging, it is in units of disk, central characteristics are utilized using again Distribution technique carries out rearrangement to the pad for being distributed in chip perimeter, and realizes wafer scale completing flip chip technology (fct) afterwards Encapsulation, a kind of interconnection technique with passive silicon pinboard perpendicular interconnection is realized into the active face upset of chip down, from before 30 years Since IBM Corporation comes out, it has been widely used, the technical characterstic is no bonding wire (no wire bonding) technology, is needed The interconnection technique of chip attachment is carried out using upside-down mounting soldering equipment, but cost is higher.
The content of the invention
For above-mentioned technical problem, the purpose of the present invention is：It is proposed a kind of by silicon support plate technology and traditional bonding wire The bonded wafer level packaging structure and its technological process that technology combines.
What the technical solution of the present invention was realized in：A kind of bonded wafer level packaging structure, includes passive silicon Sill carrier element, capsulation material and multiple active chips, multiple active chips stack and are pasted onto passive silica-base material carrier On unit, and pass through capsulation material plastic packaging；The passive silica-base material carrier element includes what is set gradually bottom-up Ball pad plating bonding wire layer, wiring route metal level, passivation polymer layer and bonding bonding wire layer are planted, plants and is set on ball pad plating bonding wire layer It is equipped with multiple tin balls；Pad is provided with the active chip, the bottom of active chip is provided with thin-film material, and adjacent is active The pad of chip is electrically connected with by gold thread, and the pad of the source chip of bottom is electrically connected with by gold thread with being bonded bonding wire layer.
The technological process of above-mentioned bonded wafer level packaging structure, comprises the following steps：
1. process passive silica-base material carrier；
One layer of nanoscale sacrificial film layer is first established on special mechanical metal carrier, then processing is more on sacrificial film layer Individual passive silica-base material carrier element, each passive silica-base material carrier element include the plant ball set gradually bottom-up Pad plating bonding wire layer, wiring route metal level, passivation polymer layer and bonding bonding wire layer；
2. active chip is affixed into passive silica-base material carrier；
Stacked on each passive silica-base material carrier element and paste multiple active chips, be provided with pad on active chip, have The bottom of source chip is provided with thin-film material；
3. wafer scale bonding wire；
The pad of adjacent active chip is electrically connected with by gold thread, and the pad of the source chip of bottom is by gold thread with being bonded bonding wire Layer is electrically connected with；
4. wafer scale plastic packaging；
Capsulation material is filled on passive silica-base material carrier element, protects the active chip and gold thread of inside；
5. bottom is peeled off；
After capsulation material solidification, stripping nano level sacrificial film layer, and separated in synchronization mechanical metal carrier；
6. wafer scale plants ball；
By tin ball bonding on the plant ball pad plating bonding wire layer of passive silica-base material carrier element bottom surface；
7. using separator and disk unit removal techniques by step 6. in product by unit separation cutting unification.
Due to the utilization of above-mentioned technical proposal, the present invention has following advantages compared with prior art：
The bonded wafer level packaging structure of the present invention and its technological process, by advanced silicon support plate technology, chip and wafer Technology for applying, with reference to traditional bonding wire interconnection technique, it can effectively integrate using existing factory resources, such as WB bonding wires board, While ensureing the package application of secret chip, the financial cost of encapsulation is reduced again.
Brief description of the drawings
Technical solution of the present invention is described further below in conjunction with the accompanying drawings：
The step of accompanying drawing 1 is the technological process of bonded wafer level packaging structure of the present invention 1. schematic diagram；
The step of accompanying drawing 2 is above-mentioned technological process 2. schematic diagram；
The step of accompanying drawing 3 is above-mentioned technological process 3. schematic diagram；
The step of accompanying drawing 4 is above-mentioned technological process 4. schematic diagram；
The step of accompanying drawing 5 is above-mentioned technological process 5. schematic diagram；
The step of accompanying drawing 6 is above-mentioned technological process 6. schematic diagram；
The step of accompanying drawing 7 is above-mentioned technological process 7. schematic diagram.
Embodiment
Illustrate the present invention below in conjunction with the accompanying drawings.
A kind of technological process of bonded wafer level packaging structure of the present invention, comprises the following steps：
1. process passive silica-base material carrier；
As shown in Figure 1, one layer of nanoscale sacrificial film layer 2 is first established on special mechanical metal carrier 1, then it is thin sacrificing Multiple passive silica-base material carrier elements 3 are processed on film layer 2, each passive silica-base material carrier element 3 is included from bottom Plant ball pad plating bonding wire layer 31, wiring route metal level 32, passivation polymer layer 33 and the bonding bonding wire layer set gradually upwards 34；
2. active chip is affixed into passive silica-base material carrier；
As shown in Figure 2, stacked offset pastes 2 active chips 22 on each passive silica-base material carrier element 3, there is source core The upper surface of piece 22 is provided with pad 23, and the bottom of active chip 22 is provided with thin-film material 21；
3. wafer scale bonding wire；
As shown in Figure 3, the pad 23 of two active chips 22 is electrically connected with by a gold thread 24, the source chip 22 of bottom Pad 23 is electrically connected with by another gold thread 24 with being bonded bonding wire layer 34；
4. wafer scale plastic packaging；
As shown in Figure 4, capsulation material 41 is filled on passive silica-base material carrier element 3, that protects inside has source core Piece 22 and gold thread 24；
5. bottom is peeled off；
As shown in Figure 5, after the solidification of capsulation material 41, stripping nano level sacrificial film layer 2, and separated in synchronization mechanical metal carries Tool 1；
6. wafer scale plants ball；
As shown in Figure 6, the plant ball pad for tin ball 61 being welded on to the passive bottom surface of silica-base material carrier element 3 electroplates bonding wire layer 31 On；
7. as shown in Figure 7, using separator 71 and disk unit removal techniques by step 6. in product by unit point From cutting unification.
The bonded wafer-level packaging unit finally obtained, include passive silica-base material carrier element 3, the and of capsulation material 41 2 active chips, 22,2 stacked offsets of active chip 22 are pasted onto on passive silica-base material carrier element 3, and pass through plastic packaging material Expect 41 plastic packagings；The passive silica-base material carrier element 3 includes the plant ball pad plating bonding wire layer set gradually bottom-up 31st, wiring route metal level 32, passivation polymer layer 33 and bonding bonding wire layer 34, plant be provided with ball pad plating bonding wire layer 31 it is more Individual tin ball 61；Pad 23 is provided with the active chip 22, the bottom of active chip 22 is provided with thin-film material 21, and two have The pad 23 of source chip 22 is electrically connected with by a gold thread 24, and the pad 23 of the source chip 22 of bottom passes through another gold thread 24 It is electrically connected with being bonded bonding wire layer 34.
The above embodiments merely illustrate the technical concept and features of the present invention, and its object is to allow person skilled in the art Scholar can understand present disclosure and be carried out, and it is not intended to limit the scope of the present invention, all according to the present invention The equivalent change or modification that Spirit Essence is made, it should all cover within the scope of the present invention.

Claims (2)

  1. A kind of 1. bonded wafer level packaging structure, it is characterised in that：Include passive silica-base material carrier element（3）, plastic packaging material Material（41）With multiple active chips（22）, multiple active chips（22）Stacking is pasted onto passive silica-base material carrier element（3）On, And pass through capsulation material（41）Plastic packaging；The passive silica-base material carrier element（3）Include what is set gradually bottom-up Plant ball pad plating bonding wire layer（31）, wiring route metal level（32）, passivation polymer layer（33）With bonding bonding wire layer（34）, plant ball Pad plating bonding wire layer（31）On be provided with multiple tin balls（61）；The active chip（22）On be provided with pad（23）, there is source core Piece（22）Bottom be provided with thin-film material（21）, adjacent active chip（22）Pad（23）Pass through gold thread（24）Electrically connect Connect, the source chip of bottom（22）Pad（23）Pass through gold thread（24）With being bonded bonding wire layer（34）It is electrically connected with.
  2. 2. the technological process of bonded wafer level packaging structure as claimed in claim 1, it is characterised in that including following step Suddenly：
    1. process passive silica-base material carrier；
    First in special mechanical metal carrier（1）On establish one layer of nanoscale sacrificial film layer（2）, then in sacrificial film layer（2） On process multiple passive silica-base material carrier elements（3）, each passive silica-base material carrier element（3）Include from bottom to On set gradually plant ball pad plating bonding wire layer（31）, wiring route metal level（32）, passivation polymer layer（33）Welded with bonding Line layer（34）；
    2. active chip is affixed into passive silica-base material carrier；
    In each passive silica-base material carrier element（3）Upper stack pastes multiple active chips（22）, active chip（22）On set It is equipped with pad（23）, active chip（22）Bottom be provided with thin-film material（21）；
    3. wafer scale bonding wire；
    Adjacent active chip（22）Pad（23）Pass through gold thread（24）It is electrically connected with, the source chip of bottom（22）Pad （23）Pass through gold thread（24）With being bonded bonding wire layer（34）It is electrically connected with；
    4. wafer scale plastic packaging；
    By capsulation material（41）It is filled in passive silica-base material carrier element（3）On, protect internal active chip（22）With Gold thread（24）；
    5. bottom is peeled off；
    Treat capsulation material（41）After solidification, stripping nano level sacrificial film layer（2）, and separated in synchronization mechanical metal carrier（1）；
    6. wafer scale plants ball；
    By tin ball（61）It is welded on passive silica-base material carrier element（3）The plant ball pad plating bonding wire layer of bottom surface（31）On；
    7. utilize separator（71）And disk unit removal techniques by step 6. in product by unit separation cutting it is single Change.
CN201710946381.6A 2017-10-12 2017-10-12 A kind of bonded wafer level packaging structure and its process flow Active CN107845600B (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370334A (en) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司 3D packaging method
CN114141762A (en) * 2021-11-29 2022-03-04 沛顿科技（深圳）有限公司 Manufacturing method of multi-chip stacking fan-out type packaging structure
TWI802181B (en) * 2020-12-30 2023-05-11 加拿大商萬國半導體國際有限合夥公司 Semi-wafer level chip scale semiconductor package and method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593085A (en) * 2011-01-10 2012-07-18 原相科技股份有限公司 Chip packaging structure and chip packaging manufacturing process
CN102629604A (en) * 2012-04-06 2012-08-08 天水华天科技股份有限公司 Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package
CN102903680A (en) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof
CN104091791A (en) * 2012-08-31 2014-10-08 天水华天科技股份有限公司 Lead frame pagoda type IC chip stacked package part and production method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593085A (en) * 2011-01-10 2012-07-18 原相科技股份有限公司 Chip packaging structure and chip packaging manufacturing process
CN102903680A (en) * 2011-07-27 2013-01-30 矽品精密工业股份有限公司 Semiconductor package and fabrication method thereof
CN102629604A (en) * 2012-04-06 2012-08-08 天水华天科技股份有限公司 Cantilever type IC (Integrated Circuit) chip stack package of BT (Bismaleimide Triazine) substrate and production method of cantilever type IC chip stack package
CN104091791A (en) * 2012-08-31 2014-10-08 天水华天科技股份有限公司 Lead frame pagoda type IC chip stacked package part and production method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111370334A (en) * 2018-12-26 2020-07-03 中芯集成电路（宁波）有限公司 3D packaging method
CN111370334B (en) * 2018-12-26 2022-07-08 中芯集成电路（宁波）有限公司 3D packaging method
TWI802181B (en) * 2020-12-30 2023-05-11 加拿大商萬國半導體國際有限合夥公司 Semi-wafer level chip scale semiconductor package and method thereof
US11721665B2 (en) 2020-12-30 2023-08-08 Alpha And Omega Semiconductor International Lp Wafer level chip scale semiconductor package
CN114141762A (en) * 2021-11-29 2022-03-04 沛顿科技（深圳）有限公司 Manufacturing method of multi-chip stacking fan-out type packaging structure
CN114141762B (en) * 2021-11-29 2024-09-03 沛顿科技（深圳）有限公司 Manufacturing method of multi-chip stacked fan-out type packaging structure

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