CN105900244A - 用于高电压应用的具有含多场弛豫沟槽的终端结构的沟槽mos器件 - Google Patents

用于高电压应用的具有含多场弛豫沟槽的终端结构的沟槽mos器件 Download PDF

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CN105900244A
CN105900244A CN201480072323.XA CN201480072323A CN105900244A CN 105900244 A CN105900244 A CN 105900244A CN 201480072323 A CN201480072323 A CN 201480072323A CN 105900244 A CN105900244 A CN 105900244A
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林亦佑
张竣珏
龚璞如
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Vishay General Semiconductor LLC
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Abstract

本发明公开了一种用于半导体器件的终端结构，所述终端结构包括具有有源区和终端区的半导体衬底。两个或更多个沟槽单元位于所述终端区中并从所述有源区的边界朝所述半导体衬底的边缘延伸。终端沟槽在所述终端区中所述沟槽单元的远离所述有源区的一侧上形成。导电间隔物位于与所述终端沟槽的最接近所述沟槽单元的侧壁相邻的位置。第一氧化物层在所述终端沟槽中形成并接触所述导电间隔物的侧壁。第一导电层在所述半导体衬底的背表面上形成。第二导电层在所述有源区和所述终端区顶部形成。

Description

用于高电压应用的具有含多场弛豫沟槽的终端结构的沟槽MOS器件
技术领域
本发明整体涉及半导体器件，更具体地讲，涉及用于沟槽MOS器件的终端结构。
背景技术
传统上，肖特基二极管包括重掺杂的半导体衬底，典型地，该衬底由单晶硅制成。第二层覆盖衬底。第二层被称为漂移区，较不重地掺杂有具有与衬底相同导电类型的载流子的杂质。金属层或金属硅化物层形成具有轻掺杂的漂移区的肖特基接触，并形成二极管阳极。
当形成单极部件诸如肖特基二极管时，会出现两个相对立的约束。具体地讲，该部件应在具有高击穿电压的同时呈现出尽可能最低的导通态电阻(Ron)。使导通态电阻最小化，促使最大限度地减小较少掺杂层的厚度并且最大限度地提高了该层的掺杂。相反，为了获得高的反向击穿电压，必须使较少掺杂层的掺杂最小化并且必须使其厚度最大化，同时避免形成等势面强烈弯曲的区域。
已经提供了各种解决方案来调和这些相对立的约束，这导致了沟槽MOS电容肖特基二极管结构的发展，这种二极管结构被称为沟槽MOS势垒肖特基(TMBS)二极管。在这种器件的一个例子中，沟槽区在厚漂移层的上部中形成，该厚漂移层比下层衬底较不重地掺杂有与相同导电类型的杂质。沟槽区填充有MOS结构。蒸镀阳极金属层以覆盖整个表面并形成具有下层漂移区的肖特基接触。
当反向偏置时，绝缘导电区使电荷的横向耗尽进入漂移区，这改变了该层中等势面的分布。这使得能够增加漂移区掺杂，并因此降低了导通态电阻而不会对反向击穿电压造成不利影响。
要实现高电压肖特基整流器，一个关键问题是其终端区的设计。与任何电压设计一样，终端区由于不存在自身多单元保护和曲率效应而易于形成较高电场。因此，击穿电压通常从其理想值急剧地降低。为了避免这种降低，应将终端区设计成减少在器件边缘处(有源区附近)的电场聚集。减少电场聚集的常规方法包括提供终端结构，该终端结构具有硅局部氧化(LOCOS)区、场板、保护环、沟槽及其各种组合。美国专利No.6,396,090中示出了包括这种终端区的肖特基二极管的一个例子。
图1示出了美国专利申请No.12/724,771中所示类型的TMBS肖特基二极管的有源区和终端区的简化剖视图。有源区包括重掺杂有第一导电类型(如n+型)的掺杂剂的半导体衬底100B。第一层100A在衬底100B上形成，并且较多地轻掺杂有第一导电类型(如n-型)的掺杂剂。沟槽110(仅示出了其中的一个)在第一层100A中形成。沟槽110衬接绝缘层125，并填充有导电材料140诸如掺杂的多晶硅。金属层165在导电材料140和第一层100A的暴露表面上方形成，从而在金属层165和第一层100A之间的界面处形成肖特基接触160。阴极电极(未示出)位于半导体衬底100B的背面上。
图1所示的TMBS二极管的终端区包括从有源区的边界112朝半导体衬底100B的边缘延伸的终端沟槽120。MOS栅极122在与有源区的边界112相邻的终端区的侧壁上形成。MOS栅极包括绝缘材料128和导电间隔物122。绝缘材料128衬接导电间隔物122所在的侧壁和第一层100A的与侧壁相邻的部分。导电间隔物122覆盖绝缘材料128。终端氧化物层150在终端沟槽120中形成并从导电间隔物122朝器件的边缘延伸。位于有源区中的金属层165延伸进入终端区并覆盖导电间隔物122和终端氧化物层150的一部分，从而限定场板。
遗憾的是，对于高电压应用，终端区的这些常规设计成效甚微，这是因为在终端区表面处的电场分布仍然很不理想。由于漂移区的长度有限，所以电场由于不对称而在有源区的端部迅速增大。因此，在器件的击穿中，边缘击穿占主导地位。
图1所示的常规器件已被驱动到200V，但这时其性能已经由于终端区表面处的过早击穿而降低。因此，本设计的可靠性在很大程度上取决于场板165在终端区中的端部位置。通常，在形成场板165时所使用的金属湿法蚀刻工艺只能被控制在约±6μm的精度内，而这种波动会显著影响器件的反向阻断电压。例如，短场板将会增大最近有源单元角落附近的电场，导致过早击穿。另一方面，延伸到远端隔离件附近位置的较长场板也可降低击穿电压，同时也在其细长金属端引起机械应力。
伸长的金属长度变化(μm) -4 -2 0 +2 +4 +6 +8
击穿电压Vbr(V) 235 277 278 276 271 269 261
击穿波动(％) -15.5 -0.72 - -0.72 -2.52 -3.24 -6.14
表1：常规TMBS终端的击穿电压与金属场板长度
表1示出了击穿电压随着金属场板长度的变化而发生的变化。通过模拟针对具有20μm终端沟槽的高击穿电压TMBS器件所设计的漂移层，获得了这些数据。应该指出的是，漂移区的具有相同参数的单位单元的击穿电压为375V，并且如表所示，用常规的终端设计可获得的最高击穿电压是理想值的74％。
发明内容
本发明公开了一种用于半导体器件的终端结构。该终端结构包括具有有源区和终端区的半导体衬底。两个或更多个沟槽单元位于终端区中并从有源区的边界朝半导体衬底的边缘延伸。终端沟槽在终端区中沟槽单元的远离有源区的一侧上形成。导电间隔物位于与终端沟槽的最接近沟槽单元的侧壁相邻的位置。第一氧化物层在终端沟槽中形成并接触导电间隔物的侧壁。第一导电层在半导体衬底的背表面上形成。第二导电层在有源区和终端区顶部形成。
本发明还公开了一种形成半导体器件的方法。根据该方法，形成至少一个位于半导体衬底的有源区中的沟槽MOS器件。形成两个或更多个沟槽单元，它们位于与半导体衬底的有源区相邻的半导体衬底的终端区中。沟槽单元从有源区和终端区之间的边界朝半导体衬底的边缘延伸。在半导体衬底终端区中沟槽单元的远离有源区的一侧上形成终端沟槽。形成导电间隔物，它位于与终端沟槽的最接近沟槽单元的侧壁相邻的位置。在终端沟槽中形成接触导电间隔物的侧壁的第一氧化物层。在半导体衬底的背表面上形成第一导电层。第二导电层位于有源区顶部。在终端区中形成场板。
附图说明
图1是常规TMBS二极管或整流器的简化局部视图。
图2示出了根据本发明所构造的TMBS二极管的一个例子的有源区和终端区的剖视图。
图3示出了对于长度为12微米的场板，在图1所示的常规器件和图2所示的器件的终端区下的各个位置处的电场。
图4示出了对于长度为5微米的场板，在图1所示的常规器件和图2所示的器件的终端区下的各个位置处的电场。
图5至图8示出了可用于制造图2所示器件的工序的一个例子。
具体实施方式
如下详述，提供了一种能够减轻上述问题的终端结构。该结构包括两个或更多个沟槽单元以及延伸超过终端沟槽的终端沟槽。终端结构的沟槽充当场弛豫环以增大器件的击穿电压。伸长的金属场板覆盖沟槽单元和终端沟槽两者。这种终端结构可延长电场分布的边界，而额外的沟槽单元可进一步降低由于场板长度的变化所导致的对电场分布的影响。将提供模拟结果，示出终端结构对击穿电压的影响。
图2示出了根据本发明的一个例子所构造的TMBS肖特基二极管的有源区和终端区的剖视图。有源区包括重掺杂有第一导电类型(如n+型)的掺杂剂的半导体衬底110B。第一层100A在衬底100B上形成，并且较多地轻掺杂有第一导电类型(如n-型)的掺杂剂。沟槽110(仅示出了其中的一个)在第一层100A中形成。沟槽110衬接绝缘层125，并填充有导电材料113，诸如多晶硅或金属(诸如Al)。金属层165在导电材料113和第一层100A的暴露表面上方形成，从而在金属层165和第一层100A之间的界面处形成肖特基接触160。阴极电极170位于半导体衬底100B的背面上。
图2所示的TMBS肖特基二极管的终端结构在本文中被称为多场弛豫沟槽(MFRT)结构，它包括一个或多个沟槽单元111，这些沟槽单元111始于有源区的边界112处并朝半导体衬底100B的边缘延伸。在这个例子中，示出了三个这样的沟槽单元111。在沟槽单元111远处，更靠近衬底100B的位置，是终端沟槽120，它也是终端区的一部分。
沟槽单元111和终端沟槽120衬接绝缘层126，并填充有导电材料141，诸如掺杂的多晶硅或金属(诸如铝)。导电间隔物122在终端沟槽120的最接近沟槽单元111的侧壁上形成。绝缘材料126衬接导电间隔物122所在的侧壁和第一层100A的与侧壁相邻的部分。
终端氧化物层150在终端沟槽120中的绝缘材料126上形成。终端氧化物层150从导电间隔物122朝器件的边缘并在终端沟槽120的远端侧壁118上方延伸。终端氧化物层150还覆盖第一层100A的位于沟槽单元111之间以及在沟槽单元111和终端沟槽120之间的表面。位于有源区中的金属层165延伸进入终端区并覆盖沟槽单元111以及氧化物层150的位于其间的一部分。金属层165延伸进入终端沟槽120，覆盖导电间隔物122以及氧化物层165的位于终端沟槽120中的一部分。金属层165用作场板，可在到达终端沟槽120的远端侧壁118之前终止。
图3示出了在图1所示的常规器件和图2所示的器件的终端区下的各个位置处的电场。在这两种情况下，场板的长度为12微米，反向偏压为200V。通过计算机模拟确定了电场。图3中标出了五个点，每个点表示一个不同的位置，具体如下：
点1表示如图1所示的常规TMBS器件的聚合物间隔物下的最大电场。
点2表示如图1所示的常规TMBS器件的场板终端下的最大电场。
点a表示如图2所示的具有MFRT终端结构的TMBS器件的沟槽单元下的最大电场。
点b表示如图2所示的具有MFRT终端结构的TMBS器件的导电间隔物下的最大电场。
点3表示如图2所示的具有MFRT终端结构的TMPS器件的场板终端下的最大电场。
类似于图3，图4示出了在图1所示的常规器件和图2所示的器件的终端结构下的各个位置处的电场。然而，在此例子中，场板的长度为5微米。
图3和图4所示的结果表明，常规器件和图2所示的器件之间的主要区别是导电间隔物下的电场值和场板终端下的电场值。常规TMBS器件下的最大电场在导电间隔物下出现，特别是在场板的长度为5微米时。另一方面，在场板的长度为5微米时，图2所示的TMBS器件下的最大电场在沟槽单元的底部下出现。虽然在常规器件和图2所示的器件两者中的最大电场高达4×a105V/cm，但是在后一种TMBS器件中，由于在位于沟槽单元之间的台面上缺少导电通路，所以终端区不会影响器件的击穿电压。
当场板的长度为12微米时，图2所示的器件可使击穿电压从212V增大到226V。当场板的长度为5微米时，图2所示的器件仍然可使击穿电压保持为约225V，但是在常规器件中，击穿电压减小到170V。
图2所示的结构的一个重要优点是，它的制造不需要除了用于制造图1所示的常规TMBS器件的工序之外的任何额外工序。相比于传统的边缘终端技术，无需额外控制扩散工艺或复杂的多场板设置。举例来说，可将用于保护环的沟槽与有源区中的沟槽同时形成。此外，可将绝缘层125和126彼此同时形成，并可将导电材料140和141彼此同时沉积。
将结合图5至图8来描述可用于形成图2所示的TMBS二极管的方法的一个例子。在这个例子中，肖特基二极管及其终端结构同时形成，但情况并非总是如此。
图5是半导体衬底200的剖视图，该半导体衬底200包括第一层200A和基部衬底200B，其中第一层200A具有第一导电类型(如n-型)的掺杂剂，基部衬底200B较重地掺杂有第一导电类型(如n+型)的掺杂剂。通过化学气相沉积(CVD)在第一衬底200A上形成氧化物层201，例如厚度为约2000埃至10,000埃。接着，将光致抗蚀剂(未示出)涂覆在氧化物层201上，以在有源区中限定一个或多个有源区沟槽210，在终端区中限定多个沟槽单元211，还在终端区中限定终端沟槽220。虽然在这个例子中示出了三个沟槽单元211，但是本领域技术人员将认识到，可使用相同的工艺来形成具有任意数目的沟槽单元的器件。沟槽单元211彼此被台面215间隔开，并且沟槽单元211与终端沟槽220被台面216分隔开。此外，台面214将有源单元彼此210彼此分隔开，并使彼此相邻的沟槽单元211和有源单元210分隔开。在一个例子中，各有源区沟槽210的宽度为约0.2微米至2.0微米。在一个例子中，终端沟槽220具有12μm的宽度，保护环沟槽具有0.5μm的宽度。
参见图6，在移除氧化物层201之后，进行高温氧化处理以形成栅极氧化物层225和终端氧化物层226。在有源沟槽210、沟槽单元211和终端沟槽220的侧壁和底部上形成氧化物层225和226，在一些例子中，这些氧化物层具有约150埃和3000埃之间的厚度。可在单个工艺中同时形成与所有各个沟槽衬接的氧化物层225和226。在氧化工艺之外，可由高温沉积形成氧化物层225和226，从而形成HTO(高温氧化物沉积)层。
接着，同样参见图6，通过例如CVD法在氧化物225和226上形成第一导电层240，并且该第一导电层240填充有源沟槽210、终端沟槽220、沟槽单元211以及台面214、215和216。第一导电层240具有一定的厚度，使得其在台面215和216上方延伸。第一导电层240可以是任何合适的材料，诸如金属、掺杂的多晶硅或掺杂的非晶硅。第一导电层240可具有约0.5微米至3.0微米的厚度。为了防止在沟槽210的内部形成空隙，第一导电层240可以是通过LPCVD(低压CVD)工艺形成的具有良好阶梯覆盖的多晶硅。然而，在一些情况下，非晶硅能够比多晶硅更好地消除空隙。为了使非晶硅导电，可采用重结晶工艺。
现在参见图7，进行各向异性蚀刻，以移除过量的第一导电层240。在此蚀刻工艺中，从终端沟槽220移除除了导电间隔物242以外的导电材料，该导电间隔物242形成于终端氧化物层226上，衬接终端沟槽220的最接近沟槽单元211的侧壁。在一些例子中，导电间隔物242的宽度(沿所示的剖视图)约等于终端沟槽220的高度。
接着，使用蚀刻工艺在终端区中形成介电层250。介电层250可以是例如TEOS层，诸如LPTEOS或PETEOS层或者O3-TEOS或HTO层。在一些例子中，介电层250的厚度可以在约0.2微米至1.0微米之间。介电层250覆盖沟槽单元211的最接近有源区的部分，以及第一层210A的在沟槽单元211之间的部分(即台面215)和在终端沟槽120和沟槽单元211之间的部分(即台面216)。介电层250还覆盖终端沟槽220并接触导电间隔物242的侧壁。然而，导电间隔物242的最上表面230保持暴露。
接着，在图8中，进行溅射或其他合适的工艺，在整个结构上方沉积第二导电层165，以便在台面114上形成肖特基接触区260。第二导电层165可由能够与下面的第一层100A形成肖特基二极管的任何材料形成。例如，第二导电层165可以是金属硅化物层。最后，在衬底100B的背面上沉积阴极电极170。
实例
通过举例说明的方式，将为本发明的包括四个沟槽单元的一个具体实施例指定各种结构尺寸和参数。在该实施例中，终端沟槽120具有范围从10微米至50微米的宽度，并且其深度可与有源区中的沟槽110的深度相同或不同。取决于具体的设计和所需的器件特性(如耐压、速度、漏电流)，终端沟槽120的深度可在0.5微米至10微米的范围内。位于终端沟槽120中的介电层150可以是二氧化硅层，该二氧化硅层具有在约1500埃至15,000埃之间的厚度，具体取决于所需的阻断电压和材料的组成。
沟槽单元可具有在0.2微米和2.0微米之间的宽度，以及在0.5微米和10微米之间的深度。沟槽单元的宽度和深度可以彼此相同或不同。在终端沟槽120中，由导电层165延伸进入终端区所限定的场板可具有在约5微米和50微米之间的长度。
本文所述的MFRT终端结构提供了许多益处。例如，通过使终端结构下的电场重新分布，导电间隔物将不是影响器件的击穿电压的关键点。因此，终端结构的击穿电压维持能力将与有源区的击穿电压维持能力相近。此外，如果在可用于形成场板的湿法金属蚀刻工艺期间存在任何控制问题，则导电间隔物下的电场和场板远端下的电场仍然可以维持在可接受的水平并且不会影响击穿电压。
应该指出的是，可将本文所述的MFRT终端结构与除了TMBS二极管之外的器件结合使用，本文通过仅举例说明的方式介绍了TMBS二极管。例如，可将终端结构应用于任何功率晶体管，诸如双倍扩散的金属氧化物半导体场效应晶体管(DMOSFET)、绝缘栅双极型晶体管(IGBT)以及其他沟槽MOS器件。
应当理解，为了便于说明，本文中使用了空间相对术语诸如“顶部”、“底部”、“上方”、“上”、“之下”、“下方”、“下”等来描述如在附图中所示的一个要素或特征与另一要素或特征之间的关系。应当理解，空间相对术语旨在包括除了附图中所描绘的取向外，还包括器件在使用或操作时的不同取向。例如，如果将附图中的器件翻转，则被描述为在其他要素或特征的“下方”或“之下”的要素将被取向为在所述其他要素或特征的“上方”。因此，示例性术语“上方”可涵盖上方和下方这两种取向。
虽然本文明确示出并描述了各种实施例，但应当理解在不脱离本发明的精神和预期范围的情况下，本发明的修改形式和变型形式被上面的教导内容所涵盖并且在所附权利要求书的范围内。

Claims (20)

1.一种用于半导体器件的终端结构，所述终端结构包括：
具有有源区和终端区的半导体衬底；
位于所述终端区中并从所述有源区的边界朝所述半导体衬底的边缘延伸的多个沟槽单元；
在所述终端区中所述多个沟槽单元的远离所述有源区的一侧上形成的终端沟槽；
位于与所述终端沟槽的最接近所述多个沟槽单元的侧壁相邻的位置的导电间隔物；
在所述终端沟槽中形成并接触所述导电间隔物的侧壁的第一氧化物层；
在所述半导体衬底的背表面上形成的第一导电层；以及
在所述有源区和所述终端区顶部形成的第二导电层。
2.根据权利要求1所述的终端结构，还包括衬接所述沟槽单元和所述终端沟槽的侧壁和底表面的第二氧化物层，所述导电间隔物与所述终端沟槽的侧壁和底表面上的所述第二氧化物层相接触。
3.根据权利要求2所述的终端结构，还包括第三氧化物层，所述第三氧化物层位于在相邻的沟槽单元之间所设置的台面上并且还位于所述第二导电层与所述半导体衬底之间。
4.根据权利要求1所述的终端结构，其中所述半导体器件是肖特基二极管。
5.根据权利要求3所述的终端结构，其中所述肖特基二极管为在所述衬底的所述有源区中包括至少一个沟槽的TMBS肖特基二极管。
6.根据权利要求2所述的终端结构，其中所述沟槽单元填充有导电材料。
7.根据权利要求1所述的终端结构，其中所述第二导电层作为连续层延伸，所述连续层延伸进入所述终端沟槽的至少一部分和所述沟槽单元内，使得所述第二导电层和所述导电间隔物彼此电耦接。
8.根据权利要求1所述的终端结构，其中所述终端结构用于选自由功率晶体管和整流器所构成的组中的器件。
9.一种半导体器件，包括：
半导体衬底，所述半导体衬底具有位于该半导体衬底的有源区中的至少一个沟槽MOS器件；
位于所述半导体衬底中的与所述半导体衬底的所述有源区相邻的终端区中的多个沟槽单元，所述多个沟槽单元从所述有源区与所述终端区之间的边界朝所述半导体衬底的边缘延伸；
在所述终端区中所述多个沟槽单元的远离所述有源区的一侧上形成的终端沟槽；
衬接所述多个沟槽单元和所述终端沟槽的第一氧化物层；
位于与所述终端沟槽的最接近所述多个沟槽单元的侧壁相邻的位置的导电间隔物；
在所述终端沟槽中形成并接触所述导电间隔物的侧壁的第二氧化物层；
在所述半导体衬底的背表面上形成的第一导电层；以及
位于所述有源区和所述终端区顶部的第二导电层，所述第二导电层的位于所述终端区中的一部分限定了场板。
10.根据权利要求9所述的半导体器件，其中所述半导体衬底包括第一层和基部衬底，并且所述第一层具有轻掺杂的第一类型的导电杂质，并且所述基部衬底具有重掺杂的所述第一类型的导电杂质。
11.根据权利要求9所述的半导体器件，其中所述沟槽MOS器件和所述终端沟槽形成于所述第一层中并且具有在约0.5微米至10.0微米之间的深度。
12.根据权利要求9所述的半导体器件，其中所述终端沟槽具有在约10微米至50微米之间的宽度。
13.根据权利要求9所述的终端结构，还包括第三氧化物层，所述第三氧化物层位于在相邻的沟槽单元之间所设置的台面上并且还位于所述第二导电层与所述半导体衬底之间。
14.根据权利要求9所述的终端结构，其中所述半导体器件是肖特基二极管。
15.根据权利要求14所述的终端结构，其中所述肖特基二极管为在所述衬底的所述有源区中包括至少一个沟槽的TMBS肖特基二极管。
16.根据权利要求9所述的终端结构，其中所述沟槽单元填充有导电材料。
17.根据权利要求9所述的终端结构，其中所述第二导电层作为连续层延伸，所述连续层延伸进入所述终端沟槽的至少一部分和所述沟槽单元内，使得所述第二导电层和所述导电间隔物彼此电耦接。
18.根据权利要求9所述的终端结构，其中所述终端结构用于选自由功率晶体管和整流器所构成的组中的器件。
19.一种形成半导体器件的方法，包括：
形成位于半导体衬底的有源区中的至少一个沟槽MOS器件；
形成位于所述半导体衬底中的与所述半导体衬底的所述有源区相邻的终端区中的多个沟槽单元，所述多个沟槽单元从所述有源区与所述终端区之间的边界朝所述半导体衬底的边缘延伸；
在所述半导体衬底的所述终端区中所述多个沟槽单元的远离所述有源区的一侧上形成终端沟槽；
形成位于与所述终端沟槽的最接近所述多个沟槽单元的侧壁相邻的位置的导电间隔物；
在所述终端沟槽中形成接触所述导电间隔物的侧壁的第一氧化物层；
在所述半导体衬底的背表面上形成第一导电层；以及
形成位于所述有源区顶部的第二导电层；以及
在所述终端区中形成场板。
20.根据权利要求19所述的方法，其中形成所述场板包括形成所述第二导电层到所述终端沟槽中的延伸。
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