TWI657583B - 具有多重場張馳溝渠的終端結構以用於高電壓應用的溝渠式ｍｏｓ裝置 - Google Patents

具有多重場張馳溝渠的終端結構以用於高電壓應用的溝渠式ｍｏｓ裝置 Download PDF

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TWI657583B
TWI657583B TW103136657A TW103136657A TWI657583B TW I657583 B TWI657583 B TW I657583B TW 103136657 A TW103136657 A TW 103136657A TW 103136657 A TW103136657 A TW 103136657A TW I657583 B TWI657583 B TW I657583B
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trench
terminal
conductive
semiconductor substrate
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林亦佑
張竣玨
龔璞如
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微協通用半導體有限責任公司
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Abstract

半導體裝置的終端結構包括具有主動區域與終端區域的半導體基板。二或以上的溝渠胞元位在終端區域中，且自主動區域的邊界朝向半導體基板的邊緣延伸。終端溝渠形成在離主動區域遠端的溝渠胞元之側上的主動區域中。導電隔層位在鄰接最接近溝渠胞元的終端溝渠之側壁。第一氧化物層形成在終端溝渠中且接觸導電隔層之側壁。第一導電層形成在半導體基板之背側表面。第二導電層形成在主動區域及終端區域的頂上。

Description

具有多重場張馳溝渠的終端結構以用於高電壓應用的溝渠式MOS裝置
本發明一般係關於半導體裝置，且更特別的是關於溝渠式MOS裝置的終端結構。
傳統上，蕭基二極體(Schottky diode)包括重摻雜的(heavily-doped)半導體基板，典型地由單晶矽(single-crystal silicon)作成。第二層覆蓋基板。第二層，稱為漂移區域(drift region)，係以具有與基板相同導電類型的載子之雜質(impurity)來進行較低的重摻雜。金屬層或金屬矽化物層形成與輕摻雜漂移區域的蕭基接觸(Schottky contact)且形成二極體的陽極。
當形成像是蕭基二極體的單極組件兩個對立的約束出現。特別是，組件應展現最低可能的開狀態(on-state)電阻(Ron)，同時具有高的崩潰電壓(breakdown voltage)。最小化開狀態電阻強迫最小化較 低摻雜層的厚度並且最大化此層的摻雜。相反的，為獲得高的逆向崩潰電壓，較低摻雜層的摻雜必需被最小化且其厚度必需被最大化，同時避免創建等電位表面在其中被強烈的彎曲的地區。
已提出個種解法以調解這些對立約束，其已導至發展溝渠式MOS電容蕭基二極體結構，其被稱為溝渠式MOS位障蕭基(TMBS；Trench MOS Barrier Schottky)二極體。在這類裝置之範例中，溝渠區域形成在與在下面的基板相同的導電類型之雜質來較低的重摻雜之厚漂移層的上部中。溝渠區域填充以MOS結構。蒸發陽極金屬層以覆蓋整體表面且形成與在下面的漂移區域之蕭基接觸。
當逆向偏壓時，絕緣導電地區引起電荷進入漂移區域的側向空乏(lateral depletion)，其修改在此層中的等電位表面之分佈。這使能增加漂移區域的摻雜，因而降低在沒有逆向崩潰電壓上不利效應的開狀態電阻。
用於達成高電壓蕭基整流器的關鍵問題為其終端區域的設計。如任何電壓設計一樣，終端區域傾向於較高的電場，其係由於缺乏自我多胞元保護(self multi-cell protection)及曲率效應(curvature effect)。結果，崩潰電壓典型地劇烈地從其理想值降低。為了避免此降低，終端區域應被設計成降低在裝置之邊緣(靠近主動區域)擠滿電場。傳統降低電場擠滿的方式包括具有矽之局部氧化(LOCOS；local oxidation of silicon)區域、場板 (field plate)、保護環(guard ring)、溝渠以及其各種結合。包括這類終端區域的蕭基二極體之範例係顯示於美國專利第6,396,090號中。
圖1繪示在美國專利申請案12/724,771中繪示之類型的TMBS蕭基二極體的主動及終端區域的簡化的剖面視圖。主動區域包括半導體基板100B，其以第一導電類型(例如，n+類型)之摻雜劑來重摻雜。第一層100A形成在基板100B上且以第一導電類型(例如，n-類型)之摻雜劑來較輕的摻雜。溝渠110(僅繪示其中一個)形成在第一層100A中。溝渠110上內襯有絕緣層125且填充以像是摻雜的多晶矽之導電材料140。金屬層165形成在導電材料140之曝露的表面和第一層100A之上，藉以形成在金屬層165與第一層100A之間介面處的蕭基接觸160。陰極電極(未繪示)係位在半導體基板100B之背側上。
在圖1中繪示的TMBS二極體包括終端溝渠120，其從具有主動區域的邊界112朝向半導體基板100B之邊緣延伸。MOS閘極122形成在鄰接具有主動區域的邊界112的終端區域之側壁上。MOS閘極包括絕緣材料128和導電隔層(conductive spacer)122。絕緣材料128沿著導電隔層122所位在靠著的側壁形成一層，且第一層100A的部分鄰接該側壁。導電隔層122覆蓋絕緣材料128。終端氧化物層150形成在終端溝渠120中且自導電隔層122朝裝置之邊緣延伸。位在主動區域中的金屬層 165延伸進入終端區域並且覆蓋導電隔層122以及一部分的終端氧化物層150來藉以界定場板。
不幸的，對於高電壓應用，這些用於終端區域的傳統設計早已僅具有有限的成功，因為在終端區域之表面的電場分佈仍與理想相距甚遠。因為漂移區域之有限的長度，電場由於非對稱而在主動區域之端部快速的上升。結果，裝置之崩潰則由邊緣崩潰所支配。
在圖1中繪示的傳統裝置已被驅動到200V，但由於在終端區域之表面處的過早崩潰(premature breakdown)，在這點上其效能已經降低。結果，此設計之可靠度大大的取決於在終端區域中場板165之端部位置。正常來說，在形成場板165中使用的金屬濕蝕刻製程能僅被控制到約±6μm內的精確度，並且此變異性(variability)能對裝置的逆向阻斷電壓(reverse blocking voltage)具有明顯的衝擊。舉例來說，短的場板將在接近最終主動胞元的角落擴增電場，造成過早崩潰。在另一方面，延伸到遠端隔層附近的點之較長的場板也能降低崩潰電壓，同時亦引起在其延長的金屬端的機械應力(mechanical stress)。
表1將在崩潰電壓中的變異顯示為金屬場板之長度的函數。資料已從設計用於具有20μm終端溝渠之高崩潰電壓TMBS裝置的漂移層之模擬來獲得。應注意，具有相同的漂移區域之參數的單位胞元(unit cell)之崩潰電壓為375V，並且如表所示，以傳統終端設計可達到的最高崩潰電壓為理想值的74%。
揭露了用於半導體裝置的終端結構。終端結構包括具有主動區域和終端區域的半導體基板。二個或以上的溝渠胞元位在終端區域並且從主動區域之邊界朝向半導體基板之邊緣延伸。終端溝渠形成在離主動區域之遠端溝渠胞元之側的終端區域中。導電隔層位在鄰接最近於溝渠胞元的終端溝渠之側壁。第一氧化物層形成在終端溝渠中且接觸導電隔層之側壁。第一導電層形成在半導體基板之背側表面上。第二導電層形成在主動區域及終端區域之頂上。
亦揭露了形成半導體裝置之方法。依據此方法，形成至少一溝渠MOS裝置，其位在半導體基板之主動區域中。形成二或以上的溝渠胞元，其位在鄰接半導體基板之主動區域的半導體基板之終端區域中。溝渠胞元自主動與終端區域之間的邊界朝向半導體基板之邊緣延伸。終端溝渠形成在離主動區域遠端的溝渠胞元之側上半導體 基板之終端區域中。形成導電隔層，其位在鄰接最近於溝渠胞元的終端溝渠之側壁。第一氧化物半導體層形成在終端溝渠中，其接觸導電隔層之側壁。第一導電層形成在半導體基板之背側表面上。第二導電層位在主動區域之頂上。場板形成在終端區域中。
110‧‧‧溝渠
112‧‧‧邊界
120‧‧‧終端溝渠
122‧‧‧MOS閘極
125‧‧‧絕緣層
128‧‧‧絕緣材料
140‧‧‧導電材料
150‧‧‧終端氧化物層
160‧‧‧蕭基接觸
165‧‧‧場板
118‧‧‧遠端側壁
126‧‧‧絕緣材料
113‧‧‧導電材料
111‧‧‧溝渠胞元
141‧‧‧導電材料
170‧‧‧陰極電極
100A‧‧‧第一層
100B‧‧‧基板
200A‧‧‧第一層
200B‧‧‧基底基板
200‧‧‧半導體基板
201‧‧‧氧化物層
210‧‧‧主動胞元
211‧‧‧溝渠胞元
214‧‧‧台面
215‧‧‧台面
216‧‧‧台面
220‧‧‧終端溝渠
225‧‧‧氧化物層
226‧‧‧氧化物層
240‧‧‧第一導電層
222‧‧‧MOS閘極
230‧‧‧最頂表面
242‧‧‧導電隔層
250‧‧‧介電層
260‧‧‧蕭基接觸區域
265‧‧‧場板
270‧‧‧陰極電極
圖1為傳統TMBS二極體或整流器之簡化、部分視圖。
圖2繪示依據本發明建構的TMBS二極體之一範例的主動及終端區域的剖面視圖。
圖3闡述在圖1繪示的傳統裝置之終端區域及用於12微米長度之場板的圖2繪示的裝置之下在各種位置處的電場。
圖4闡述在圖1中所繪示的傳統裝置之終端區域及在用於5微米長度場板的圖2中繪示的裝置之終端區域下在各種位置處的電場。
圖5~8闡述可採用以製造圖2之裝置的處理步驟之一範例。
如下的詳細說明，設置了減低前述問題的終端結構。此結構包括二或以上的溝渠胞元以及延伸到終端溝渠之外的終端溝渠。終端結構溝渠作為場張馳環(field relaxation ring)以增強裝置之崩潰電壓。延伸的金屬場板覆蓋溝渠胞元與終端溝渠兩者。這類的終端結構胞能延伸電場輪廓的邊界，同時額外的溝渠胞元能更降低對電場分佈的衝擊，其引起自場板之長度上的變異。將提出模擬結果顯示在崩潰電壓上終端結構之影響。
圖2繪示依據本發明一範例所建構的TMBS蕭基二極體之主動及終端區域的剖面視圖。主動區域包括半導體基板100B，其以第一導電類型(例如，n+類型)之摻雜劑來重摻雜。第一層100A形成在基板100B上且以第一導電類型(例如n-類型)之摻雜劑來較輕的摻雜。溝渠110(僅繪示其中一個)形成在第一層100A中。溝渠110內襯有絕緣層125且以導電材料113來填充，諸如經摻雜的多晶矽或像是Al的金屬。金屬層165形成在導電材料113之曝露表面及第一層100A之上，藉以在金屬層165與第一層100A之間介面處形成蕭基接觸160。陰極電極170位在半導體基板100B之背側上。
圖2中繪示的TMBS蕭基二極體之終端結構，於此參照為多重場張馳溝渠(MFRT；Multiple Field-Relaxation Trench)結構，包括一或以上的溝渠胞元111，其在具有主動區域的邊界112開始且朝向半導體基板100B的邊緣延伸。在此範例中，繪示了三個這類溝渠胞元111。越過溝渠胞元111，較接近於基板100B之邊緣，為終端溝渠120，其亦為終端區域的部分。
溝渠胞元111及終端溝渠120內襯有絕緣層 126且填充以導電材料141，諸如摻雜的多晶矽或像是Al的金屬。導電隔層122係形成在最近於溝渠胞元111的終端溝渠120之側壁。絕緣材料126在導電隔層122所位於靠著的側壁上形成一層，並且第一層100A之部分鄰接側壁。
終端氧化物層150形成在絕緣材料126上的終端溝渠120中。終端氧化物層150從導電隔層122朝向裝置之邊緣以及在終端溝渠120之遠端側壁118之上延伸。終端氧化物層150亦覆蓋位在溝渠胞元111之間且在溝渠胞元111與終端溝渠120之間的第一層100A之表面。在位主動區域中的金屬層165延伸進入終端區域且覆蓋溝渠胞元111以及位在其之間氧化物層150之部分。金屬層150延伸進入終端溝渠120，覆蓋導電隔層122以及位在終端溝渠120中部分的氧化物層150。金屬層165，其作為場板，可在達到終端溝渠120之遠端側壁118之前終止。
圖3闡述在圖1中繪示傳統裝置以及圖2中繪示的裝置之終端區域之下各種位置處的電場。在兩者情形中場板之長度為12微米且逆向偏壓(reverse bias)為200V。電場已由電腦模擬確定。在圖3中標示5個點，各者代表不同位置，其如下列所述：
點1代表在像是圖1中繪示的傳統TMBS裝置之聚合物件隔件之下最大電場。
點2代表在像是圖1中繪示的傳統TMBS裝 置之場板的終端部之下最大電場。
點a代表在圖2中所繪示具有MFRT終端結構的TMBS裝置之溝渠胞元之下最大電場。
點b代表在圖2中繪示具有MFRT終端結構的TMBS裝置之導電隔層之下最大電場。
點3代表在圖2中所繪示具有MFRT終端結構的TMBS裝置之場板的終端部之下最大電場。
類似於圖3，圖4闡述在圖1繪示的傳統裝置及圖2繪示的裝置之終端結構之下各種位置處的電場。然而，在此範例中場板之長度為5微米。
在圖3及4所繪示的結果指示了傳統裝置和在圖2中繪示的裝置之間主要的差異為在導電隔層和場板之終端部之下電場的值。在傳統TMBS裝置之下最大電場發生在導電隔層之下，特別是當場板之長度為5微米時。在另一方面，在圖2所繪示的TMBS裝置之下最大電場發生在當場板之長度為5微米時溝渠胞元之底部之下。雖然在傳統裝置與圖2所繪示的裝置兩者中最大電場高達4xa105V/cm，但在後者TMBS裝置中終端區域可能不會衝擊裝置的崩潰電壓，由於在位於溝渠胞元之間台面(mesas)上缺乏導電路徑。
當場板之長度為12微米時，在圖2中繪示的裝置能從212V增加崩潰電壓到226V。當場板之長度為5微米時，圖2中繪示的裝置仍能將崩潰電壓保持在約225V，但在傳統裝置中的崩潰電壓被降低到170V。
在圖2中繪示的結構之一個重要的益處為其製造並不需要超出用以製造圖1所繪示傳統TMBS裝置的該些者的任何額外的處理步驟。相較於慣用的邊緣終端技藝，沒有需要額外控制擴散處理或是複雜多重場板設定。舉例來說，用於保護環的溝渠能與在主動區域中的溝渠同時形成。此外，絕緣層125及126彼此能同時形成，並且導電材料140及141能彼此同時沈積。
可採用以形成圖2之TMBS二極體之方法的一個範例將參考圖5~8來說明。在此範例中，蕭基二極體及其終端結構同時形成，雖然此需要並不總是這樣的情形。
圖5為半導體基板200之剖面視圖，其包括具有第一導電類型(例如，n-類型)之摻雜劑的第一層200A以及以第一導電類型(例如，n+類型)較重地摻雜的來基底基板(base substrate)200B。氧化物層201係藉由化學汽相沈積(CVD；chemical vapor deposition)形成在第一基板200A上，例如到約2000-10,000埃(angstroms)的厚度。接下來，光蝕刻(未繪示)被塗佈在氧化物層201上，以在主動區域中界定一或以上的主動區域溝渠210、在終端區域中複數個溝渠胞元211以及亦在終端區域中的終端溝渠220。在此範例中，繪示了三個溝渠211，雖然本領域具有通常知識者將認定可使用同樣的製程來形成具有任何數目的溝渠的裝置。溝渠胞元211藉由台面215彼此相隔並且溝渠胞元211藉由台面 216與終端溝渠220分開。此外，台面214將主動胞元210彼此分開，並將溝渠胞元211與彼此鄰接的主動胞元210分開。在一範例中，主動區域溝渠210之各者在寬度上約0.2~2.0微米。在一範例中，終端溝渠220具有12μm的寬度並且保護環溝渠具有0.5μm的寬度。
參照到圖6，在移除氧化物層201之後，進行高溫氧化製程以形成閘極氧化物層225及終端氧化物層226。氧化物層225及226，其在一些範例中具有約150埃與3000埃之間的厚度，形成在主動溝渠210、溝渠胞元211及終端溝渠220之側壁及底部上。在所有各種溝渠形成一層的氧化物層225及226可在單一製程中同時形成。替代氧化製程，氧化物層225及226可藉由高溫沈積來形成，用以形成HTO(高溫氧化物沈積)層。
接著，亦參照到圖6，第一導電層240係藉由CVD形成在例如氧化物225及226上，並且填充主動溝渠210、終端溝渠220及溝渠胞元211以及台面214、215和216。第一導電層240具有厚度使得其在台面215及216之上延伸第一導電層240可為任何適合的材料，諸如金屬、摻雜的多晶矽(doped-polysilicon)或摻雜的非晶矽(doped-amorphous silicon)。第一導電層240可具有約0.5到3.0微米的厚度。為了防止空孔(void)形成在溝渠210之內部部分，第一導電層240可為藉由LPCVD(低壓CVD)形成的多晶矽，其具有良好的步階覆蓋(step coverage)。然而，在一些情形中，非晶矽比多晶 矽可較佳的能消除空孔。為了製作非晶矽導電，可採用再結晶(recrystallization)製程。
現參照到圖7，進行各向異性蝕刻(anisotropic etching)以移除過剩的第一導電層240。在此蝕刻製程期間，從終端溝渠220移除導電材料，但排除用於導電隔層242，其係形成在最接近溝渠胞元211的終端溝渠220之側壁上成為一層的終端氧化物層226上。在一些範例中，導電隔層242具有約等於終端溝渠220之高度的寬度(沿著所繪示的剖面視圖)。
介電層250接著使用蝕刻製程形成在終端區域中。介電層250可例如為TEOS層，諸如LPTEOS或PETEOS層或是O3-TEOS或HTO層。在一些範例中，介電層250之厚度可在約0.2~1.0微米之間。介電層250覆蓋最接近主動區域溝渠胞元211之一部分和在溝渠胞元211之間(亦即，台面215)及在終端溝渠120與溝渠胞元211之間(亦即，台面216)的第一層210A的部分。介電層250亦覆蓋終端溝渠220且接觸導電隔層242之側壁。然而，導電隔層242之最頂表面230仍然是曝露。
下一步，圖8為進行濺射(sputtering)或其它適合的製程以在整體結構之上沈積第二導電層165以致在台面114上形成蕭基接觸區域260。第二導電層165可能以在下面的第一層100A自形成蕭基二極體的任何材料來形成。例如，第二導電層165可為金屬矽化物層。最後，陰極電極170係沈積在基板100B的背側。
範例
藉由闡述的方式，各種結構維度及參數將針對包括四個溝渠胞元的本發明之特定實施例來載明。在此實施例中，終端溝渠120具有範圍從10~50微米的寬度及可相同或不同於在主動區域中溝渠110深度的深度。取決於特定設計及所欲的裝置特性(例如，電壓能力(voltage capability)、速度、漏電流)，終端溝渠120之深度可從0.5~10微米的範圍。位在終端溝渠120中的介電層150可為具有約1500~15,000埃之間厚度的二氧化矽層，其取決於需要的阻斷電壓和材料之組成。
溝渠胞元可具有在0.2與2.0微米之間的寬度和在0.5與10微米之間的深度。溝渠胞元之寬度及深度可相同或不同於彼此。由導電層165延伸進入終端區域所界定的場板在終端溝渠120中可具有約5與50微米長度。
於此說明的MFRT終端結構提供許多好處。例如，藉由在終端結構之上重新分佈電場，導電隔層將不會為影響裝置之崩潰電壓的關鍵點。結果是，終端結構之崩潰電壓承受能力(breakdown voltage sustaining capability)將類似於主動區域之崩潰電壓承受能力。再者，若在可採用來形成場板的溼金屬蝕刻製程(wet metal etching process)期間有任何控制問題，在導電隔層之下的電場和場板之末稍端部仍能維持在可接受的準位且將不 會影響崩潰電壓。
應注意，於此說明的MFRT終端結構可被使用與排除TMBS二極體的裝置連接，其已僅藉由闡述的方式提出。舉例來說，終端結構能應用到任何功率電晶體，像是雙倍的擴散金氧半導體場效電晶體(DMOSFET；diffused metal-oxide-semiconductor field effect transistor)、絕緣閘極雙極電晶體(IGBT；insulated gate bipolar transistor)以及其它溝渠MOS裝置。
將了解的是，空間關係術語，像是「頂部」、「底部」、「上方(above)」、「上部(upper)」、「下面(beneath)」、「下方(below)」、「下部(lower)」等，可於此使用為了方便說明來描述如在圖中所闡述一個元件或特徵對另一個元件或特徵的關係。將了解，空間關係術語打算包含使用中的裝置的不同方向或除了在圖中描繪的方向之外的操作。例如，若在圖中的裝置被翻轉，說明為在其它元件或特徵的「下方」或「下面」接著會被定向為在其它元件或特徵的「上方」。因此，示例性術語「上方」可包含上方及下方的方向兩者。
雖然各種實施例被具體的闡述及說明於此，將理解的是，本發明之修改及變異係由上方教示所涵蓋，並且在不悖離本發明之精神及意指的範疇下係在所附申請專利範圍之範圍內。

Claims (19)

  1. 一種半導體裝置的終端結構，該終端結構包含：半導體基板，具有主動區域與終端區域；複數個溝渠胞元，位在該終端區域中且自該主動區域之邊界朝向該半導體基板之邊緣延伸；終端溝渠，形成在該終端區域中，在該複數個溝渠胞元遠離開該主動區域之一側上；導電隔層，位在相鄰該終端溝渠最接近該複數個溝渠胞元的側壁；第一氧化物層，形成在該終端溝渠中且接觸該導電隔層之側壁；第一導電層，形成在該半導體基板之背側表面上；以及第二導電層，形成在該主動區域及該終端區域的頂上。
  2. 如申請專利範圍第1項的終端結構，更包含沿著該溝渠胞元及該終端溝渠之側壁及底部表面的第二氧化物層，該導電隔層與該第二氧化物層接觸於該終端溝渠之側壁及底部表面上。
  3. 如申請專利範圍第2項的終端結構，更包含第三氧化物層，位在配置於相鄰溝渠胞元之間的台面上，並且更位在該第二導電層與該半導體基板之間。
  4. 如申請專利範圍第1項的終端結構，其中該半導體裝置為蕭基二極體。
  5. 如申請專利範圍第4項的終端結構，其中該蕭基二極體為TMBS蕭基二極體，其在該基板之主動區域中包括至少一溝渠。
  6. 如申請專利範圍第2項的終端結構，其中該溝渠胞元係填充以導電材料。
  7. 如申請專利範圍第1項的終端結構，其中該第二導電層延伸為連續層，其延伸進入該溝渠胞元和該終端溝渠之至少一部分，使得該第二導電層及該導電隔層彼此電耦接。
  8. 一種以電晶體來建置的裝置，其中該裝置係選自功率電晶體與整流器所組成的群組，且其中該裝置採用如申請專利範圍第1~7項之任一項的終端結構。
  9. 一種半導體裝置，包含：半導體基板，具有至少一溝渠MOS裝置，其位在該半導體基板之主動區域中；複數個溝渠胞元，位在鄰接於該半導體基板之主動區域的該半導體基板之終端區域中，該複數個溝渠胞元自該主動及終端區域之間的邊界朝向該半導體基板的邊緣延伸；終端溝渠，形成在該終端區域中，在該複數個溝渠胞元遠離開該主動區域之一側上；第一氧化物層，沿著該複數個溝渠胞元和該終端溝渠上形成；導電隔層，位在相鄰該終端溝渠最接近該複數個溝渠 胞元的側壁；第二氧化物層，形成在該終端溝渠中且接觸該導電隔層的側壁；第一導電層，形成在該半導體基板的背側表面上；以及第二導電層，位在該主動區域及該終端區域的頂上，該第二導電層之一部分位在界定場板的該終端區域中。
  10. 如申請專利範圍第9項的半導體裝置，其中該半導體基板包含第一層及基底層，並且該第一層具有輕摻雜的第一類型導電雜質，且該基底基板具有重摻雜的該第一類型導電雜質。
  11. 如申請專利範圍第9項的半導體裝置，其中該溝渠MOS裝置及該終端溝渠形成在該第一層中且具有在約0.5~10.0微米之間的深度。
  12. 如申請專利範圍第9項的半導體裝置，其中該終端溝渠具有在約10~50微米之間的寬度。
  13. 如申請專利範圍第9項的半導體裝置，更包含第三氧化物層，其位在配置於相鄰溝渠胞元之間的台面，並且更位在該第二導電層與該半導體基板之間。
  14. 如申請專利範圍第9項的半導體裝置，其中該半導體裝置為蕭基二極體。
  15. 如申請專利範圍第14項的半導體裝置，其中該蕭基二極體為TMBS蕭基二極體，其包括在該基板之主動區域中的至少一溝渠。
  16. 如申請專利範圍第9項的半導體裝置，其中該溝渠胞元係填充以導電材料。
  17. 如申請專利範圍第9項的半導體裝置，其中該第二導電層延伸為連續層，其延伸進入該溝渠胞元及該終端溝渠之至少一部分，使得該第二導電層及該導電隔層彼此電耦接。
  18. 一種形成半導體裝置的方法，包含：形成位在半導體基板之主動區域中的至少一溝渠MOS裝置；形成位在鄰接該半導體基板之主動區域的該半導體基板之終端區域中的複數個溝渠胞元，該複數個溝渠胞元從在該主動及終端區域之間的邊界朝向該半導體基板之邊緣延伸；在該半導體基板之終端區域中該複數個溝渠胞元遠端開該主動區域之一側上形成終端溝渠；形成導電隔層，其位在相鄰該終端溝渠最接近該複數個溝渠胞元的側壁；在接觸該導電隔層之側壁的該終端溝渠中形成第一氧化物層；在該半導體基板之背側表面上形成第一導電層；以及在該主動區域頂上形成第二導電層；以及在該終端區域中形成場板。
  19. 如申請專利範圍第18項的方法，其中形成該場板包括形成該第二導電層進入該終端溝渠的延伸。
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