CN105870089A - 可靠的互连 - Google Patents

可靠的互连 Download PDF

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Publication number
CN105870089A
CN105870089A CN201610076079.5A CN201610076079A CN105870089A CN 105870089 A CN105870089 A CN 105870089A CN 201610076079 A CN201610076079 A CN 201610076079A CN 105870089 A CN105870089 A CN 105870089A
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China
Prior art keywords
contact area
cushion
layer
barrier layer
opening
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CN201610076079.5A
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CN105870089B (zh
Inventor
黄锐
胡振鸿
迪马·巴巴澜·小安东尼奥
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United Test and Assembly Center Ltd
UTAC Headquarters Pte Ltd
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UTAC Headquarters Pte Ltd
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Abstract

本发明公开一种器件和形成器件的方法。该器件包括设置在该器件的最后互连级上面的接触区。该器件包括具有至少开口的最终钝化层和至少设置在接触区的顶表面的第一暴露部分上面的缓冲层，所述开口至少部分暴露接触区的顶表面。当导电互连件耦合至接触区时，缓冲层吸收经施加形成导电互连件和接触区之间的互连的力的一部分。

Description

可靠的互连
背景技术
提供低成本的集成电路(IC)以满足客户期望一直是人们的愿望。此外，总是存在通过降低信号传播路径的RC时间常数以提高信号传输速度来提供高速IC的需求。然而，当提供高速IC时，IC的电气或机械可靠性，尤其是IC的互连会受到损害。
基于上述讨论，希望提供可靠的互连以及提供简化和低成本的方法以形成此类可靠的互连。
发明内容
实施例主要涉及半导体器件和形成半导体器件的方法。在一个实施例中，公开了一种器件。该器件包括设置在该器件的最后互连级上面的接触区。该器件包括具有至少开口的最终钝化层和至少设置在接触区的顶表面的第一暴露部分上面的缓冲层，所述开口至少部分暴露接触区的顶表面。当导电互连件耦合至接触区时，缓冲层吸收经施加形成导电互连件和接触区之间的互连的力的一部分。
在另一实施例中，涉及一种器件。该器件包括设置在该器件的最后互连级上面的接触区和缓冲层。接触区和缓冲层适应导电互连。该器件还包括具有至少开口的最终钝化层，所述开口至少部分暴露接触区的顶表面。当导电互连件耦合至接触区时，缓冲层吸收经施加形成导电互连件和接触区之间的互连的力的一部分。
在又另一实施例中，涉及用于形成一种器件的方法。接触区在该器件的最后互连级上面形成。形成具有至少开口的最终钝化层，所述开口至少部分暴露接触区的顶表面。该方法还包括至少在接触区的顶表面的第一暴露部分上面形成缓冲层。当导电互连件耦合至接触区时，缓冲层吸收经施加形成导电互连件和接触区之间的互连的力的一部分。
通过参考下面的具体实施方式和附图，本文公开的实施例的这些和其他优点和特征将变得显而易见。此外，应当理解，本文所述的各个实施例的特征不是互相排斥的，并且可以存在于各个实施例的组合排列中。
附图说明
在附图中，相同的附图标号通常指的是所有不同视图中的相同部件。而且，所述附图不一定按比例绘制，而是绘出重点以便清晰说明本发明的原理。在下列具体实施方式中，本发明的各个实施例参考下列附图来描述，其中：
图1示出半导体封装的实施例的简化剖视图；
图2-11示出半导体封装的一部分的各种实施例；以及
图12a-12e和图13a-13e示出形成半导体封装的工艺的各种实施例。
具体实施例
各实施例主要涉及半导体封装。例如，封装具有耦合至导电互连件(诸如但不限于导线键合件)的接触区。在一些实施例中，至少一个接触区包括设置在其上面的缓冲层。例如，接触区可以与铜导线键合。此类半导体封装广泛用在电子器件中。例如，所述器件可以是存储器器件、无线通信器件或汽车控制器件。所述器件可以并入消费产品，诸如消费电子产品中。将器件并入其他应用中也是可用的。
图1示出半导体封装的简化剖视图。如图1所示的半导体封装100包括封装基板101。封装基板包括第一主表面101a和第二主表面101b。第一主表面101a例如可称为顶表面，以及第二主表面101b例如可称为底表面。所述表面也可用其他名称。封装基板可以是单层基板或多层基板。各种材料，包括但不限于PCB基板、聚合物、陶瓷、半导体、金属等可以用于形成封装基板。封装基板包括多个导电迹线和通路触点(未示出)和设置在例如封装基板的第一主表面上的非裸片附接区105b的多个接触/键合焊盘132。
半导体裸片或芯片110使用粘合剂120安装在封装基板的裸片附接区105a上。半导体芯片可以是任何合适类型的半导体芯片。如图所示，所述裸片包括有效主表面110a和无效主表面110b。有效表面110a包括接触区113。在一个实施例中，接触区包括裸片焊盘。接触区设有通向裸片的内部线路(未示出)的入口。如图所示，裸片焊盘位于裸片的有效主表面和周边上。在裸片的其他位置提供裸片焊盘也是可用的。最终钝化层117设置在裸片的有效表面并覆盖该有效表面，诸如图1中所示出的，除了设置裸片焊盘的位置以外。如图所示，最终钝化层117可包括至少部分暴露所述裸片焊盘的开口119。
在一个实施例中，裸片通过导电互连件电连接至封装基板。在一个实施例中，导电互连件包括导线键合件。其他合适类型的导电互连件也是可用的。在一个实施例中，导线键合件包括导线145。在一个实施例中，导线包括铜、金、银、钯铜或它们的任何合金的导线。任何其他合适类型的导电材料也可以用于导线。所述导线例如附接至裸片的裸片焊盘和附接至设置在封装基板的第一主表面上的非裸片附接区105b上的接触焊盘132。在一个实施例中，导线键合件的第一端145a键合至裸片焊盘以便形成球形键合件146，而导线键合件的第二端145b键合至接触焊盘以便形成针脚或楔形键合147，如图1所示。其他合适类型的导线键合构造也是可用的。例如，所述导线键合构造包括但不限于隔离针脚式键合(stand-off stitch bond，SSB)、反向隔离针脚式键合(RSSB)等。
图2更详细示出根据一个实施例的半导体封装200的部分A的简化剖视图。如图所示，最终钝化层117设置在裸片的除了设置接触区113(诸如裸片焊盘)的位置以外的有效表面上并覆盖所述有效表面。最终钝化层包括开口119，所述开口至少部分暴露裸片焊盘113的顶表面113a。最终钝化层例如包括电介质材料，诸如二氧化硅(SiO2)或氮化硅。其他合适类型的电介质材料也是可用的。接触区例如包括金属接触焊盘，诸如铝(Al)、铜或其合金。其他合适类型的导电材料也可用于所述接触区。
在一个实施例中，缓冲层250设置在接触区113上。在一个实施例中，缓冲层250覆盖所述接触区的暴露表面的一部分。如图2所示，未被缓冲层覆盖的裸片焊盘的暴露顶表面部分保留暴露。缓冲层例如设置在裸片焊盘的暴露表面的中心部分上面。缓冲层也可设置在接触区的其他部分，只要它允许形成接触区和导电互连件之间的电耦合。例如，缓冲层可设置在裸片焊盘的暴露表面上的任何合适位置，只要它在导线键合工艺中允许裸片焊盘和导线键合件之间的电接触。在一个实施例中，缓冲层包括当力施加在其上面时可变形的柔性材料。例如，缓冲层包括聚酰亚胺、B-阶段材料、具有填料的聚合物等。其他合适类型的柔性材料也是可用的。
参考图2，阻挡层260设置在最终钝化层117上并衬砌最终钝化层的开口。在一个实施例中，阻挡层260设置在最终钝化层的顶表面117a的一部分上并衬砌开口119，所述开口包括所述开口的侧壁以及接触区的暴露部分并覆盖缓冲层250。在一个实施例中，阻挡层包括单层阻挡层。在其他实施例中，阻挡层包括具有不止一层阻挡层的多层叠堆。在一个实施例中，阻挡层包括可以防止导电互连件的材料扩散到接触区下面的层中并为导电互连件提供可键合表面的任何合适类型的材料。例如，阻挡层包括可以防止铜扩散并提供用于铜导线键合的可键合表面的材料，诸如镍、钯、金、锌、及其合金等。
在一些其他实施例中，可选地，在最终钝化层的顶表面117a的一部分上设置额外的缓冲层255。该额外的缓冲层255可包括与缓冲层250相同或不同的缓冲材料。
如图2所示，导电互连件，诸如具有球形键合件146的导线键合件的第一端145a键合至接触区，诸如裸片焊盘113。在一个实施例中，球形键合件146接触阻挡层260的设置在最终钝化层117的开口119内的部分。在一个实施例中，球形键合件146的一部分设置在缓冲层250上，球形键合件146的剩余部分设置在裸片焊盘113的暴露部分上面并接触阻挡层260。在键合工艺中，缓冲层250变形以便吸收施加在导电互连件(诸如导线键合件)和阻挡层之间以形成金属间键合件的力或能量的一部分。这允许导电互连件和待形成的接触区之间的可靠电气和机械互连，而不会损坏半导体裸片的内部线路(包括接触区下面的金属互连网络、层间电介质材料或半导体材料)。此外，阻挡层防止导电互连件的材料扩散到接触区下面的层中并为导电互连件提供可键合表面。这避免降低载体使用寿命并维持集成电路的高传输速度。
图3-11更详细示出根据各个实施例的半导体封装的部分A的简化剖视图。在图3-11中示出的半导体封装的每个部分和图2中示出的半导体封装200的部分不同之处在于一个或几个方面。共用元件可不描述或详细描述。为简洁起见，下面的图3-11的描述主要专注于半导体封装的每个部分相对于图2所示半导体封装200的部分的差异。
如图3所示的半导体封装300的部分A’示出设置在裸片的有效表面并覆盖裸片的有效表面的最终钝化层117。最终钝化层117包括开口119，所述开口至少部分暴露接触区(诸如裸片焊盘113)的顶表面113a。如图3所示，缓冲层350设置在接触区113上面。缓冲层350覆盖接触区113的一部分。在一个实施例中，开口或缺口在缓冲层350内形成，以便确保接触区和导电互连件之间的可靠电耦合。阻挡层260设置在最终钝化层的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁以及接触区的暴露部分并覆盖缓冲层250。例如，最终钝化层、接触区、缓冲层和阻挡层包括如图2所述的这些层的任何合适的材料。
如图3所示的缓冲层350包括相对于图2所示的缓冲层250具有不同形状和形式的缓冲层。在一个实施例中，缓冲层350包括具有布置在接触区113上面的多个缓冲区的第一形式350a。在一个实施例中，第一形式350a的多个缓冲区包括多个正方形缓冲区351。正方形缓冲区例如包括相同大小。正方形缓冲区例如布置在3x3的阵列中。为多个缓冲区提供其他合适形状或其他合适尺寸和其他构造/布置也是可用的。在另一实施例中，缓冲区350包括具有圆形形状的第二形式350b。圆形形状的缓冲区350b例如包括环形形状。缓冲区350b例如包括形成暴露接触区113的一部分的中空区域的外径352o和内径352i。
在其他实施例中，缓冲层包括第三形式350c或第四形式350d。在一个实施例中，缓冲层的第三形式350c包括类似于井号(#)形状或符号的图案，而在一个实施例中，第四形式350d包括类似于交叉(X)形状或符号的图案。其他合适类型的图案也是可用的。应当理解，缓冲层350可图案化或构造为具有各种形式并且可设置在接触区上面的任何合适位置上面，只要它允许在接触区和导电互连件之间电接触并提供最大缓冲效果。
图4和5更详细示出半导体封装400和500的部分A’的不同实施例。如图4和5所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区(诸如裸片焊盘113)的顶表面113a。如图4和5所示，缓冲层450或550设置在接触区113上面。缓冲层450或550覆盖接触区113的一部分。阻挡层260设置在最终钝化层的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁以及接触区的暴露部分并覆盖缓冲层450或550。例如，最终钝化层、接触区、缓冲层和阻挡层包括如图2所述的这些层的任何合适的材料。
如图4和5所示的缓冲层450或550包括相对于图2所示的缓冲层250具有不同轮廓的上表面的缓冲层。如图2所示，缓冲层250包括顶部平面或平坦的表面。在一个实施例中，缓冲层450包括具有如图4所示的凸状轮廓的顶表面。在另一实施例中，缓冲层550的顶表面包括如图5所示的凹状轮廓。根据各种因素诸如缓冲层的材料及其处理技术，缓冲层的顶表面可具有其他合适的轮廓。例如，如果缓冲层由B-阶段材料制成，则可在其顶表面形成凹状或凸状轮廓。在形成缓冲层期间，此类非平面或非平坦表面轮廓也可通过点胶、丝网印刷、固化、压印工艺或它们的组合来形成。
图6和7更详细示出半导体封装600和700的部分A’的各种其他实施例。如图6和7所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区(诸如裸片焊盘113)的顶表面113a。最终钝化层和接触区例如包括如图2所述的这些层的任何合适材料。
不同于如图2所示的部分200，部分600或700包括设置在最终钝化层117的顶表面117a的一部分上面的导电层670。如图6和7所示，导电层670设置在最终钝化层的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁以及接触区113的暴露部分。在一个实施例中，导电层接触所述接触区的暴露部分。在一个实施例中，导电层670包括单层导电层。导电层可包括具有不止一层导电层的多层叠堆。在一个实施例中，导电层670充当种子层。导电层670可包括可以充当沉积阻挡层的种子层的任何合适类型的材料，如下文所述。例如，导电层包括铜、铝铜等。其他合适的导电材料也是可用的，只要它在下面的接触区和最终钝化层以及覆盖在它上面的阻挡层之间具有良好的粘性。
在一个实施例中，缓冲层650设置在导电层670上面。在一个实施例中，缓冲层650覆盖导电层670的一部分，其覆盖接触区的暴露表面的一部分。缓冲层650例如包括如图2所述的缓冲层250的合适缓冲材料。因此，共用元件可不描述或详细描述。
在一个实施例中，阻挡层660或760设置在导电层670和缓冲层650上面。阻挡层660或760例如包括如图2所述的阻挡层260的合适材料。在一个实施例中，阻挡层660是如图6所示的局部共形势垒层阻挡层。阻挡层660的上表面包括局部或完全共形于下面层的形貌特征的轮廓。例如，阻挡层660的上表面共形于导电层的边缘并包括具有与最终钝化层的顶表面基本共面的底部的凹陷部。在另一实施例中，阻挡层760的上表面包括如图7所示为平面或平坦的上表面。阻挡层760例如设置在导电层上面并完全填充剩余开口并覆盖缓冲层650。
图8更详细示出半导体封装800的部分A’的另一实施例。如图8所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区(诸如裸片焊盘113)的顶表面113a。最终钝化层和接触区例如包括如图2所述的这些层的任何合适材料。例如，接触区113包括金属接触焊盘。
不同于如图2所示的部分200，部分800包括设置在最终钝化层117的顶表面117a的一部分上面的缓冲层850。如图8所示，缓冲层850设置在最终钝化层的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁以及接触区113的暴露部分。在一个实施例中，缓冲层850接触所述接触区的暴露部分。在一个实施例中，缓冲层850包括具有填料的缓冲层。在一个实施例中，缓冲层包括如图2所示的柔性材料并且还包括多种填充材料857。所述柔性材料例如包括聚合物，而填充材料包括导电粒子或柱石，诸如银、铜或其合金。其他合适的材料也是可用的。
在一个实施例中，阻挡层860设置在缓冲层850上面。阻挡层860例如包括如图2所述的阻挡层260的合适材料。在一个实施例中，阻挡层860是如图8所示的共形阻挡层。阻挡层860的上表面包括共形于下面层的形貌特征的轮廓。阻挡层860的上表面也可包括其他合适的轮廓，诸如与下面层的形貌特征不共形的轮廓。
图9更详细示出半导体封装900的部分A’的另一实施例。如图9所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区913的顶表面913a。最终钝化层例如包括如图2所述的该层的任何合适材料。
不同于如图2所示的部分200，部分900的接触区913不是金属接触焊盘。在一个实施例中，接触区是具有填料957的缓冲层950。在该实施例中，具有填料的缓冲层充当用于设置在其上面的导电互连件的接触区。这允许形成更薄和简化的半导体封装。具有填料的缓冲层950例如包括与上述图8相同的柔性和填充材料。在一个实施例中，阻挡层960直接设置在具有带有填料957的缓冲层950的接触区913上面。阻挡层960例如包括如图2所述的阻挡层260的合适材料。在一个实施例中，阻挡层960是如图9所示的共形阻挡层。在一个实施例中，阻挡层960设置在最终钝化层117的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁并且覆盖接触区913a的暴露的顶表面。
例如，如上述图8和9的具有填料的缓冲层的运用使得当按压缓冲层时，在导电互连件和具有填料的缓冲层之间建立电耦合。
图10更详细示出半导体封装1000的部分A’的另一实施例。如图10所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区(诸如裸片焊盘113)的顶表面113a。最终钝化层和接触区例如包括如图2所述的这些层的任何合适材料。例如，接触区113包括金属接触焊盘。
不同于如图2所示的部分200，部分1000包括设置在开口119内并覆盖接触区113的缓冲层1050。在一个实施例中，缓冲层1050设置在接触区的暴露顶表面上面并接触所述开口的侧壁。在一个实施例中，缓冲层1050包括用于半导体应用的高强度和刚度、高电荷迁移率、高热导率或高导电性、低电阻和机械顺从性的材料。在一个实施例中，导电层1050包括石墨烯或碳纳米管层。例如，碳纳米管层在10纳米至几毫米的长度内没有晶界。相对于具有金属粒子的缓冲材料，这允许优异的可变形性和弹性以及顺应性。其他具有该性质的合适材料也是可用的。在该实施例中，缓冲层1050本身也起阻挡层的作用。这样，没有阻挡层设置在缓冲层和/或接触区上面。
图11更详细示出半导体封装1100的部分A’的另一实施例。如图9所示，最终钝化层117设置在裸片的有效表面并覆盖裸片的有效表面。最终钝化层117包括开口119，所述开口至少部分暴露接触区113的顶表面113a。最终钝化层和接触区例如包括如图2所述的这些层的任何合适材料。
缓冲层1150设置在接触区的暴露表面的一部分上面，如图11所示。在一个实施例中，不同于如图2所示的部分200，部分1100的缓冲层1150包括与图10所述相同的材料。因此，将不描述缓冲层1150的材料。类似于部分200，阻挡层260设置在最终钝化层117的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁并且覆盖接触区113a的暴露顶表面。
如图2-11所述的实施例示出具有不同构造的缓冲层、阻挡层或接触区的半导体的一部分。应当理解，如图2-11所述的任一实施例可经更改或重新布置以包括如图2-11所述的特征结构的不同组合。
图12a-12e示出用于形成半导体封装的一部分的工艺1200的实施例。所形成的半导体封装的所述部分类似于如图2所述的部分。共用元件可不描述或详细描述。如图所示，提供局部处理的基板。所述局部处理的基板可以是晶片或半导体裸片或芯片的形式。所述局部处理的基板包括基板和经处理直至例如半导体裸片或晶片110的互连级的最后金属层(未示出)的多级金属层。不同级的金属层通过多层电介质层分开。基板包括半导体材料，诸如硅，并具有电路部件(未示出)诸如在其上形成的晶体管。根据互连级的水平，金属层包括例如铜、钨或其合金，而电介质层包括合适的电介质材料诸如SiO2。局部处理的基板使用线路技术的任何合适前端和后端来处理，因此，不再描述或详细描述。
具有最后金属层和电介质层的最后互连级用导电层覆盖。在一个实施例中，导电层包括金属层。例如，金属层包括铝、铜或其合金。导电层通过合适的沉积技术、诸如物理气相沉积(PVD)、化学气相沉积(CVD)或原子层沉积(ALD)在最后互连级上面形成。其他合适的沉积技术也是可用的。导电层可通过合适的掩膜和蚀刻技术经图案化以形成多个接触区113。在一个实施例中，接触区113是裸片焊盘。接触区容纳电连接至封装基板(未示出)的导电互连件(未示出)，并提供进入裸片内部线路(未示出)的入口。在一个实施例中，导电互连件是导线键合件。其他合适类型的导电互连件也是可用的。应当理解，可选地，电测试通过探测在这一阶段的接触区来执行。
参考图12a，最终钝化层117是沉积在接触区113上面的覆盖层。最终钝化层例如包括电介质材料，诸如SiO2。最终钝化层通过CVD或PVD沉积在接触区113上面。其他合适类型的电介质材料和沉积技术也是可用的。最终钝化层具有足够的厚度并覆盖接触区。该工艺继续以在最终钝化层117中形成开口119。例如，最终钝化层117经图案化以形成开口119，所述开口至少部分暴露接触区113的顶表面113a。所述图案化包括合适的掩膜和蚀刻技术。例如，开口的宽度小于接触区的宽度。用于开口的其他合适构造也是可用的。应当理解，在钝化层中形成开口后可执行电测试，其中，探头掩膜可在这一阶段的接触区中形成。
参考图12b，缓冲层1250沉积在局部处理的基板110上面。在一个实施例中，缓冲层是沉积在最终钝化层的顶表面117上面、衬砌开口119的侧壁以及在接触区的暴露顶表面113a上面的覆盖层。缓冲层1250通过CVD工艺在局部处理的基板110上面形成。在一个实施例中，缓冲层包括当力施加在其上面时可变形的柔性材料。例如，缓冲层包括聚酰亚胺、B-阶段材料、具有填料的聚合物等。也可以采用其他合适类型的柔性材料和其他合适的沉积技术。缓冲层1250例如包括比最终钝化层的厚度更薄的厚度。其他合适的厚度尺寸可经采用用于缓冲层。
该工艺继续图案化缓冲层1250以形成如图12c所示的各个缓冲层250。为形成该各个缓冲层250，可以采用掩膜和蚀刻技术。例如，可以使用诸如光刻胶的软掩膜(未示出)。光刻胶例如可以通过各种技术(诸如旋涂)来形成。其他技术也是可用的。掩膜层经选择性暴露和生长以形成对应于各个缓冲层的图案的预期图案。在一个实施例中，掩膜包括保护或覆盖缓冲层1250的定义各个缓冲层250的部分。未被掩膜图案覆盖的缓冲层1250的暴露部分通过例如蚀刻来去除。用于形成具有期望图案的缓冲层的其他合适技术也是可用的。例如，丝印或点胶也可用于形成具有期望图案的缓冲层。
在一个实施例中，设置在接触区113上面和开口119内的缓冲层1250的部分通过图案化工艺中的掩膜来保护。在一个实施例中，图案化缓冲层250覆盖接触区的暴露区域的一部分，而未被缓冲层250覆盖的接触区的暴露顶表面部分保留暴露。在一个实施例中，图案化缓冲层包括上平面表面，并设置在接触区的暴露表面的中心部分上面。形成具有其他期望图案或轮廓的缓冲层以及在接触区的暴露表面的其他位置形成所述缓冲层也是可用的，只要它允许在接触区和后续处理工艺中的导电互连件之间形成电耦合。另选地，缓冲层1250可被图案化，使得缓冲层的部分保留在开口119内以及在最终钝化层117的顶表面117a的部分上面。在另一实施例中，缓冲层经形成以诸如完全覆盖由电测试引起的探针掩膜。
参考图12d，阻挡层1260在局部处理的基板110上面形成。在一个实施例中，阻挡层1260是沉积在最终钝化层的顶表面117上面、衬砌开口119的侧壁以及在接触区的暴露顶表面113a上面并覆盖缓冲层250的覆盖层。阻挡层1260通过PVD工艺在局部处理的基板110上面形成。在一个实施例中，阻挡层包括单层阻挡层。在其他实施例中，多层阻挡材料可经沉积以形成多层叠堆。在一个实施例中，阻挡层1260包括可以防止导电互连件扩散到接触区下面的层中并提供用于导电互连件的可键合表面的任何合适类型的材料。例如，阻挡层包括可以防止铜扩散并提供铜导线键合的可键合表面的材料，诸如镍、钯、金、锌、其合金等。阻挡层1260例如可包括任何足够的厚度，只要它能够充当有效阻隔以及提供可键合表面。
该工艺继续以图案化阻挡层1260以形成如图12e所示的各个阻挡层260。为形成各个阻挡层260，可以采用掩膜和蚀刻技术。例如，可以使用诸如光刻胶的软掩膜(未示出)。光刻胶例如可以通过各种技术诸如旋涂来形成。其他技术也是可用的。掩膜层经选择性暴露和生长以形成对应于各个阻挡层的图案的期望图案。在一个实施例中，掩膜包括彼此充分隔离接触区的图案。未被掩膜图案覆盖的阻挡层1260的暴露部分通过例如蚀刻去除。用于图案化阻挡层的其他合适技术也是可用的。
图案化的阻挡层260设置在最终钝化层117上面并衬砌最终钝化层的开口。在一个实施例中，阻挡层260设置在最终钝化层的顶表面117a的一部分上面并衬砌开口119，所述开口包括所述开口的侧壁以及接触区的暴露部分并覆盖缓冲层250。
该工艺继续以形成半导体封装。进一步处理可以包括切割、在接触区上面形成导电互连件、组装和封装。例如，导电互连件，诸如具有球形键合件的导线键合件的第一端可键合至接触区，以便可形成诸如图2所示的半导体封装的一部分。也可执行其他另外的工艺。
如图12a-12e所述的工艺可经更改以形成诸如图3-5和图8-11所述的半导体封装的部分。对于图3所述的部分300，所述工艺可经更改以形成如图12b所述的缓冲层，并且所述缓冲层经图案化以在接触区的暴露表面的一部分上形成期望的形式或图案350a-350d。为形成具有诸如图4或5所示的凸状或凹状上轮廓的缓冲层，如图12b和12c所述的工艺步骤可经更改以包括例如由B阶段材料制成的缓冲层和在形成缓冲层的工艺中采用诸如点胶、丝印、固化、压印工艺或它们的任何组合。至于图8所述的部分800，该工艺可经更改以提供具有填料的缓冲层并且具有填料的缓冲层经图案化使得图案化的缓冲层局部设置在最终钝化层上面、衬砌开口的侧壁并且覆盖接触区的暴露部分。为形成诸如图9所示的具有带有填料的缓冲层的接触区，如图12a所述的工艺步骤可经更改以包括设置在最后互连级上面并经图案化以定义多个接触区的具有填料的缓冲层。另一方面，为形成诸如图10或图11所示的缓冲层，如图12b和12c所述的工艺步骤可经更改以包括用于半导体应用的高强度和刚度、高电荷迁移率和高的热导率或高导电性、低电阻和机械顺应性并经图案化以实现如图10或图11所示的期望图案的缓冲层，诸如石墨烯或碳纳米管层。
图13a-13e示出用于形成半导体封装的一部分的工艺1300的实施例。所形成的半导体封装的所述部分类似于如图7所述的部分。参考图13a，提供局部处理的基板。局部处理的基板在与图12a所述的相同阶段处理。因此，共用元件可不描述或详细描述。
参考图13b，导电层1670沉积在局部处理的基板110上面。在一个实施例中，导电层是沉积在最终钝化层的顶表面117上面、衬砌开口119的侧壁以及在接触区的暴露顶表面113a上面的覆盖层。导电层可经形成以覆盖通过电测试造成的探头掩膜。导电层1670通过PVD工艺在局部处理的基板110上面形成。在一个实施例中，导电层包括单层导电层。多层导电层可经沉积以形成多层的导电叠堆。在一个实施例中，导电层1670充当用于如在后文描述的阻挡层的后续处理的种子层。导电层例如包括铜、铝铜等。也可采用其他合适的导电材料。沉积的导电层1670例如包括充当种子层的足够厚度。一种选择是通过使用电镀工艺，优选通过电解电镀，来增加导电层1670的厚度。
该工艺继续以在局部处理的基板上面形成缓冲层。在一个实施例中，缓冲层650是沉积在导电层1670上面的覆盖层。缓冲层包括合适的材料并由图12b所述的合适技术来形成。因此，将不描述材料和形成技术的细节。缓冲层经处理以形成如图13c所示的各个缓冲层650。为形成各个缓冲层650，可采用掩膜和蚀刻技术。例如，可以使用诸如光刻胶的软掩膜(未示出)。光刻胶例如可以通过各种技术诸如旋涂来形成。其他技术也是可用的。掩膜层经选择性暴露和生长以形成对应于各个缓冲层的图案的预期图案。在一个实施例中，掩膜包括保护或覆盖缓冲层的限定各个缓冲层650的部分。未被掩膜图案覆盖的缓冲层的暴露部分通过例如蚀刻来去除。用于形成具有期望图案的缓冲层的其他合适技术也是可用的。
在一个实施例中，设置在导电层1670和接触区113上面和开口119内的缓冲层的部分通过图案化工艺中的掩膜来保护。在一个实施例中，图案化的缓冲层650设置在导电层1670的在接触区的暴露表面的一部分上面的一部分上面，而未被缓冲层650覆盖的导电层1670的部分保留暴露。在一个实施例中，图案化的缓冲层650包括上平面表面并设置在接触区的暴露表面的中心部分上面。形成具有其他期望图案或轮廓的缓冲层并在接触区的暴露表面的其他位置形成所述缓冲层也是有用的。
参考图13d，阻挡层760在局部处理的基板110上面形成。在一个实施例中，阻挡层760通过镀覆工艺或、PVD和镀覆工艺的组合来形成。例如，也可采用电化学或无电镀来形成阻挡层760。因此，一个或多个层可经镀覆以形成阻挡层。在一个实施例中，具有掩膜图案的镀覆掩膜(未示出)设置在导电层1670上面，阻挡层760可通过电化学镀覆来形成，在该工艺中，导电层充当镀覆电流导电路径。也可使用其他用于形成阻挡层的合适方法。镀覆阻挡层填充剩余开口以及在未被镀覆掩膜保护的最终钝化层的顶表面的部分上面。阻挡层760的镀覆上表面是基本平面或平坦的，如图13d所示。
该工艺继续以图案化导电层1670以形成如图13e所示的各个导电层670。在一个实施例中，导电层的厚度比镀覆的阻挡层更薄。为形成各个导电层670，镀覆的阻挡层760可充当蚀刻掩膜。这避免使用另外的图案化掩膜。该工艺是简化的，因为不需要另外的掩膜，并且导电层的厚度比镀覆的阻挡层更薄，降低了蚀刻时的材料浪费，从而进一步降低生产成本。在一个实施例中，镀覆的阻挡层用作蚀刻掩膜，使得未被镀覆的阻挡层覆盖的导电层的部分通过蚀刻去除。图案化的导电层彼此充分隔离接触区。用于图案化导电层的其他合适技术也是可用的。
该工艺继续以形成半导体封装。进一步处理可以包括切割、在接触区上面形成导电互连件、组装和封装。例如，导电互连件，诸如具有球形键合件的导线键合件的第一端可键合至接触区，以便可形成诸如图7所示的半导体封装的一部分。也可执行其他另外的工艺。
如图13a-13e所述的工艺可经更改以形成诸如图6所述的半导体封装的一部分。对于如图6所述的部分600，该工艺可经更改以形成如图6所述的具有上表面轮廓的镀覆阻挡层。此外，如图13a-13e所述的工艺可经更改以形成诸如图3-5和图8-11所述的半导体封装的部分。这些更改将不描述或详细描述。
图12a-12e和13a-13e所述的实施例包括图2-11所述的一些或全部优点。因此，这些优点将不描述或详细描述。
用于说明目的，所述器件为导线键合类型的器件。应当理解，所述的实施例是灵活的并且也可用于其他类型的器件(包括但不限于倒装芯片类型的器件)。
本发明可在不偏离本发明的精神和本质特征的情况下以其他具体形式实施。因此，上述实施例应视为在各方面是说明性的而不是限制本文所述的本发明。因此，本发明的范围由附属的权利要求表明，而不是由所述的具体实施方式表明，并且等效于本权利要求的范围以及在本权利要求的含义范围内的所有变化应包含在内。

Claims (20)

1.一种器件，包括：
设置在所述器件的最后互连级上面的接触区；
具有至少开口的最终钝化层，所述开口至少部分暴露所述接触区的顶表面；以及
至少设置在所述接触区的顶表面的第一暴露部分上面的缓冲层，
其中，当导电互连件耦合至所述接触区时，所述缓冲层吸收经施加形成所述导电互连件和所述接触区之间的互连的力的一部分。
2.根据权利要求1所述的器件，包括所述导电互连件，其中：
所述接触区是裸片键合焊盘；以及
所述导电互连件是导线键合件。
3.根据权利要求2所述的器件，包括阻挡层，所述阻挡层局部覆盖所述接触区的所述顶表面的第二暴露部分和所述缓冲层。
4.根据权利要求3所述的器件，其中：
所述接触区包括金属接触焊盘，所述金属接触焊盘包括铝、铜或其合金；
所述导线键合件包括铜、金、银、钯铜或其合金；以及
所述阻挡层包括能防止导线键合材料扩散到所述接触区下面的层中、并提供用于所述导线键合的可键合表面的材料。
5.根据权利要求4所述的器件，其中，所述阻挡层包括镍、钯、金、锌或其合金。
6.根据权利要求1所述的器件，其中，所述缓冲层包括具有聚酰亚胺、B-阶段材料或带有填料的聚合物的柔性材料。
7.根据权利要求1所述的器件，其中，所述阻挡层包括正方形形状、环形形状、井号形状或交叉形状。
8.根据权利要求1所述的器件，其中：
所述缓冲层包括B-阶段材料；以及
所述缓冲层包括上部凸状或凹状轮廓。
9.根据权利要求1所述的器件，包括：
设置在所述最终钝化层的顶表面的一部分上面并衬砌所述开口的导电层，所述开口包括所述开口的侧壁以及所述接触区的暴露顶表面；
所述缓冲层设置在所述导电层上面；以及
阻挡层设置在所述导电层和所述缓冲层上面。
10.根据权利要求9所述的器件，其中，所述阻挡层包括基本平坦的上表面。
11.根据权利要求1所述的器件，其中，所述缓冲层覆盖所述接触区的整个暴露的顶表面。
12.根据权利要求11所述的器件，其中，所述缓冲层包括带有填料的缓冲材料，诸如石墨烯或碳纳米管层。
13.一种器件，包括：
设置在所述器件的最后互连级上面的接触区和缓冲层，其中，所述接触区和所述缓冲层适应导电互连件；以及
具有至少开口的最终钝化层，所述开口至少部分暴露所述接触区的顶表面，
其中，当导电互连件耦合至所述接触区时，所述缓冲层吸收经施加形成所述导电互连件和所述接触区之间的互连的力的一部分。
14.根据权利要求13所述的器件，其中，所述缓冲层充当所述接触区。
15.一种形成器件的方法，包括：
在所述器件的最后互连级上面形成接触区；
形成具有至少开口的最终钝化层，所述开口至少部分暴露所述接触区的顶表面；以及
形成至少在所述接触区的顶表面的第一暴露部分上面的缓冲层，
其中，当导电互连件耦合至所述接触区时，所述缓冲层吸收经施加形成所述导电互连件和所述接触区之间的互连的力的一部分。
16.根据权利要求15所述的方法，包括：
在所述最终钝化层上面形成阻挡层，其中，所述阻挡层设置在所述最终钝化层的顶表面上面、衬砌所述开口的侧壁并覆盖所述缓冲层；并且
图案化所述阻挡层以隔离所述接触区和其他区域。
17.根据权利要求15所述的方法，其中，所述缓冲层在所述接触区的所述顶表面的第一暴露部分上面直接形成。
18.根据权利要求15所述的方法，包括在所述最终导电层上面形成导电层，其中，所述导电层设置在所述最终钝化层的顶表面上面、衬砌所述开口的侧壁并覆盖所述接触区。
19.根据权利要求18所述的方法，其中，所述缓冲层在形成所述导电层之后形成。
20.根据权利要求19所述的方法，包括：
在所述最终钝化层上面形成阻挡层，其中，所述阻挡层填充所述开口并覆盖所述缓冲层以及所述接触区的所述顶表面的第二暴露部分；并且
图案化所述阻挡层以隔离所述接触区和其他区域。
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