CN105810729A - 鳍式场效应晶体管及其制造方法 - Google Patents

鳍式场效应晶体管及其制造方法 Download PDF

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CN105810729A
CN105810729A CN201410838568.0A CN201410838568A CN105810729A CN 105810729 A CN105810729 A CN 105810729A CN 201410838568 A CN201410838568 A CN 201410838568A CN 105810729 A CN105810729 A CN 105810729A
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CN105810729B (zh
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许淼
朱慧珑
赵利川
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Institute of Microelectronics of CAS
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Abstract

本发明公开了一种鳍式场效应晶体管的制造方法，包括步骤：提供具有鳍的半导体衬底，鳍之间形成有隔离；在鳍上形成伪栅器件，并覆盖伪栅器件两侧形成层间介质层；去除伪栅极，以形成开口；进行离子注入，在开口下的鳍内形成穿通停止层，同时，在源漏区内侧的鳍中形成反射掺杂层；在开口中形成替代栅。本发明减小了结漏和结电容，有利于改善器件的阈值电压，尤其在器件尺寸不断缩小时，可抑制阈值电压的卷曲，改善器件的短沟道效应。

Description

鳍式场效应晶体管及其制造方法
技术领域
本发明属于半导体制造领域，尤其涉及一种鳍式场效应晶体管及其制造方法。
背景技术
随着半导体器件的高度集成，MOSFET沟道长度不断缩短，一系列在MOSFET长沟道模型中可以忽略的效应变得愈发显著，甚至成为影响器件性能的主导因素，这种现象统称为短沟道效应。短沟道效应会恶化器件的电学性能，如造成栅极阈值电压下降、功耗增加以及信噪比下降等问题。
目前，为了解决短沟道效应的问题，提出了鳍式场效应晶体管(Fin-FET)的立体器件结构，Fin-FET是具有鳍型沟道结构的晶体管，它利用薄鳍的几个表面作为沟道，从而可以防止传统晶体管中的短沟道效应，同时可以增大工作电流。
在Fin-FET的制造工艺中，为了减小源区和漏区之间的漏电流，可以在鳍的下部形成穿通停止层(PTSL,Punch-Though-StopLayer)，通常在形成鳍和隔离之后，通过离子注入来在鳍中形成该穿通停止层，然而，问题在于，由于鳍的边缘处的穿通停止层的掺杂浓度不均匀，在栅长不断缩小后，尤其是小于20nm以后，源区和漏区的漏电流增大，短沟道效应也更加明显。
发明内容
本发明的目的在于克服现有技术中的不足，提供一种鳍式场效应晶体管及其制造方法，减小结漏和结电容，改善短沟道效应。
为实现上述目的，本发明的技术方案为：
一种鳍式场效应晶体管的制造方法，包括步骤：
提供具有鳍的半导体衬底，鳍间形成有隔离；
在鳍上形成伪栅器件，并覆盖伪栅极两侧形成层间介质层；
去除伪栅极，以形成开口；
进行离子注入，在开口下的鳍内形成穿通停止层，同时，在源漏区内侧的鳍中形成反射掺杂层；
在开口中形成替代栅。
可选的，所述离子注入为垂直角度的离子注入。
可选的，离子注入的剂量范围为1E12至1E14cm-2，能量范围为10至150KEV。
可选的，在鳍上分别形成第一类型伪栅器件和第二类型伪栅器件。
可选的，在开口中分别形成第一替代栅和第二替代栅。
此外，本发明还提供了一种鳍式场效应晶体管，包括：
半导体衬底；
衬底上的鳍，鳍间形成有隔离；
鳍上的器件结构；
栅极之下的鳍中的穿通停止层，以及源漏区内侧的鳍中的反射掺杂层，反射掺杂层与穿通停止层具有相同的掺杂类型。
可选的，所述器件结构包括第一类型器件结构和第二类型器件结构。
本发明的鳍式场效应晶体管及其制造方法，在去除伪栅极之后，进行穿通停止层的离子注入，使得穿通停止层仅形成在栅极下的鳍中，而源漏区下并未形成该穿通停止层的掺杂区，从而减小结漏(junctionleakage)和结电容(junctioncapacitance)；在离子注入的同时，由于伪栅器件的侧墙的存在，使得靠近侧墙的离子反射注入至侧墙下源漏区内侧的鳍中，在沟道的两侧形成反射掺杂区，该掺杂区有利于改善器件的阈值电压，尤其在器件尺寸不断缩小时，沟道两侧的反射掺杂区越来越靠近，可抑制阈值电压的卷曲(Vtroll-off)，改善器件的短沟道效应。
附图说明
为了更清楚地说明本发明实施的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本发明的鳍式场效应晶体管的制造方法的流程图；
图2-图10B为根据本发明实施例制造鳍式场效应晶体管的各个制造过程中的截面结构示意图，其中，图2-图10为各个制造过程中晶体管的俯视示意图，图2A-10A为沿俯视图中AA向的截面结构示意图，图5B-10B为沿腐蚀图中BB向的截面结构示意图；
图11为现有技术PTSL晶体管与本发明实施例的PTSL晶体管的鳍中掺杂浓度分布对比示意图；
图12为现有技术PTSL晶体管与本发明实施例的PTSL晶体管的阈值电压卷曲对比示意图。
具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂，下面结合附图对本发明的具体实施方式做详细的说明。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是本发明还可以采用其他不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本发明内涵的情况下做类似推广，因此本发明不受下面公开的具体实施例的限制。
其次，本发明结合示意图进行详细描述，在详述本发明实施例时，为便于说明，表示器件结构的剖面图会不依一般比例作局部放大，而且所述示意图只是示例，其在此不应限制本发明保护的范围。此外，在实际制作中应包含长度、宽度及深度的三维空间尺寸。
需要说明的是，在本发明的附图中，相同序号的附图，如图2和图2A，图6和图6A、图6B，为同一制造过程中晶体管的不同方向的示意图，其中，图2-图10为各个制造过程中晶体管的俯视示意图，图2A-10A为沿俯视图中AA向的截面结构示意图，图5B-10B为沿腐蚀图中BB向的截面结构示意图。
在本发明中，提出了一种鳍式场效应晶体管的制造方法，包括：提供具有鳍的半导体衬底，鳍之间形成有隔离；在鳍上形成伪栅器件，并覆盖伪栅器件两侧形成层间介质层；去除伪栅极，以形成开口；进行离子注入，在开口下的鳍内形成穿通停止层，同时，在源漏区内侧的鳍中形成反射掺杂层；在开口中形成替代栅。
在本发明的技术方案中，在去除伪栅极之后，进行穿通停止层的离子注入，使得穿通停止层仅形成在栅极区域下的鳍中，而源漏区下并未形成该穿通停止层的掺杂区，从而减小结漏(junctionleakage)和结电容(junctioncapacitance)；同时，在离子注入时，由于伪栅器件的侧墙的存在，使得靠近侧墙的离子反射注入至侧墙下源漏区内侧的鳍中，在沟道的两侧形成反射掺杂区，该掺杂区有利于改善器件的阈值电压，尤其在器件尺寸不断缩小时，沟道两侧的反射掺杂区越来越靠近，可抑制阈值电压的卷曲(Vtroll-off)，改善器件的短沟道效应。
为了更好的理解本发明的技术方案和技术效果，以下将结合制造方法的流程示意图图1对具体的实施例进行详细的描述。
在步骤S01，提供具有鳍106的半导体衬底100，鳍106之间形成有隔离108，参考图4和图4A(图4的AA向截面示意图)所示。
在本发明实施例中，所述半导体衬底100可以为Si衬底、Ge衬底、SiGe衬底、SOI(绝缘体上硅，SiliconOnInsulator)或GOI(绝缘体上锗，GermaniumOnInsulator)等，还可以为包括其他元素半导体或化合物半导体的衬底，例如GaAs、InP或SiC等，还可以为叠层结构，例如Si/SiGe等，还可以其他外延结构，例如SGOI(绝缘体上锗硅)等。
在本实施例中，所述半导体衬底100为体硅衬底。
在一个具体的实施例中，可以通过如下步骤来提供鳍102及隔离108。
首先，可以采用传统的方法进行阱掺杂，对于N型器件进行P型粒子的掺杂，对于P型器件，进行N型粒子的掺杂，在体硅的衬底100中形成阱区102，参考图2和图2A(图2的AA向截面示意图)。
接着，在衬底100上形成光敏刻蚀剂层104，而后，采用刻蚀技术，例如RIE(反应离子刻蚀)的方法，刻蚀衬底100来形成鳍106，从而形成了衬底100上的鳍106，如图3和图3A所示；而后，通过溶剂溶解或灰化方式，将光敏刻蚀剂层104去除。
而后，进行二氧化硅的隔离材料的填充，并进行平坦化工艺，如进行化学机械平坦化，而后，可以使用湿法腐蚀，例如使用氢氟酸腐蚀去除一定厚度的二氧化硅的隔离材料，保留部分的隔离材料在鳍106之间，从而形成了隔离108，如图4和图4A所示。
在步骤S02，在鳍上形成伪栅器件，并覆盖伪栅器件两侧形成层间介质层120，参考图7、7A(图7的AA向截面示意图)和7B(图7的BB向截面示意图)所示。
在本发明实施例中，伪栅器件至少包括横跨鳍的伪栅极、鳍两端的源漏区以及伪栅极的侧墙。在本实施例中，分别形成了第一类型伪栅器件和第二类型伪栅器件，第一和第二类型伪栅器件可以互为N型和P型器件、也可以为具有不同阈值电压的同种类型器件。
具体的实施例中，首先，淀积伪栅介质层和伪栅极材料，并进行图案化，如图5和5A(图5的AA向截面示意图)、5B(图5的BB向截面示意图)所示，形成伪栅介质层110及第一伪栅极112、第二伪栅极113，其中，伪栅介质层可以为热氧化层或其他合适的介质材料，伪栅极可以为非晶硅、多晶硅或氧化硅等，本实施例中，伪栅介质层为热氧化层，伪栅极为多晶硅，第一伪栅极112和第二伪栅极113具有不同的栅长，以用于形成不同类型的器件，第一伪栅极112用于形成第一类型伪栅器件，如N型器件，第二伪栅极113用于形成第二类型伪栅器件，如P型器件，可以采用光敏刻蚀剂为掩膜进行图案化或者进行双掩膜或双图案化，来得到两种栅长的伪栅极。
接着，进行氮化硅的淀积，厚度可以为5-20nm，并进行刻蚀，以仅在第一伪栅极和第二伪栅极的侧壁上形成氮化硅的侧墙114，所述侧墙的厚度可以大于10nm，高度小于100nm，如图6、图6A(图6的AA向截面示意图)和6B(图6的BB向截面示意图)所示，在其他实施例中，侧墙还可以为其他材料，侧墙还可以为不同材料的叠层，如氮化硅、氧化硅或氮氧化硅等或他们的组合。
而后，分别进行N型掺杂和P型掺杂，以在鳍的两端分别形成第一源漏区116和第二源漏区117，N型掺杂例如P、As等，P型掺杂剂例如B、In等，可以通过离子注入或外延掺杂来形成源漏区，如图6、图6A和6B所示。至此，形成了本实施例的第一器件和第二器件，第一类型伪栅器件包括横跨一区域的鳍的栅介质层110和其上的第一伪栅极112以及第一伪栅极112两侧的鳍中的第一源漏区116、第一伪栅极112的侧墙114，第二类型伪栅器件包括横跨另一区域的鳍的栅介质层110和其上的第二伪栅极113以及第二伪栅极113两侧的鳍中的第二源漏区117、第二伪栅极的侧墙114。
接着，进行层间介质层的淀积，例如未掺杂的氧化硅(SiO2)、掺杂的氧化硅(如硼硅玻璃、硼磷硅玻璃等)、氮化硅(Si3N4)或其他低k介质材料，而后进行平坦化，例如CMP(化学机械抛光)，直至暴露鳍的上表面，从而形成所述层间介质层(ILD)120，层间介质层120覆盖伪栅极两侧的鳍及隔离。
在步骤S03，去除伪栅极，以形成开口，参考图7、图7A(图7的AA向截面示意图)和7B(图7的BB向截面示意图)所示。
在本实施例中，可以采用湿法腐蚀去除伪栅极和伪栅介质层，在一个实施例中，可以通过四甲基氢氧化铵(TMAH)去除非晶硅的第一伪栅极和第二伪栅极，从而形成第一开口130和第二开口131，该些开口暴露其下的鳍106和隔离108，如图8、图8A(图8的AA向截面示意图)和8B(图8的BB向截面示意图)所示。
在步骤S04，进行离子注入，在开口下的鳍内形成穿通停止层140，同时，在源漏区内侧的鳍中形成反射掺杂层142，参考图9、图9A(图9的AA向截面示意图)和9B(图9的BB向截面示意图)。
在本发明中，在去除伪栅极之后进行穿通停止层的离子注入，对于N型器件，进行P型掺杂剂的注入，例如B、In、BF2等，对于P型器件，进行N型掺杂剂的离子注入，例如P、As等。
在本实施例中，可以分别进行离子注入，并一起进行退火激活，以分别在第一开口130和第二开口131下形成第一穿通停止层140和第二穿通停止层141。在进行离子注入时，离子注入的剂量范围可以为1E12至1E14cm-2，能量范围可以为10至150KEV，可以采用小角度的离子注入，如入射角度在0-6°，在鳍的尺寸不断减小后，优选0角度的离子注入，即垂直鳍的离子注入。部分的粒子从隔离反射进入鳍中，形成了形貌比较陡峭的穿通停止层，该穿通停止层仅形成在了开口区域下的鳍中，即沟道区域下的鳍中，而在源漏区下并未形成该穿通停止层的掺杂区，如图9、9A和9B所示，从而，减小结漏(junctionleakage)和结电容(junctioncapacitance)，提高器件的性能。在离子注入的同时，由于侧墙114的存在，注入的部分粒子通过侧墙114反射进入鳍106中，在源漏区内侧的鳍中形成一个反射掺杂区142，即在沟道的两侧形成一个掺杂区，该反射掺杂区142相较于穿通停止层140具有较小的掺杂浓度，但相较于穿通停止层与沟道间的其他区域具有更大的掺杂浓度，由于该较大掺杂浓度的反射掺杂区142的存在，有利于改善器件的阈值电压，在器件尺寸不断缩小时，沟道两侧的反射掺杂区越来越靠近,直至重合在一起，此时沟道的掺杂浓度能够有效抑制阈值电压的卷曲(Vtroll-off)，改善器件的短沟道效应。
在注入形成穿通停止层之后，可以通过稀释的HF去除二氧化硅的伪栅介质层110，以便于重新形成更高质量的介质材料。
至此，形成了本发明实施例的穿通停止层，而后，进行器件的其他加工工艺。
参考图11所示，为现有技术PTSL晶体管与本发明实施例的PTSL晶体管的鳍中掺杂浓度分布对比示意图，其中，现有技术PTSL晶体管是指，传统技术中在形成隔离后，在整个鳍中形成穿通停止层，而本发明实施例的PTSL晶体管为在去除伪栅后形成穿通停止层，在现有技术和本发明的实施例中，都进行As粒子的注入，采用相同的注入条件：能量为70keV，剂量为1e13/cm2，角度为0度，可以看到，在现有技术中，形成的穿通停止层的掺杂浓度在3-5E18/cm3，在沟道区域的上部有横向较为均匀分布的较小掺杂浓度的掺杂区，而在本发明实施例中，穿通停止层的掺杂浓度在3-5E18/cm3，而在沟道区域的边缘处(虚线框区域)有掺杂浓度小于穿通停止层，但较其他区域掺杂浓度较高且集中分布的掺杂区，掺杂浓度大致在1e17～1e18/cm3，该区域即为由侧墙反射形成的反射掺杂区，利于改善器件的阈值电压。
参考图12所示，为现有技术PTSL晶体管与本发明实施例的PTSL晶体管的阈值电压卷曲对比示意图，可以看到，现有技术的晶体管器件，在栅极(Lg)的尺寸不段缩小后，阈值电压(VTH)明显卷曲，而本发明实施例的晶体管器件，在栅极(Lg)的尺寸不段缩小后，阈值电压(VTH)并无明显卷曲，有效改善了器件的短沟道效应。
在步骤S05，在开口中形成替代栅，参考图10、图10A(图10的AA向截面示意图)和10B(图10的BB向截面示意图)。
可以采用传统的方法形成替代栅。在本实施例中，在第一开口和第二开口中分别形成第一替代栅和第二替代栅，具体的，首先，淀积替代栅介质层151，该栅介质层151可以为高k介质材料，(例如，和氧化硅相比，具有高介电常数的材料)或其他合适的介质材料，高k介质材料例如铪基氧化物，HFO2、HfSiO、HfSiON、HfTaO、HfTiO等，厚度可以为1-3nm，而后，分别形成第一替代栅的栅堆叠152和第二替代栅的栅堆叠154，栅堆叠可以为金属材料，例如Ti、TiAlx、TiN、TaNx、HfN、TiCx、TaCx、W等等，具体的实施例中，在N型器件的第一开口中淀积TiCx或TaCx第一金属层(图未示出)，在第二开口中淀积TiAlx或TiN的第二金属层(图未示出)，而后以W填充第一和第二开口形成填充金属层(图未示出)，并进行平坦化，直至暴露出层间介质层，从而分别在第一开口中形成包括第一金属层和填充金属层的栅堆叠152的第一替代栅，在第二开口中形成包括第二金属层和填充金属层的栅堆叠154的第二替代栅，如图10、图10A和10B所示。此处形成替代栅的结构和材料仅为示例，可以根据具体的需要形成所需材料和结构的替代栅。至此，形成了本发明实施例的鳍式场效应晶体管器件。
此外，，本发明还提供了利用上述方法形成的鳍式场效应晶体管，参考图10、图10A和10B所示，该晶体管包括：半导体衬底100；衬底上的鳍106，鳍间形成有隔离108；鳍108上的器件结构；栅极152、154之下的鳍106中的穿通停止层140，以及源漏区内侧的鳍中的反射掺杂层142，反射掺杂层142与穿通停止层140具有相同的掺杂类型。
其中，器件结构包括横跨鳍的栅极152以及栅极侧壁的侧墙114、栅极两侧的鳍中的源漏区116，反射掺杂层142与穿通停止层140具有相同的掺杂类型，与源漏区116具有相反的掺杂类型。
在本发明实施例中，反射掺杂层142与穿通停止层140在离子注入工艺中形成，且由于注入时侧墙的反射作用形成反射掺杂层，使得该反射惨杂层相较于穿通停止层具有较小的掺杂浓度，但相较于穿通停止层与其他沟道区域，具有较大的掺杂浓度。
在本实施例中，为双栅的器件结构，在部分区域的鳍上形成第一类型的器件结构，在另一些区域的鳍上形成了第二类型的器件结构。
本发明的鳍式场效应晶体管器件，由于穿通停止层仅形成在栅极下的鳍中，而源漏区下并未形成该穿通停止层的掺杂区，从而减小结漏(junctionleakage)和结电容(junctioncapacitance)；而在沟道的两侧形成了反射掺杂区，该掺杂区有利于改善器件的阈值电压，尤其在器件尺寸不断缩小时，沟道两侧的反射掺杂区越来越靠近，可抑制阈值电压的卷曲(Vtroll-off)，改善器件的短沟道效应。
虽然本发明已以较佳实施例披露如上，然而并非用以限定本发明。任何熟悉本领域的技术人员，在不脱离本发明技术方案范围情况下，都可利用上述揭示的方法和技术内容对本发明技术方案作出许多可能的变动和修饰，或修改为等同变化的等效实施例。因此，凡是未脱离本发明技术方案的内容，依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰，均仍属于本发明技术方案保护的范围内。

Claims (7)

1.一种鳍式场效应晶体管的制造方法，其特征在于，包括步骤：
提供具有鳍的半导体衬底，鳍间形成有隔离；
在鳍上形成伪栅器件，并覆盖伪栅极两侧形成层间介质层；
去除伪栅极，以形成开口；
进行离子注入，在开口下的鳍内形成穿通停止层，同时，在源漏区内侧的鳍中形成反射掺杂层；
在开口中形成替代栅。
2.根据权利要求1所述的制造方法，其特征在于，所述离子注入为垂直角度的离子注入。
3.根据权利要求2所述的制造方法，其特征在于，离子注入的剂量范围为1E12至1E14cm-2，能量范围为10至150KEV。
4.根据权利要求1所述的制造方法，其特征在于，在鳍上分别形成第一类型伪栅器件和第二类型伪栅器件。
5.根据权利要求4所述的制造方法，其特征在于，在开口中分别形成第一替代栅和第二替代栅。
6.一种鳍式场效应晶体管，其特征在于，包括：
半导体衬底；
衬底上的鳍，鳍间形成有隔离；
鳍上的器件结构；
栅极之下的鳍中的穿通停止层，以及源漏区内侧的鳍中的反射掺杂层，反射掺杂层与穿通停止层具有相同的掺杂类型。
7.根据权利要求6所述的晶体管，其特征在于，所述器件结构包括第一类型器件结构和第二类型器件结构。
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CN108630548A (zh) * 2017-03-21 2018-10-09 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
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* Cited by examiner, † Cited by third party
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US20150024584A1 (en) * 2013-07-17 2015-01-22 Global Foundries, Inc. Methods for forming integrated circuits with reduced replacement metal gate height variability
US9871037B2 (en) * 2014-02-26 2018-01-16 Taiwan Semiconductor Manufacturing Company Limited Structures and methods for fabricating semiconductor devices using fin structures
US9947592B2 (en) * 2015-11-16 2018-04-17 Taiwan Semiconductor Manufacturing Co., Ltd. FinFET devices and methods of forming the same
US10020304B2 (en) * 2015-11-16 2018-07-10 Taiwan Semiconductor Manufacturing Co., Ltd. Fin field effect transistor, semiconductor device and fabricating method thereof
CN108573927B (zh) * 2017-03-07 2020-07-10 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10867101B1 (en) * 2020-02-24 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Leakage reduction between two transistor devices on a same continuous fin

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100327363A1 (en) * 2008-05-22 2010-12-30 Panasonic Corporation Semiconductor device and method for fabricating the same
CN103107139A (zh) * 2011-11-09 2013-05-15 联华电子股份有限公司 具有鳍状结构的场效晶体管的结构及其制作方法
CN103855010A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 FinFET及其制造方法
CN103928333A (zh) * 2013-01-15 2014-07-16 中国科学院微电子研究所 半导体器件及其制造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW514992B (en) * 1999-12-17 2002-12-21 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
JP4551811B2 (ja) * 2005-04-27 2010-09-29 株式会社東芝 半導体装置の製造方法
JP2013045901A (ja) * 2011-08-24 2013-03-04 Toshiba Corp 半導体装置および半導体装置の製造方法
CN103985754B (zh) * 2013-02-08 2018-09-04 中国科学院微电子研究所 半导体器件及其制造方法
US9299840B2 (en) * 2013-03-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. FinFETs and methods for forming the same
US9847404B2 (en) * 2013-07-06 2017-12-19 Semiwise Limited Fluctuation resistant FinFET
US9082698B1 (en) * 2014-03-07 2015-07-14 Globalfoundries Inc. Methods to improve FinFet semiconductor device behavior using co-implantation under the channel region
US9431395B2 (en) * 2014-07-01 2016-08-30 International Business Machines Corporation Protection of semiconductor-oxide-containing gate dielectric during replacement gate formation

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100327363A1 (en) * 2008-05-22 2010-12-30 Panasonic Corporation Semiconductor device and method for fabricating the same
CN103107139A (zh) * 2011-11-09 2013-05-15 联华电子股份有限公司 具有鳍状结构的场效晶体管的结构及其制作方法
CN103855010A (zh) * 2012-11-30 2014-06-11 中国科学院微电子研究所 FinFET及其制造方法
CN103928333A (zh) * 2013-01-15 2014-07-16 中国科学院微电子研究所 半导体器件及其制造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630548A (zh) * 2017-03-21 2018-10-09 中芯国际集成电路制造(上海)有限公司 鳍式场效应管及其形成方法
TWI693634B (zh) * 2017-06-30 2020-05-11 台灣積體電路製造股份有限公司 半導體裝置之製造方法
US10714598B2 (en) 2017-06-30 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor device
US11043580B2 (en) 2017-06-30 2021-06-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing semiconductor devices
US11677012B2 (en) 2017-06-30 2023-06-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing semiconductor devices
CN111755498A (zh) * 2019-03-27 2020-10-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN111755498B (zh) * 2019-03-27 2024-03-22 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法

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