CN105765718B - 集成功率技术中的垂直沟槽型mosfet器件 - Google Patents

集成功率技术中的垂直沟槽型mosfet器件 Download PDF

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CN105765718B
CN105765718B CN201480065238.0A CN201480065238A CN105765718B CN 105765718 B CN105765718 B CN 105765718B CN 201480065238 A CN201480065238 A CN 201480065238A CN 105765718 B CN105765718 B CN 105765718B
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vertical
deep groove
groove structure
gate
drift region
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CN105765718A (zh
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G·马图尔
M·丹尼森
S·彭德哈卡尔
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Texas Instruments Inc
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Abstract

在描述的示例中，具有垂直漏极延伸式MOS晶体管(110)的半导体器件(100)可通过形成深沟槽结构(104)形成，以限定至少一个垂直漂移区域(108)，该垂直漂移区域108在至少两个相反的侧面与深沟槽结构(104)相邻。深沟槽结构(104)包括介电内衬(124)。深沟槽结构(104)被隔开以为漂移区域(108)形成RESURF区域。垂直栅极(114)形成于深沟槽结构(104)的介电内衬(124)中的垂直取向的栅极沟槽中，该深沟槽结构(104)邻接垂直漂移区域(108)。为晶体管体(118)植入掺杂剂的体植入掩模也用作在介电内衬(124)中形成垂直取向的栅极沟槽的刻蚀掩模。

Description

集成功率技术中的垂直沟槽型MOSFET器件
技术领域
本申请通常涉及半导体器件，以及特别地涉及半导体器件中漏极延伸式晶体管。
背景技术
延伸式漏极金属氧化物半导体(MOS)晶体管可由开态的晶体管电阻，晶体管在包括晶体管的衬底上表面所占的横向面积，以及晶体管的漏极节点和源极节点之间的击穿电势表征，其中击穿电势限制晶体管的最大操作电势。减小针对给定值的开态电阻和击穿电势的晶体管的面积可能是期望的。一种减小面积的技术为在延伸式漏极的垂直取向上配置漂移区域，以便漂移区域的漏极电流垂直地流向衬底上表面。半导体器件中使用平面处理集成垂直取向的漂移区域同时维持期望的制造成本以及复杂性可为有问题的。
发明内容
在描述的示例中，具有垂直漏极延伸式MOS晶体管的半导体器件可通过形成深沟槽结构形成，该深沟槽结构用于限定至少一个垂直漂移区域，该至少一个垂直漂移区域在至少两个相反的侧面与深沟槽结构相邻。深沟槽结构包括介电内衬。深沟槽结构被隔开以为漂移区域形成RESURF区域。垂直栅极形成于深沟槽结构的介电内衬中的垂直取向的栅极沟槽中，该深沟槽结构邻接垂直漂移区域。为晶体管体植入掺杂剂的体植入掩模也用作在介电内衬中形成垂直取向的栅极沟槽的刻蚀掩模。
附图说明
图1为具有一种垂直漏极延伸式MOS晶体管的半导体器件的横截面视图。
图2为具有一种垂直漏极延伸式MOS晶体管的半导体器件的横截面视图。
图3A到图3G为半导体器件，例如图1或图2的半导体器件，在连续制造阶段的横截面视图。
图4为具有示例接触配置的半导体器件的横截面视图。
图5为包含垂直漏极延伸式MOS晶体管和平面MOS晶体管的半导体器件的横截面视图。
具体实施方式
下面的共同未决专利申请包含相关的事件并以引用方式被合并：申请号US 14/044,909；以及申请号US 14/044,915。
具有垂直漏极延伸式MOS晶体管的半导体器件可通过形成深沟槽结构形成，以定义晶体管的至少一个垂直漂移区域。深沟槽结构包括介电内衬。垂直漂移区域在至少两个相反的侧面与深沟槽结构相邻。深沟槽结构被隔开以为漂移区域形成RESURF区域。垂直栅极形成于深沟槽结构的介电内衬的沟槽中，该深沟槽结构邻接垂直漂移区域。为晶体管的体区域植入掺杂剂的体植入掩模也用作在介电内衬中形成垂直取向的栅极沟槽的刻蚀掩模。可选的掩埋式漏极接触层可连接到垂直漂移区域以提供漏极连接，或垂直漏极接触区域(邻近于垂直漂移区域)可提供漏极连接。在至少一个示例中，半导体器件可为集成电路，其包含垂直漏极延伸式MOS晶体管和其他晶体管。在另外的示例中，半导体器件可为离散器件，其中垂直漏极延伸式MOS晶体管是唯一的晶体管。垂直漏极接触区域可能配置在深沟槽结构的邻近部分之间。
为了本说明书的目的，术语“RESURF”指的是在邻近的半导体区域中减小电场的材料。例如，RESURF区域可为具有与邻近半导体区域相反的导电类型的半导体区域。RESURF结构在Appels等的“薄层高电压器件(Thin Layer High Voltage Devices)”文章中描述，该文章发表在1980年出版的飞利浦研究杂志(Philips J)第35期第1-13页上。
本公开所述的示例描述了n沟道器件。相应的p沟道器件可通过适当的改变掺杂极性形成。图1为具有垂直漏极延伸式MOS晶体管的半导体器件的横截面视图。半导体器件100形成于p型半导体衬底102中和p型半导体衬底102上。垂直漏极延伸式MOS晶体管110包括深沟槽结构104，该深沟槽结构104配置在衬底102中，以限定通过深沟槽结构104的实例分开的至少一个n型垂直漏极接触区域106和邻近的n型垂直取向的漂移区域108。在本示例中，分开垂直取向的漂移区域108的深沟槽结构104的一些实例可有线性配置，如图1所示；线性配置不具有封闭的回路拓扑结构。至少一个垂直漏极接触区域106和垂直取向的漂移区域108接触配置在衬底102中的n型掩埋层112。
深沟槽结构104为1到5微米深，以及0.5到1.5微米宽。深沟槽结构104大体上全部等深。深沟槽结构104具有介电内衬124并可有可选的导电中心部件126。垂直取向的漂移区域108在至少两个相反的侧面与深沟槽结构104相邻，该深沟槽结构104被隔开0.5到2微米的距离，以为垂直取向的漂移区域108提供RESURF区域。垂直漏极接触区域106在至少两个相反的侧面与深沟槽结构104相邻，该深沟槽结构可被隔开，例如0.5到2.5微米的距离。
垂直栅极114和相应的栅极介电层116配置在深沟槽结构104的介电内衬124的沟槽中。在本示例中，垂直栅极114没有横向地延伸进入介电内衬124的弯曲部分。至少一个p型体区域118配置在衬底102中的垂直取向的漂移区域108上方并接触栅极介电层116。垂直栅极114在体区域118下方延伸至垂直取向的漂移区域108。N型源极区域120配置在衬底102中接触p型体区域118和栅极介电层116。可选的p型体接触区域可配置在衬底102接触体区域118。
深沟槽结构104的深度可经调整为垂直漏极延伸式MOS晶体管110提供期望的操作电压。例如，2.5微米深的深沟槽结构104可提供30伏特的操作。4微米深的深沟槽结构104可提供50伏特的操作。在垂直漏极延伸式MOS晶体管110操作期间，导电中心部件126，如果有，可电偏置以减小垂直取向的漂移区域108的峰值电场。例如，导电中心部件126可连接到源极区域120，到垂直栅极114或到具有期望电势的偏置源极。配置垂直漏极延伸式MOS晶体管110可提供特定电阻率的期望值，对于该垂直漏极延伸式MOS晶体管110，其为开态电阻和晶体管面积的乘积，其中该垂直漏极延伸式晶体管110具有以下结构：平行的垂直取向的漂移区域108，位于深沟槽结构104的每个介电内衬124中的垂直栅极114，深沟槽结构104邻接垂直取向的漂移区域108。
图2为具有垂直漏极延伸式MOS晶体管的半导体器件的横截面视图。半导体器件200形成于p型半导体衬底202中和p型半导体衬底202上。垂直漏极延伸式MOS晶体管210有深沟槽结构204，该深沟槽结构204配置在衬底202中；深沟槽结构204有介电内衬224和可选的导电中心部件226。通过垂直漏极接触区域206在至少两个相反侧面与深沟槽结构204相邻，深沟槽结构204限定至少一个垂直漏极接触区域206，并围绕至少一个垂直取向的漂移区域208，该垂直取向的漂移区域208毗邻垂直漏极接触区域206。深沟槽结构204为垂直取向的漂移区域208提供RESURF区域。每个垂直取向的漂移区域208毗邻两个深沟槽结构204，如图2所示。垂直漏极接触区域206为n型并在深沟槽结构204的底部下方延伸，以临近于深沟槽结构204的底部电气连接至垂直漏极接触区域206。深沟槽结构204可围绕垂直漏极延伸式MOS晶体管210，如图2所示。深沟槽结构204与关于图1所述有相同的深度和间距。
垂直栅极214和相应的栅极介电层216配置在深沟槽结构204的介电内衬224的沟槽中。在本示例中，垂直栅极214横向地延伸进入介电内衬224的弯曲部分以横向地围绕垂直取向的漂移区域208，如图2所示。P型体区域218配置在衬底202中垂直取向的漂移区域208上方并接触栅极介电层216。垂直栅极214在体区域218下方延伸至垂直取向的漂移区域208。N型源极区域220配置在衬底202中接触p型体区域218和栅极介电层216。
垂直漏极延伸式MOS晶体管210的操作与关于图1所述相似。配置垂直漏极延伸式MOS晶体管，以便深沟槽结构204围绕垂直取向的漂移区域208，以及以便垂直栅极214横向地围绕垂直取向的漂移区域208延伸，可为垂直漏极延伸式MOS晶体管210提供特定电阻率的期望值。
图3A到图3G为半导体器件，例如图1或图2的半导体器件，在连续制造阶段的横截面视图。参考图3A，半导体器件300形成于p型半导体衬底302中和p型半导体衬底302上。垂直漏极延伸式MOS晶体管310的深沟槽结构304通过以下步骤形成于衬底302中：在衬底中刻蚀深隔离沟槽，形成介电内衬324以及随后在介电内衬324上可选地形成导电中心部件326。例如，深隔离沟槽可通过起始于在衬底302上表面上形成硬掩模材料层的过程形成。硬掩模可通过光刻形成刻蚀掩模，随后使用反应离子刻蚀(RIE)过程移除限定用于深隔离沟槽的区域上的硬掩模材料形成。硬掩模形成图案之后，使用各向异性刻蚀过程，例如博世(Bosch)深RIE过程或连续深RIE过程，将材料从衬底302的深隔离沟槽中移除。
在一个示例中，介电内衬324可包括热生长二氧化硅。介电内衬324也可包括一个或更多介电材料层，该介电材料例如二氧化硅，氮化硅和/或氮氧化硅，其通过化学气相沉积(CVD)过程形成。在一个示例中，导电中心部件326可包括多晶的硅，通常指的是多晶硅，其通过在温度为580℃到650℃的低压反应器内部热分解SiH4气体形成。多晶硅可在形成期间掺杂以提供期望的电阻。被填充的深隔离沟槽形成深沟槽结构304。由于形成介电内衬324导致的衬底302上表面上的不需要的介电材料和由于形成导电中心部件326导致的衬底302上表面上的不需要的导电材料可被移除，例如通过使用回蚀和/或化学机械抛光(CMP)过程。
垂直漏极延伸式MOS晶体管310包括垂直漏极接触区域，图3A到图3G中未示出，以及形成于衬底302中的垂直取向的漂移区域308。执行漏极接触离子植入过程，其将n型掺杂剂例如磷植入衬底320中限定用于垂直漏极接触区域的区域，以形成漏极接触植入区域。例如，一剂漏极接触离子植入过程可为1×1016cm-2到3×1016cm-2。执行漂移区域离子植入过程，其将n型掺杂剂例如磷植入衬底302中限定用于垂直取向的漂移区域308的区域中或上方，以形成漂移植入区域。一剂漏极接触离子植入过程为漂移区域离子植入剂量的至少10倍。
随后，执行热驱动操作，其加热衬底302以激活和扩散漏极接触植入区域和漂移植入区域植入的掺杂剂，从而分别形成垂直漏极接触区域和垂直取向的漂移区域308。热驱动操作的条件取决于深沟槽结构304的深度和深沟槽结构304底部处的垂直漏极接触区域期望的横向范围。例如，具有2.5微米深的深沟槽结构304的垂直漏极延伸式MOS晶体管310可有热驱动操作，其在1100℃下加热衬底3023.5到4小时，或等价的退火条件，例如1125℃下2小时，或1050℃下12小时。
随后，体植入掩模328在衬底302上形成以暴露垂直取向的漂移区域308的区域，其限定用于垂直漏极延伸式MOS晶体管310的体区域。例如，体植入掩模328可主要包括光刻胶，或可包括硬掩模材料例如氮化硅。通过体植入掩模328暴露的区域在介电内衬324上延伸并邻接限定用于体区域的区域。
参考图3B，执行体植入过程，其将p型掺杂剂例如硼植入衬底302中通过体植入掩模328暴露的区域以形成体植入区域330。例如，一剂体植入过程可为1×1013cm-2到5×1013cm-2。
参考图3C，执行栅极沟槽刻蚀操作，其使用体植入掩模328作为刻蚀掩模。通过栅极沟槽刻蚀操作将介电材料从介电内衬324移除，以形成垂直取向的栅极沟槽332，其毗邻并在体植入区域330下方延伸。栅极沟槽刻蚀操作可为时控的刻蚀。湿清洁操作，例如包括氢氟酸的稀释水溶液，可在栅极沟槽刻蚀操作之后执行，以从垂直取向的栅极沟槽332的侧面移除残留物。体植入掩模328可在栅极沟槽刻蚀操作完成之后移除。
参考图3D，栅极介电层316在衬底302上垂直取向的栅极沟槽332上形成，以及可能在衬底302其他暴露的半导体表面形成。例如，栅极介电层316可为一个或更多层的二氧化硅，氮氧化硅，氧化铝，氮氧化铝，氧化铪，铪硅酸盐，铪氧氮化硅，氧化锆，锆硅酸盐，和/或锆氧氮化硅。由于在温度为50℃到800℃之间暴露于包含等离子体的氮气或包含氮的环境气体中，栅极介电层316可包括氮。栅极介电层316可由多种栅极介电形成过程中的任何形成过程形成，例如热氧化，氧化层的氮化等离子体，和/或通过原子层沉积(ALD)的介电材料沉积。栅极介电层316的厚度可为2.5到3.3纳米每伏特的垂直漏极延伸式MOS晶体管310的栅源偏压。例如，用30伏特的栅源偏压操作的垂直漏极延伸式MOS晶体管310的实例可有75到100纳米厚的栅极介电层316。
形成栅极介电层316可涉及加热衬底302，以便图3C的体植入区域330的p型掺杂剂扩散并激活以形成p型体区域318。例如，为栅极介电层316生长热氧化层可提供充足的热剖面以在体植入区域330中扩散p型掺杂剂，以便体区域318延伸至衬底302中期望的深度。或者，执行例如退火的热过程为体区域318提供期望的深度。
参考图3E，栅极材料层334在垂直取向的栅极沟槽332中的栅极介电层316上形成，以及可能在半导体器件300的其他区域上形成。例如，栅极材料层334可为多晶硅，或可为一个或更多的层的其他导电材料，例如金属硅化物或氮化钛。
参考图3F，图3E的栅极材料层334形成图案以将栅极材料留在垂直取向的栅极沟槽中以形成垂直栅极314。垂直栅极314在体区域318下方延伸。在本示例的一个版本中，垂直栅极314可通过介电材料与导电中心部件326电隔离。
参考图3G，n型源极区域320在衬底302中形成，其毗邻栅极314并邻接与垂直取向的漂移区域308相反的体区域318。一个或更多可选的p型体接触区域322可配置在衬底302中邻接体区域318。
图4为具有示例接触配置的半导体器件的横截面视图。半导体器件300形成于p型半导体衬底302中和p型半导体衬底302上。垂直漏极延伸式MOS晶体管310的深沟槽结构304配置在衬底302中，该垂直漏极延伸式MOS晶体管310包括介电内衬324和导电中心部件326。n型垂直取向的漂移区域308配置在衬底302中，其在至少两个侧面邻接深沟槽结构304，该深沟槽结构304为垂直取向的漂移区域308提供RESURF区域。p型体区域318配置在衬底302中垂直取向的漂移区域308上方。n型源极区域320配置在衬底302中体区域318上方。垂直栅极314和栅极介电层316配置在深沟槽结构304中，如关于图1所述。
在本示例中，垂直栅极314形成图案以与导电中心部件326重叠。例如，垂直栅极314可使用光刻生成的刻蚀掩模及随后的RIE过程形成图案。形成栅极接触336以电气连接至在导电中心部件326上的重叠区域上的垂直栅极314。可形成可选的接触328以电气连接至导电中心部件326。
图5为包含垂直漏极延伸式MOS晶体管和平面MOS晶体管的半导体器件的横截面视图。垂直漏极延伸式MOS晶体管310包括垂直栅极314，并且栅极介电层316形成于配置在半导体器件300的衬底302中的深沟槽结构的介电内衬324中。栅极介电层316和垂直栅极314与衬底302的上表面重叠，其可简化沟槽栅极314的制备。沟槽栅极314可使用光刻限定的刻蚀掩模通过RIE过程形成。栅极介电层316和沟槽栅极314可与平面MOS晶体管344的晶体管栅极介电层340和晶体管栅极342同时地形成。
在权利要求书的范围内，在所述的实施例中修改是可能的，并且其他实施例是可能的。

Claims (20)

1.一种半导体器件，包括：
衬底，其包括具有第一导电类型的半导体；以及
垂直漏极延伸式金属氧化物半导体晶体管，即垂直漏极延伸式MOS晶体管，其包括：
多个深沟槽结构，其配置在所述衬底中，至少一微米深，每个具有邻接所述衬底的介电内衬，所述深沟槽结构具有大体相等的深度；
垂直漏极接触区域，其具有与配置在所述衬底中的所述第一导电类型相反的第二导电类型，所述垂直漏极接触区域邻接所述深沟槽结构并在至少两个相反侧面与所述深沟槽结构的一部分相邻；
垂直取向的漂移区域，其具有所述第二导电类型，配置在所述衬底中，邻接所述深沟槽结构并在至少两个相反的侧面与所述深沟槽结构的一部分相邻；
栅极介电层上的垂直栅极，其配置在所述多个深沟槽结构的相应的深沟槽结构的所述介电内衬中的垂直取向的栅极沟槽中；以及
体区域，其具有所述第一导电类型，配置在所述垂直取向的漂移区域上方，并接触所述栅极介电层，以便所述垂直栅极在所述体区域下方延伸；
其中，所述垂直取向的漂移区域与所述衬底形成结，并临近所述多个深沟槽结构的所述相应的深沟槽结构的底部形成电气连接到垂直漏极接触区域，并且
其中，所述相应的深沟槽结构定位在所述垂直取向的漂移区域和所述垂直漏极接触区域之间。
2.根据权利要求1所述的半导体器件，其中所述垂直栅极没有横向地延伸进入所述介电内衬的弯曲部分。
3.根据权利要求1所述的半导体器件，其中所述垂直栅极横向地延伸进入所述介电内衬的弯曲部分。
4.根据权利要求1所述的半导体器件，其中所述垂直漏极延伸式MOS晶体管进一步包括：掩埋层，其具有所述第二导电类型，配置在所述衬底中，在所述垂直取向的漂移区域下方延伸，并电气连接至所述垂直漏极接触区域。
5.根据权利要求1所述的半导体器件，其中所述垂直取向的漂移区域临近于所述多个深沟槽结构的第一深沟槽结构的底部电气连接至所述垂直漏极接触区域，所述第一深沟槽结构将所述垂直取向的漂移区域与所述垂直漏极接触区域分开。
6.根据权利要求1所述的半导体器件，其中所述垂直取向的漂移区域被所述多个深沟槽结构的第一深沟槽结构横向地围绕，所述第一深沟槽结构具有封闭的回路配置。
7.根据权利要求6所述的半导体器件，其中所述垂直栅极横向地围绕所述垂直取向的漂移区域。
8.根据权利要求1所述的半导体器件，其中：
所述垂直取向的漂移区域为第一垂直取向的漂移区域；
所述垂直栅极为第一垂直栅极；
所述栅极介电层为第一栅极介电层；
所述垂直取向的栅极沟槽为第一垂直取向的栅极沟槽；以及
所述垂直漏极延伸式MOS晶体管进一步包括：第二垂直取向的漂移区域，其通过所述多个深沟槽结构的第一深沟槽结构与所述第一垂直取向的漂移区域分开，其中第二栅极介电层上的第二垂直栅极配置在所述第一深沟槽结构的所述介电内衬中的第二垂直取向的栅极沟槽中。
9.根据权利要求1所述的半导体器件，其中所述深沟槽结构为2.5微米到5微米深。
10.根据权利要求1所述的半导体器件，其中：所述第一导电类型为p型；以及所述第二导电类型为n型。
11.一种形成半导体器件的方法，所述方法包括：
提供衬底，所述衬底包括具有第一导电类型的半导体；以及
通过包含以下步骤的过程，形成垂直漏极延伸式MOS晶体管：
在所述衬底中形成至少1微米深的多个深隔离沟槽，所述深隔离沟槽具有大体相等的深度；
在所述深隔离沟槽中形成介电内衬，所述介电内衬接触所述衬底，以形成多个深沟槽结构；
形成垂直漏极接触区域，所述漏极接触区域具有与配置在所述衬底中的所述第一导电类型相反的第二导电类型，所述垂直漏极接触区域邻接所述深沟槽结构并在至少两个相反的侧面与所述深沟槽结构的一部分相邻；
形成垂直取向的漂移区域，所述垂直取向的漂移区域具有所述第二导电类型，配置在所述衬底中，邻接所述深沟槽结构并在至少两个相反的侧面与所述深沟槽结构的一部分相邻；
在所述衬底上形成体植入掩模以暴露所述垂直取向的漂移区域的区域，该区域限定用于所述垂直漏极延伸式MOS晶体管的体区域，由所述体植入掩模暴露的所述区域在所述介电内衬上延伸并毗邻限定用于所述体区域的区域；
将所述第一导电类型的掺杂剂植入所述衬底的由所述体植入掩模暴露的区域内以形成体区域；
从由所述体植入掩模暴露的区域中的所述介电内衬移除介电材料以形成垂直取向的栅极沟槽；
在所述垂直取向的栅极沟槽中形成栅极介电层；以及
在配置在所述垂直取向的栅极沟槽中的所述栅极介电层上形成垂直栅极，所述垂直栅极毗邻所述体区域。
12.根据权利要求11所述的方法，其中所述垂直栅极没有横向地延伸进入所述介电内衬的弯曲部分。
13.根据权利要求11所述的方法，其中所述垂直栅极横向地延伸进入所述介电内衬的弯曲部分。
14.根据权利要求11所述的方法，其中所述垂直漏极延伸式MOS晶体管进一步包括：掩埋层，其具有所述第二导电类型，配置在所述衬底中，在所述垂直取向的漂移区域下方延伸，并电气连接至所述垂直漏极接触区域。
15.根据权利要求11所述的方法，其中在所述垂直取向的漂移区域与所述垂直漏极接触区域之间，所述垂直取向的漂移区域临近于所述多个深沟槽结构的相应的深沟槽结构的底部电气连接至所述垂直漏极接触区域。
16.根据权利要求11所述的方法，其中所述垂直取向的漂移区域被所述多个深沟槽结构的相应的深沟槽结构横向地围绕，所述相应的深沟槽结构具有封闭的回路配置。
17.根据权利要求16所述的方法，其中所述垂直栅极横向地围绕所述垂直取向的漂移区域。
18.根据权利要求11所述的方法，其中所述深沟槽结构为2.5微米到5微米深。
19.根据权利要求11所述的方法，其中所述垂直栅极与平面MOS晶体管同时地形成。
20.根据权利要求11所述的方法，其中：所述第一导电类型为p型；以及所述第二导电类型为n型。
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