JP2016536781A - インテグレートされたパワー技術における垂直トレンチmosfetデバイス - Google Patents
インテグレートされたパワー技術における垂直トレンチmosfetデバイス Download PDFInfo
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- JP2016536781A JP2016536781A JP2016520001A JP2016520001A JP2016536781A JP 2016536781 A JP2016536781 A JP 2016536781A JP 2016520001 A JP2016520001 A JP 2016520001A JP 2016520001 A JP2016520001 A JP 2016520001A JP 2016536781 A JP2016536781 A JP 2016536781A
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- deep trench
- gate
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- vertically oriented
- drift region
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Abstract
Description
Appels, et al, "Thin Layer High Voltage Devices" Philips J, Res. 35 1-13, 1980
Claims (20)
- 半導体デバイスであって、
第1の導電型を有する半導体を含む基板、及び
垂直のドレイン拡張された金属酸化物半導体(MOS)トランジスタ、
を含み、
前記垂直のドレイン拡張されたMOSトランジスタが、
少なくとも1ミクロンの深さの、前記基板に配置される複数のディープトレンチ構造であって、前記複数のディープトレンチ構造の各々が、前記基板に隣接する誘電体ライナーを有し、前記複数のディープトレンチ構造が実質的に等しい深さを有する、前記複数のディープトレンチ構造と、
前記基板に配置される前記第1の導電型とは反対の第2の導電型を有する垂直ドレインコンタクト領域であって、前記ディープトレンチ構造の一部に隣接し、且つ、前記ディープトレンチ構造の一部により少なくとも2つの対向する側部で区分される、前記垂直ドレインコンタクト領域と、
前記基板に配置される前記第2の導電型を有する垂直に向けられるドリフト領域であって、前記ディープトレンチ構造の一部に隣接し、且つ、前記ディープトレンチ構造の一部により少なくとも2つの対向する側部で区分される、前記垂直に向けられるドリフト領域と、
前記複数のディープトレンチ構造の第1のディープトレンチ構造の前記誘電体ライナーにおいて垂直に向けられるゲートトレンチに配置されるゲート誘電体層上の垂直ゲートと、
前記垂直ゲートが前記ボディ領域より下に延在するように、前記垂直に向けられるドリフト領域の上に配置される前記第1の導電型を有し、且つ、前記ゲート誘電体層に接する、ボディ領域と、
を含む、半導体デバイス。 - 請求項1に記載の半導体デバイスであって、前記垂直ゲートが、前記誘電体ライナーの湾曲部分内へ横方向に延在しない、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記垂直ゲートが、前記誘電体ライナーの湾曲部分内へ横方向に延在する、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記垂直のドレイン拡張されたMOSトランジスタが更に、前記基板に配置される前記第2の導電型を有する埋め込み層を含み、前記埋め込み層が、前記垂直に向けられるドリフト領域の下に延在し、且つ、前記垂直ドレインコンタクト領域への電気的接続を成す、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記垂直に向けられるドリフト領域が、前記複数の前記ディープトレンチ構造の第1のディープトレンチ構造の底部に近接する前記垂直ドレインコンタクト領域への電気的接続を成し、前記第1のディープトレンチ構造が、前記垂直に向けられるドリフト領域を前記垂直ドレインコンタクト領域から分離する、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記垂直に向けられるドリフト領域が、前記複数の前記ディープトレンチ構造の第1のディープトレンチ構造により横方向に囲まれ、前記第1のディープトレンチ構造が閉ループ構成を有する、半導体デバイス。
- 請求項6に記載の半導体デバイスであって、前記垂直ゲートが、前記垂直に向けられるドリフト領域を横方向に囲む、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、
前記垂直に向けられるドリフト領域が第1の垂直に向けられるドリフト領域であり、
前記垂直ゲートが第1の垂直ゲートであり、
前記ゲート誘電体層が第1のゲート誘電体層であり、
前記垂直に向けられるゲートトレンチが、第1の垂直に向けられるゲートトレンチであり、
前記垂直のドレイン拡張されたMOSトランジスタが更に、前記複数の前記ディープトレンチ構造の第1のディープトレンチ構造によって前記第1の垂直に向けられるドリフト領域から分離される、第2の垂直に向けられるドリフト領域を含み、第2のゲート誘電体層上の第2の垂直ゲートが、前記第1のディープトレンチ構造の前記誘電体ライナーにおける第2の垂直に向けられるゲートトレンチに配置される、
半導体デバイス。 - 請求項1に記載の半導体デバイスであって、前記ディープトレンチ構造が2.5ミクロン〜5ミクロンの深さである、半導体デバイス。
- 請求項1に記載の半導体デバイスであって、前記第1の導電型がp型であり、前記第2の導電型がn型である、半導体デバイス。
- 半導体デバイスを形成する方法であって、前記方法が、
第1の導電型を有する半導体を含む基板を提供すること、及び
垂直のドレイン拡張されたMOSトランジスタを形成すること、
を含み、
前記垂直のドレイン拡張されたMOSトランジスタを形成することが、
前記基板に、少なくとも1ミクロンの深さの実質的に等しい深さを有する複数のディープ隔離トレンチを形成することと、
複数のディープトレンチ構造を形成するために、前記基板に接する誘電体ライナーを前記ディープ隔離トレンチに形成することと、
前記基板に配置される前記第1の導電型とは反対の第2の導電型を有する垂直ドレインコンタクト領域を形成することであって、前記垂直ドレインコンタクト領域が、前記ディープトレンチ構造の一部に隣接し、前記ディープトレンチ構造の一部により少なくとも2つの対向する側部で区分されることと、
前記基板に配置される前記第2の導電型を有し、前記ディープトレンチ構造の一部に隣接し、前記ディープトレンチ構造の一部により少なくとも2つの対向する側部で区分される、垂直に向けられるドリフト領域を形成することと、
前記垂直のドレイン拡張されたMOSトランジスタのボディ領域のために画定される前記垂直に向けられるドリフト領域のエリアを露出させるように前記基板の上にボディインプラントマスクを形成することであって、前記ボディインプラントマスクにより露出された前記エリアが、前記ボディ領域のために画定された前記エリアに隣接する前記誘電体ライナーの上に延在することと、
ボディ領域を形成するために、前記ボディインプラントマスクにより露出された前記エリアにおける前記基板に前記第1の導電型のドーパントを注入することと、
垂直に向けられるゲートトレンチを形成するために、前記ボディインプラントマスクにより露出された前記エリアにおける前記誘電体ライナーから誘電性材料を取り除くことと、
前記垂直に向けられるゲートトレンチにゲート誘電体層を形成することと、
前記ボディ領域に近接して前記垂直に向けられるゲートトレンチに配置される前記ゲート誘電体層上に垂直ゲートを形成することと、
を含むプロセスによる、
方法。 - 請求項11に記載の方法であって、前記垂直ゲートが、前記誘電体ライナーの湾曲部分内へ横方向に延在しない、方法。
- 請求項11に記載の方法であって、前記垂直ゲートが、前記誘電体ライナーの湾曲部分内へ横方向に延在する、方法。
- 請求項11に記載の方法であって、前記垂直のドレイン拡張されたMOSトランジスタが更に、前記基板に配置される前記第2の導電型を有する埋め込み層を含み、前記埋め込み層が、前記垂直に向けられるドリフト領域の下に延在し、且つ、前記垂直ドレインコンタクト領域への電気的接続を成す、方法。
- 請求項11に記載の方法であって、前記垂直に向けられるドリフト領域が、前記複数の前記ディープトレンチ構造の第1のディープトレンチ構造の底部に近接する前記垂直ドレインコンタクト領域への電気的接続を成し、前記第1のディープトレンチ構造が、前記垂直に向けられるドリフト領域を前記垂直ドレインコンタクト領域から分離する、方法。
- 請求項11に記載の方法であって、前記垂直に向けられるドリフト領域が、前記複数の前記ディープトレンチ構造の第1のディープトレンチ構造により横方向に囲まれ、前記第1のディープトレンチ構造が閉ループ構成を有する、方法。
- 請求項16に記載の方法であって、前記垂直ゲートが、前記垂直に向けられるドリフト領域を横方向に囲む、方法。
- 請求項11に記載の方法であって、前記ディープトレンチ構造が2.5ミクロン〜5ミクロンの深さである、方法。
- 請求項11に記載の方法であって、前記垂直ゲートが、プラナーMOSトランジスタのゲートと同時に形成される、方法。
- 請求項11に記載の方法であって、前記第1の導電型がp型であり、前記第2の導電型がn型である、方法。
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