CN105702640B - 具有减小的外形规格和增加的载流能力的功率半导体封装 - Google Patents

具有减小的外形规格和增加的载流能力的功率半导体封装 Download PDF

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CN105702640B
CN105702640B CN201510946455.7A CN201510946455A CN105702640B CN 105702640 B CN105702640 B CN 105702640B CN 201510946455 A CN201510946455 A CN 201510946455A CN 105702640 B CN105702640 B CN 105702640B
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power
bare chip
etching section
semiconductor bare
acnemia
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CN105702640A (zh
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曹应山
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Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Abstract

公开了一种功率半导体封装。该功率半导体封装包括：引线框架，具有部分刻蚀区段和至少一个非刻蚀区段；第一半导体裸片，具有单片形成在其上的第一功率晶体管和驱动器集成电路(IC)；第二半导体裸片，具有第二功率晶体管；其中第一半导体裸片和第二半导体裸片被配置用于附接到部分刻蚀区段，并且其中部分刻蚀区段和至少一个非刻蚀区段使得第一半导体裸片能够通过无腿导电接线柱耦合到第二半导体裸片。

Description

具有减小的外形规格和增加的载流能力的功率半导体封装
背景技术
本申请要求2014年12月16日提交的序列号62/092,753的题为“Small FormFactor Power Converter Package with Integrated Power Transistors”的临时专利申请的权益和优先权。由此这一临时申请中的公开内容通过引用完全并入到本申请中。
常利用诸如降压转换器之类的功率转换器将高DC电压转换为低DC电压。功率转换器通常包括以半桥配置连接的高侧开关和低侧开关。功率转换器可以包括驱动器集成电路(IC)以用于控制高侧和低侧开关中的任一者或两者的占空比，以将高输入电压转换为低输出电压。为了改善外形规格、性能和制造成本，往往期望将诸如基于半桥的DC-DC转换器或者电压转换器之类的功率转换器电路的部件集成到紧凑的功率半导体封装中。
在常规的功率半导体封装中，个体半导体裸片并排布置并且通过它们的对应导电接线柱(clip)耦合到基板，这可能不期望地增加了功率半导体封装的电阻和外形规格。而且，用于成功地容纳多个引线框架和导电接线柱的封装设计规则要求针对制造的大容限度(即大余隙空间)。通常，具有腿部分的导电接线柱用于提供足够的余隙空间以用于必要的电连接。然而，难以将导电接线柱的腿部分制造为匹配常规功率半导体封装中的半导体器件的精确高度。结果，腿部分可以使得导电接线柱朝向半导体器件或者远离半导体器件倾斜，这转而可以造成导电接线柱与半导体器件之间的不可靠电连接，并且从而限制导电接线柱的载流能力。附加地，由使用多个导电接线柱引起的增加的封装复杂度可能负面地影响制造时间、成本和封装产量。
因而，有需要在本领域中提供具有减小的外形规格和增加的载流能力的紧凑功率半导体封装。
发明内容
大体上如至少一个图所示的和/或结合至少一个图所描述的，以及如权利要求中所阐述的，本公开涉及具有减小的外形规格和增加的载流能力的功率半导体封装。
附图说明
图1图示根据本申请的一个实施方式的功率转换器的示例性电路图。
图2A图示根据本申请的一个实施方式的示例性功率半导体封装的平面顶视图。
图2B图示根据本申请的一个实施方式的示例性功率半导体封装的截面图。
图2C图示根据本申请的一个实施方式的示例性功率半导体封装的截面图。
图3图示根据本申请的一个实施方式的示例性功率半导体封装的平面顶视图。
具体实施方式
以下描述包含涉及本公开中的实施方式的具体信息。本申请中的附图和它们随附的详细描述仅涉及示例性实施方式。除非另有说明，图之中的相同或对应元件可以由相同或对应附图标记来指示。而且，本申请中的附图和图示通常不是按比例的，并且不旨在对应于实际的相对尺寸。
图1图示根据本申请的一个实施方式的功率转换器的示例性电路图。在本实施方式中，例如，功率转换器电路100包括被配置用于将高输入电压转换为低输出电压的降压转换器。在另一实施方式中，功率转换器电路100可以包括用于将低输入电压转换为高输出电压的电子电路和系统。如图1所示，功率转换器电路100包括半桥102和输出级，半桥102具有驱动器IC 110、功率开关120和功率开关130，输出级具有输出电感器142和输出电容器144。
如图1所示，功率开关120包括具有漏极122、源极124和栅极126的高侧或控制晶体管。功率开关130包括具有漏极132、源极134和栅极136的低侧或同步(下文中为“sync”)晶体管。功率开关120的漏极122耦合到正输入端子160——VIN(+)，而功率开关120的源极124耦合到交换节点140。功率开关120的栅极126耦合到驱动器IC 110，驱动器IC 110向栅极126提供高侧驱动信号(VG1)。如图1所示，功率开关130的漏极132耦合到交换节点140，而功率开关130的源极134耦合到负输入端子162——VIN(-)。功率开关130的栅极136耦合到驱动器IC110，驱动器IC 110向栅极136提供低侧驱动信号(VG2)。
在实施方式中，功率开关120和功率开关130中的至少一个包括诸如硅金属氧化物半导体FET(MOSFET)之类的场效应晶体管(FET)。在另一实施方式中，功率开关120和功率开关130中的至少一个包括III-V族半导体器件，诸如其可以是GaN高电子迁移率晶体管(HEMT)的氮化镓(GaN)器件。在其它实施方式中，功率开关120和130可以是诸如双极结型晶体管(BJT)和绝缘栅双极晶体管(IGBT)之类的任何其它适合控制器件。
根据本实施方式，驱动器IC 110和功率开关120单片集成在半导体裸片104上，并且功率开关130形成在半导体裸片106上。如下面参照图2A、2B、2C和3所讨论的，半导体裸片104和106通过无腿导电接线柱彼此耦合，并且被配置用于附接到功率半导体封装中的引线框架的部分刻蚀区段。
参照图2A、2B和2C，本申请的实施方式关于诸如功率半导体封装200之类的功率半导体封装进行描述，其中半导体裸片204上的驱动器IC 210和功率开关220以及半导体裸片206上的功率开关230可以相应地对应于图1的功率转换器电路100中的半导体裸片104上的驱动器IC 110和功率开关120以及半导体裸片106上的功率开关130，并且同样地连接。
转到图2A，图2A图示根据本申请的一个实施方式的示例性功率半导体封装的平面顶视图。如图2A所示，功率半导体封装200包括：半导体裸片204，具有单片形成在其上的功率开关220和驱动器IC 210；半导体裸片206，具有功率开关230；无腿导电接线柱252，将半导体裸片204电耦合到半导体裸片206；以及基板270。功率半导体封装200还包括引线框架，该引线框架具有至少一个非刻蚀区段(例如非刻蚀区段250a)和部分刻蚀区段(例如部分刻蚀区段250e和250f)。注意，图2A、2B和2C中的每个图中的至少一个非刻蚀区段和部分刻蚀区段统称为引线框架250。
在本实施方式中，半导体裸片204包括单片形成在其上的驱动器IC 210和功率开关220。驱动器IC 210、功率开关220和半导体裸片204可以对应地对应于图1的功率转换器电路100中的驱动器IC 110、功率开关120和半导体裸片104。如图2A所示，功率开关220包括控制晶体管，该控制晶体管具有位于半导体裸片204的顶表面上的功率电极224(例如源电极)以及位于半导体裸片204的底表面上的功率电极(例如漏电极)(图2A中未显式示出)。功率开关220还包括其可以位于半导体裸片204的顶表面或底表面上的控制电极(例如栅电极)(图2A中未显式示出)。
在本实施方式中，在半导体裸片204的底部的功率开关220的功率电极(例如漏电极)通过一个或多个键合接线256以及引线框架250的一个或多个部分刻蚀区段250f电耦合到输入电压(例如，在图1中的正输入端子160处的VIN(+))。例如，一个或多个键合接线256可以通过半导体裸片204中的一个或多个贯通基板的过孔(图2A中未显式示出)耦合到在半导体裸片204的底部的功率开关220的功率电极(例如漏电极)。在半导体裸片204的底部的功率开关220的功率电极(例如漏电极)被配置用于附接到引线框架250的一个或多个部分刻蚀区段(图2A中未显式示出)。在本实施方式中，例如，功率开关220的控制电极(例如栅电极)(图2A中未显式示出)可以通过一个或多个键合接线254、部分刻蚀区段250e以及基板270上的导电迹线(图2A中未显式示出)电耦合到驱动器IC 210。如图2A所示，功率开关220的功率电极224(例如源电极)通过其可以对应于图1的交换节点140的无腿导电接线柱252电耦合到功率开关230的功率电极232(例如漏电极)。无腿导电接线柱252通过引线框架250的非刻蚀区段250a电耦合到基板270。
在本实施方式中，驱动器IC 210形成在半导体裸片204上，并且包括通过图2A中的一个或多个键合接线254电耦合到引线框架250的一个或多个部分刻蚀区段250e的I/O焊盘(图2A中未显式示出)。驱动器IC 210被配置用于例如通过一个或多个键合接线254、部分刻蚀区段250e以及基板270上的导电迹线(图2A中未显式示出)向功率开关220和功率开关230的栅极提供驱动信号。
对比于具有并排形成在单独半导体裸片上的驱动器IC和功率开关的常规功率半导体封装，功率开关220与驱动器IC 210在半导体裸片204上的单片集成可以有利地减小功率半导体封装200的外形规格。如图2A中可见的，功率开关220具有比功率开关230的覆盖区更小的覆盖区。因而，比起将驱动器IC 210和功率开关230集成在同一半导体裸片上，将驱动器IC 210和功率开关220集成在同一半导体裸片上可以更有效地减小功率半导体封装200的外形规格，这是因为驱动器IC 210和功率开关220在半导体裸片204上的集成可以使得半导体裸片204具有比两个单独半导体裸片(如果驱动器IC 210和功率开关220单独形成在那些半导体裸片上)的组合覆盖区更小的覆盖区。
如图2A所示，半导体裸片206包括功率开关230。半导体裸片206和功率开关230可以对应地对应于图1的功率转换器电路100中的半导体裸片106和功率开关130。功率开关230包括sync晶体管，该sync晶体管具有位于半导体裸片206的顶表面上的功率电极232(例如漏电极)、以及(图2A中未显式示出的)位于半导体裸片206的底表面上的功率电极(例如源电极)和控制电极(例如栅电极)。在本实施方式中，功率开关220的功率电极224(例如源电极)通过其可以对应于图1中的交换节点140的无腿导电接线柱252电耦合到功率开关230的功率电极232(例如漏电极)。无腿导电接线柱252转而通过引线框架250的非刻蚀区段250a电耦合到基板270。
除了图2A所示的非刻蚀区段250a以及部分刻蚀区段250e和250f之外，引线框架250还包括在半导体裸片206之下的部分刻蚀区段250b和250c以及在半导体裸片204之下的部分刻蚀区段250d，其中部分刻蚀区段250b、250c和250d示于图2B和2C中。非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f是引线框架250的不同部分，其中非刻蚀区段250a保有引线框架250的全厚度，而部分刻蚀区段250b、250c、250d、250e和250f被刻蚀，从而具有引线框架250的全厚度的一部分(例如，非刻蚀区段250a的厚度的一半或四分之一)。引线框架250的非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f物理上彼此分开。在本实施方式中，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f由相同材料制成，并且具有基本上均一(uniform)的成分。在另一实施方式中，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f可以由不同材料制成，并且具有不同成分。在本实施方式中，部分刻蚀区段250b、250c、250d、250e和250f具有其为非刻蚀区段250a的全厚度的一部分的基本上均匀的厚度。在另一实施方式中，部分刻蚀区段250b、250c、250d、250e和250f可以具有不同厚度。在一个实施方式中，引线框架250的区段250e和250f可以是非刻蚀区段。
由于半导体裸片204和206位于引线框架250的部分刻蚀区段而不是非刻蚀区段上，可以减小功率半导体封装200中的半导体裸片204和206的总高度，使得可以消除常规导电接线柱中采用的腿部分。在本实施方式中，无腿导电接线柱252具有基本上平坦的本体，而没有腿部分。对比于具有附接到非刻蚀引线区段的半导体裸片和具有腿部分的导电接线柱的常规功率半导体封装，本申请的实施方式利用引线框架的至少一个非刻蚀区段(例如非刻蚀区段250a)和部分刻蚀区段(例如图2B和2C中的部分刻蚀区段250b、250c和250d)以使得半导体裸片(例如半导体裸片204和206)能够使用无腿导电接线柱(例如无腿导电接线柱252)彼此耦合并且耦合到基板(例如基板270)。结果，可以减小功率半导体封装200的总高度，这转而减小功率半导体封装200的外形规格。而且，通过采用无腿导电接线柱252以及被配置用于附接到部分刻蚀区段(例如图2B和2C中的部分刻蚀区段250b、250c和250d)的半导体裸片204和206，可以调整无腿导电接线柱252的厚度以改善载流能力，从而适应特定实施方式的需要，而不会大幅影响功率半导体封装200的总高度。
在本实施方式中，无腿导电接线柱252包括铜。在另一实施方式中，无腿导电接线柱252可以包括诸如铝或钨之类的任何适合导电材料。在本实施方式中，引线框架250的非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f可以包括诸如铜、铝或钨之类的金属、金属合金、三金属、或者其它导电材料。在本实施方式中，基板270可以是诸如印刷电路板(PCB)之类的电路板或者任何其它适合基板。
转到图2B，图2B图示根据本申请的一个实施方式的示例性功率半导体封装的截面图。在实施方式中，图2B图示沿着图2A中的线B-B的功率半导体封装200的截面图。如图2B所示，功率半导体封装200包括：半导体裸片204，具有单片形成在其上的功率开关220和驱动器IC 210；半导体裸片206，具有功率开关230；引线框架250，具有非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e；无腿导电接线柱252，将半导体裸片204电耦合到半导体裸片206；以及基板270。
如图2B所示，半导体裸片204包括驱动器IC 210和功率开关220。功率开关220包括控制晶体管，该控制晶体管具有位于半导体裸片204的顶表面上的功率电极224(例如源电极)以及位于半导体裸片204的底表面上的功率电极222(例如漏电极)。功率开关220还包括其可以位于半导体裸片204的顶表面或底表面上并且电耦合到驱动器IC 210的控制电极(例如栅电极)(图2B中未显式示出)。驱动器IC 210通过键合接线254耦合到引线框架250的部分刻蚀区段250e。例如，驱动器IC 210被配置为通过键合接线(例如键合接线254)、部分刻蚀区段(例如部分刻蚀区段250e)、以及基板270上的导电迹线(图2B中未显式示出)向功率开关220和功率开关230的栅极提供驱动信号。
如图2B所示，驱动器IC 210和功率开关220单片集成在半导体裸片204上。对比于具有并排形成在单独半导体裸片上的驱动器IC和功率开关的常规功率半导体封装，功率开关220与驱动器IC 210在半导体裸片204上的单片集成可以有利地减小功率半导体封装200的外形规格。如图2B中可见的，功率开关220具有比功率开关230的覆盖区更小的覆盖区。因而，比起将驱动器IC 210和功率开关230集成在同一半导体裸片上，将驱动器IC 210和功率开关220集成在同一半导体裸片上可以更有效地减小功率半导体封装200的外形规格，这是因为驱动器IC 210和功率开关220在半导体裸片204上的集成可以使得半导体裸片204具有比两个单独半导体裸片(如果驱动器IC 210和功率开关220单独形成在那些半导体裸片上)的组合覆盖区更小的覆盖区。
如图2B所示，半导体裸片206包括功率开关230。功率开关230包括sync晶体管，该sync晶体管具有位于半导体裸片206的顶表面上的功率电极232(例如漏电极)、以及位于半导体裸片206的底表面上的功率电极234(例如源电极)和控制电极236(例如栅电极)。在本实施方式中，功率开关220的功率电极224(例如源电极)通过其可以对应于图1中的交换节点140的无腿导电接线柱252电耦合到功率开关230的功率电极232(例如漏电极)。无腿导电接线柱252转而通过引线框架250的非刻蚀区段250a电耦合到基板270。
应该理解的是，功率开关220的功率电极224和功率开关230的功率电极232中的每个均可以通过导电粘合剂(图2B中未显式示出)电耦合和机械耦合到无腿导电接线柱252。相似地，功率开关220的功率电极222、功率开关230的功率电极234和控制电极236可以通过导电粘合剂(图2B中未显式示出)电耦合和机械耦合到引线框架250的相应部分刻蚀区段250d、250b和250c。而且，引线框架250的非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e可以通过任何适合导电粘合剂材料电耦合和机械耦合到基板270。
如图2B所示，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d、250e和250f是引线框架250的不同部分，其中非刻蚀区段250a保有引线框架250的全厚度，而部分刻蚀区段250b、250c、250d、250e和250f被刻蚀，从而具有引线框架250的全厚度的一部分(例如，非刻蚀区段250a的厚度的一半或四分之一)。在一个实施方式中，部分刻蚀区段250b、250c、250d和250e可以通过首先用掩模覆盖非刻蚀区段250a、移除(例如通过刻蚀)引线框架250的未被掩模覆盖的部分(所产生的部分刻蚀区段250b、250c、250d和250e具有基本上均匀的厚度)、然后在部分刻蚀区段250b、250c、250d和250e之上形成掩模、以及进一步移除(例如通过刻蚀通过整个厚度)引线框架250的未被掩模覆盖的部分而形成。结果，引线框架250的非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e物理上彼此分开，其中非刻蚀区段250a保有引线框架250的全厚度，而部分刻蚀区段250b、250c、250d和250e具有其是引线框架250的全厚度的一部分的基本上均匀的厚度。
在本实施方式中，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e由相同材料制成，并且具有基本上均一的成分。在另一实施方式中，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e可以由不同材料制成，并且具有不同成分。在本实施方式中，部分刻蚀区段250b、250c、250d和250e具有基本上均匀的厚度。在另一实施方式中，部分刻蚀区段250b、250c、250d和250e可以具有不同厚度。
在本实施方式中，因为引线框架250的部分刻蚀区段250b、250c、250d和250e具有非刻蚀区段250a的全厚度的一部分，例如，半导体裸片204和206可以附接到部分刻蚀区段250b、250c和250d，从而使得半导体裸片204和206具有与引线框架250的非刻蚀区段250a基本上共面的顶表面。而且，由于半导体裸片204和206位于引线框架250的部分刻蚀区段而不是非刻蚀区段上，可以减小功率半导体封装200中的半导体裸片204和206的总高度，使得可以消除常规导电接线柱中采用的腿部分。对比于具有附接到非刻蚀引线区段的半导体裸片和具有腿部分的导电接线柱的常规功率半导体封装，功率半导体封装200利用引线框架250的非刻蚀区段250a和部分刻蚀区段250b、250c和250d以使得半导体裸片204和206能够通过使用无腿导电接线柱252彼此耦合并且耦合到基板270。如图2B所示，无腿导电接线柱252具有基本上平坦的本体，该基本上平坦的本体具有基本上均匀的厚度。
除了别的优点之外，功率开关220与驱动器IC 210在半导体裸片204上的单片集成减小了功率半导体封装200的外形规格。而且，通过利用部分刻蚀区段250b、250c和250d将功率开关220和230耦合到基板270，并且通过将功率开关220的功率电极224(例如源电极)和功率开关230的功率电极232(例如漏电极)通过无腿导电接线柱252耦合到基板270，功率半导体封装200可以实现增加的载流能力以及减小的电阻、外形规格、复杂度和成本(当相比于排他地使用与具有腿部分的导电接线柱组合的非刻蚀引线框架的常规封装技术时)。而且，由无腿导电接线柱252提供的大表面积允许更高效的开关电流传导。
转到图2C，图2C图示根据本申请的一个实施方式的示例性功率半导体封装的截面图。在实施方式中，图2C图示沿着图2A中的线B-B的功率半导体封装200的截面图。利用表示图2B中的相似特征的相似数字，图2C中的功率半导体封装200包括：半导体裸片204，具有单片形成在其上的功率开关220和驱动器IC 210；半导体裸片206，具有功率开关230；引线框架250，具有非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e；无腿导电接线柱252，将半导体裸片204电耦合到半导体裸片206；以及基板270。
与图2B中的功率半导体封装相似，半导体裸片204包括驱动器IC 210和功率开关220。功率开关220包括控制晶体管，该控制晶体管具有位于半导体裸片204的顶表面上的功率电极224(例如源电极)以及位于半导体裸片204的底表面上的功率电极222(例如漏电极)。功率开关220还包括(图2C中未显式示出的)其可以位于半导体裸片204的顶表面或底表面上的控制电极(例如栅电极)。驱动器IC 210通过键合接线254耦合到引线框架250的部分刻蚀区段250e。驱动器IC 210被配置为向功率开关220和230的栅极提供驱动信号。与图2B中的功率半导体封装相似，功率开关220与驱动器IC 210在半导体裸片204上的单片集成可以有利地减小功率半导体封装200的外形规格。
如图2C所示，半导体裸片206包括功率开关230。功率开关230包括sync晶体管，该sync晶体管具有位于半导体裸片206的顶表面上的功率电极232(例如源电极)、以及(图2A中未显式示出的)位于半导体裸片206的底表面上的功率电极(例如漏电极)和控制电极(例如栅电极)。在本实施方式中，功率开关220的功率电极224(例如源电极)通过其对应于图1中的交换节点140的无腿导电接线柱252电耦合到功率开关230的功率电极232(例如漏电极)。无腿导电接线柱252转而通过引线框架250的非刻蚀区段250a电耦合到基板270。
如图2C所示，非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e是引线框架250的不同部分，其中非刻蚀区段250a保有引线框架250的全厚度，而部分刻蚀区段250b、250c、250d和250e被刻蚀，从而具有引线框架250的全厚度的一部分(例如，非刻蚀区段250a的厚度的一半或四分之一)。引线框架250的非刻蚀区段250a以及部分刻蚀区段250b、250c、250d和250e物理上彼此分开，并且具有基本上均匀的厚度。
与图2B中的功率半导体封装相似，非刻蚀区段250a以及部分刻蚀区段250b、250c和250d的组合使得半导体裸片204和206能够通过使用无腿导电接线柱252彼此耦合并且耦合到基板270。而且，由于利用引线框架250的非刻蚀区段250a、部分刻蚀区段250b、250c和250d以及无腿导电接线柱252，减小了功率半导体封装200的总高度，这转而减小了功率半导体封装200的外形规格。
如图2C所示，半导体裸片204和半导体裸片206具有不同厚度。在本实施方式中，具有功率开关230的半导体裸片206比具有驱动器IC 210和功率开关220的半导体裸片204显著更薄。在本实施方式中，图2C中的半导体裸片204具有与图2B中的半导体裸片204的厚度可比拟的厚度，而图2C中的半导体裸片206比图2B中的半导体裸片206显著更薄。如图2C中可见的，引线框架250的非刻蚀区段250a和半导体裸片206具有基本上共面的顶表面。因为半导体裸片206的厚度比图2B中的半导体裸片206的厚度更薄，并且因为引线框架250的非刻蚀区段250a和半导体裸片206具有基本上共面的顶表面，所以图2C中的引线框架250的非刻蚀区段250a具有比图2B中的非刻蚀区段250a的厚度更小的减小的厚度。因而，相比于图2B中的功率半导体封装，功率半导体封装200的总高度在图2C中进一步减小。
在本实施方式中，无腿导电接线柱252具有非刻蚀部分252a和部分刻蚀部分252b。无腿导电接线柱252的部分刻蚀部分252b被配置为提供用于半导体裸片204的余隙，使得功率开关220的功率电极224(例如源电极)可以电耦合和机械耦合到无腿导电接线柱252的部分刻蚀部分252b。相比于图2B中的功率半导体封装，半导体裸片206的厚度减小与具有部分刻蚀部分252b的无腿导电接线柱252可以减小图2C中的功率半导体封装200的总高度，这是因为无腿导电接线柱252的在半导体裸片204上方的部分刻蚀部分252b具有相比于图2B中的无腿导电接线柱252的在半导体裸片204上方的部分减小的厚度。此外，通过采用具有部分刻蚀部分252b的无腿导电接线柱252以及被配置为附接到引线框架250的部分刻蚀区段250b、250c和250d的半导体裸片204和206，可以调整无腿导电接线柱252的厚度，以改善载流能力，从而适应特定实施方式的需要，而不会大幅影响功率半导体封装200的总高度。而且，由无腿导电接线柱252提供的大表面积允许更高效的开关电流传导。
转到图3，图3图示根据本申请的一个实施方式的示例性功率半导体封装的平面顶视图。如图3所示，功率半导体封装300包括：半导体裸片304，具有单片形成在其上的功率开关320和驱动器IC 310；半导体裸片306，具有功率开关330；引线框架350，具有非刻蚀区段350a和部分刻蚀区段(例如部分刻蚀区段350e和350f)；无腿导电接线柱352；以及基板370。
在本实施方式中，半导体裸片304上的驱动器IC 310和功率开关320、以及半导体裸片306上的功率开关330可以对应地对应于图1的功率转换器电路100中的半导体裸片104上的驱动器IC 110和功率开关120、以及半导体裸片106上的功率开关130，并且同样地连接。在本实施方式中，具有功率开关320和驱动器IC 310的半导体裸片304、具有功率开关330的半导体裸片306、引线框架350的非刻蚀区段350a以及部分刻蚀区段350e和350f、无腿导电接线柱352、以及基板370可以对应地对应于图2A中的具有功率开关220和驱动器IC210的半导体裸片204、具有功率开关230的半导体裸片206、引线框架250的非刻蚀区段250a以及部分刻蚀区段250e和250f、无腿导电接线柱252、以及基板270。
对比于其中利用一个或多个键合接线256的图2A中的功率半导体封装200，如图3所示，导电接线柱358被配置为通过半导体裸片304中的一个或多个贯通基板的过孔(图3中未显式示出)将在半导体裸片304底部的功率开关320的功率电极(例如漏电极)电耦合到输入电压(例如，图1中的正输出端子164——VOUT(+))。在本实施方式中，导电接线柱358是无腿导电接线柱。在另一实施方式中，导电接线柱358可以包括腿部分。
如图3所示，由于半导体裸片304和306位于引线框架350的部分刻蚀区段而不是非刻蚀区段上，可以减小功率半导体封装300中的半导体裸片304和306的总高度，使得可以消除常规导电接线柱中采用的腿部分。在本实施方式中，无腿导电接线柱352具有基本上平坦的本体，而没有腿部分。对比于具有附接到非刻蚀引线区段的半导体裸片和具有腿部分的导电接线柱的常规功率半导体封装，本申请的实施方式利用引线框架的至少一个非刻蚀区段(例如非刻蚀区段350a)和(例如与图2B和2C中的部分刻蚀区段250b、250c和250d相似的)部分刻蚀区段以使得半导体裸片(例如半导体裸片304和306)能够使用无腿导电接线柱(例如无腿导电接线柱352)彼此耦合并且耦合到基板(例如基板370)。结果，可以减小功率半导体封装300的总高度，这可以转而减小功率半导体封装300的外形规格。而且，通过采用无腿导电接线柱352以及被配置用于附接到部分刻蚀区段的半导体裸片304和306，可以调整无腿导电接线柱352的厚度以改善载流能力，从而适应特定实施方式的需要，而不会大幅影响功率半导体封装300的总高度。因而，除了别的优点之外，功率半导体封装300还可以实现增加的载流能力以及减小的电阻、外形规格、复杂度和成本(当相比于排他地使用与具有腿部分的导电接线柱组合的非刻蚀引线框架的常规封装技术时)。而且，由无腿导电接线柱352提供的大表面积允许更高效的开关电流传导。附加地，由导电接线柱358提供的大表面积允许更高效的输入电流传导。
根据上面的描述，明显的是，各种技术可以用于实现本申请中描述的概念，而不脱离那些概念的范围。而且，虽然已经具体参照某些实施方式描述了概念，本领域普通技术人员将认识到，可以在形式和细节方面做出改变，而不脱离那些概念的范围。因此，所描述的实施方式要在所有方面被视为说明性而非限制性的。还应该理解的是，本申请不限于上述特定实施方式，而是许多重排、修改和替换是可能的，而不脱离本公开的范围。

Claims (20)

1.一种功率半导体封装，包括：
引线框架，具有部分刻蚀区段和至少一个非刻蚀区段；
第一半导体裸片，具有单片形成在其上的第一功率晶体管和驱动器集成电路(IC)；
第二半导体裸片，具有第二功率晶体管；以及
无腿导电接线柱，具有部分刻蚀部分，并且具有沿着与所述部分刻蚀部分和从所述部分刻蚀部分延伸的非刻蚀部分共同的表面的长度；
其中所述第一半导体裸片和所述第二半导体裸片被配置用于附接到所述部分刻蚀区段；
其中所述部分蚀刻部分耦合到所述第一半导体裸片，并且所述非刻蚀部分耦合到所述第二半导体裸片；以及
其中所述部分刻蚀区段和所述至少一个非刻蚀区段使得所述第一半导体裸片能够通过所述无腿导电接线柱耦合到所述第二半导体裸片。
2.根据权利要求1所述的功率半导体封装，其中所述第一功率晶体管的功率电极通过所述无腿导电接线柱耦合到所述第二功率晶体管的功率电极。
3.根据权利要求1所述的功率半导体封装，其中所述第一功率晶体管是降压转换器中的控制晶体管，并且所述第二功率晶体管是降压转换器中的同步晶体管。
4.根据权利要求1所述的功率半导体封装，其中所述第一功率晶体管和所述第二功率晶体管中的至少一个功率晶体管包括硅。
5.根据权利要求1所述的功率半导体封装，其中所述第一功率晶体管和所述第二功率晶体管中的至少一个功率晶体管包括氮化镓(GaN)。
6.根据权利要求1所述的功率半导体封装，其中所述第一功率晶体管和所述第二功率晶体管中的至少一个功率晶体管是从由场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)和高电子迁移率晶体管(HEMT)组成的组中选择的。
7.根据权利要求1所述的功率半导体封装，其中所述无腿导电接线柱包括铜。
8.根据权利要求1所述的功率半导体封装，其中所述无腿导电接线柱具有均匀的厚度。
9.根据权利要求1所述的功率半导体封装，其中所述无腿导电接线柱将所述第一半导体裸片和所述第二半导体裸片电耦合到所述引线框架的所述至少一个非刻蚀区段。
10.根据权利要求1所述的功率半导体封装，其中所述第一半导体裸片被配置用于附接到所述部分刻蚀区段的第一部分刻蚀区段，并且所述第二半导体裸片被配置用于附接到所述部分刻蚀区段的与所述第一部分刻蚀区段不同的第二部分刻蚀区段，并且其中所述第一部分刻蚀区段和所述第二部分刻蚀区段以及所述至少一个非刻蚀区段使得所述第一半导体裸片能够通过所述无腿导电接线柱耦合到所述第二半导体裸片。
11.根据权利要求1所述的功率半导体封装，其中所述无腿导电接线柱具有另一表面，并且所述第一功率晶体管的功率电极和所述第二功率晶体管的功率电极沿着所述另一表面耦合到所述无腿导电接线柱。
12.一种功率半导体封装，包括：
引线框架，具有部分刻蚀区段和至少一个非刻蚀区段；
第一半导体裸片，具有第一功率FET；
第二半导体裸片，具有第二功率FET；以及
无腿导电接线柱，具有平坦的本体和均匀的厚度；
其中所述第一半导体裸片和所述第二半导体裸片被配置用于附接到所述部分刻蚀区段，并且所述引线框架的所述部分刻蚀区段具有均匀的厚度；
其中所述部分刻蚀区段和所述至少一个非刻蚀区段使得所述第一半导体裸片能够通过所述无腿导电接线柱耦合到所述第二半导体裸片；以及
其中所述无腿导电接线柱通过所述至少一个非刻蚀区段电耦合到基板。
13.根据权利要求12所述的功率半导体封装，进一步包括与所述第一功率FET单片形成在所述第一半导体裸片上的驱动器集成电路(IC)。
14.根据权利要求12所述的功率半导体封装，其中所述第一功率FET的源电极通过所述无腿导电接线柱耦合到所述第二功率FET的漏电极。
15.根据权利要求12所述的功率半导体封装，其中所述第一功率FET是功率转换器中的控制晶体管，并且所述第二功率FET是功率转换器中的同步晶体管。
16.根据权利要求12所述的功率半导体封装，其中所述第一功率FET和所述第二功率FET中的至少一个功率FET包括硅FET或者GaN FET。
17.根据权利要求12所述的功率半导体封装，其中所述无腿导电接线柱包括铜。
18.根据权利要求12所述的功率半导体封装，其中所述无腿导电接线柱具有部分刻蚀部分。
19.根据权利要求12所述的功率半导体封装，其中所述无腿导电接线柱将所述第一半导体裸片和所述第二半导体裸片电耦合到所述至少一个非刻蚀区段。
20.根据权利要求12所述的功率半导体封装，其中所述第一半导体裸片被配置用于附接到所述部分刻蚀区段的第一部分刻蚀区段，并且所述第二半导体裸片被配置用于附接到所述部分刻蚀区段的与所述第一部分刻蚀区段不同的第二部分刻蚀区段，并且其中所述第一部分刻蚀区段和所述第二部分刻蚀区段以及所述至少一个非刻蚀区段使得所述第一半导体裸片能够通过所述无腿导电接线柱耦合到所述第二半导体裸片。
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