CN105652703A - Timer circuit and method capable of calculating delayed time automatically - Google Patents
Timer circuit and method capable of calculating delayed time automatically Download PDFInfo
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- CN105652703A CN105652703A CN201410680243.4A CN201410680243A CN105652703A CN 105652703 A CN105652703 A CN 105652703A CN 201410680243 A CN201410680243 A CN 201410680243A CN 105652703 A CN105652703 A CN 105652703A
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Abstract
The invention relate to a timer circuit capable of calculating delayed time automatically. The timer circuit comprises a timer and a timing control circuit connected with the timer. The timer is used for generating a count value, inputting an enabling signal, and sending the count value to the timing control circuit; and the timing control circuit is used for carrying out latching comparison based on inputted delay time information and outputting a comparison result. According to the method, the timer capable of calculating delayed time automatically is completed based on hardware calculation for a delay latching value, a traditional timer, and timing mode control. The timer circuit is composed of a delay-time latch circuit and a timing mode circuit and the like and a delayed time value can be calculated directly, so that a defect of a requirement of processor participation in calculation according to the traditional design can be overcome, the processor resource cost is reduced, and convenience is provided for the full-hardware realization protocol.
Description
Technical field
The present invention relates to a kind of can the timer circuit of computation delay and method automatically, be a kind of hardware implementing towards industry wireless network standard specifically, on sheet, system level chip can the timer circuit of computation delay and method.
Background technology
WIA-PA (WirelessNetworksforIndustrialAutomationProcessAutomation is towards the industry wireless network standard technique of industrial process automation) standard is the WIA standard that Chinese industrial Wireless Consortion formulates for process automatic field, is the wireless network system for technical process measurement, supervisory and control based on IEEE802.15.4 standard (hereinafter referred to as WIA agreement). WIA agreement needs comprise a large amount of timing demands, as regularly opened receptor, receive time-out time-out timing, regularly open transmitter, channel switching timing etc.
Two kinds of methods are generally had to solve this kind of a large amount of timing demand at present: one adopts multiple timer, each timer solves a kind of timing problems, this kind of method needs dependence to realize at timer in a large number, and logic resource, the current consumption of system is all brought passive impact; Another kind of method adopts single timer, when carrying out delay timing and operate, it is necessary to treater reads current timing value, is then added with timing value by delay value, then writes back timing comparative figure, and this result in again the waste of treater resource.
Summary of the invention
For above-mentioned technical deficiency, it is an object of the invention to provide a kind of industry wireless network standard technique protocol realization towards industrial process automation, on sheet, system level chip can the timer circuit of computation delay automatically. Traditional circuit is comprised two improvement by this circuit: first is the increase in delay computation circuitry; 2nd is support multi-way shared pattern, it is possible to realize the function of multichannel timing simultaneously under a timer.
The present invention solves its technical problem by the following technical solutions: a kind of can the timer circuit of computation delay automatically, comprise timer and connected timing control circuit;
Described timer, for generation of counting value, inputs enable signal, sends counting value to timing control circuit;
Timing control circuit is used for carrying out latch according to the delayed data inputted and compares, and exports comparative result.
Described delayed data comprises delay value, time delay loading, timing mode selection, exports model selection.
Described timing control circuit is multiple.
Described timing control circuit comprises time delay latch cicuit, timing matching circuit, timing mode circuit, exports mode selection circuit; Described time delay latch cicuit is connected with timing matching circuit, timing mode circuit, and timing matching circuit is connected with timing mode circuit, output mode selection circuit.
Described timing control circuit
Time delay latch cicuit is used for the timing value inputted and delay value being sued for peace and latches, and exports time delay latched value to timing matching circuit, receives the latch signal of timing mode circuit;
Timing matching circuit, for timing value and time delay latched value being compared, exports comparative result to exporting mode selection circuit, receives the enable signal of timing mode circuit;
Timing mode circuit is for controlling single timing mode or cycle timing mode, and input time delay loads, timing mode selects information, also receives the comparative result of timing matching circuit, output latch signal and relatively enable signal;
Export mode selection circuit for controlling to produce the output of pulse or level mode, receive the Output rusults exporting mode selecting information and timing matching circuit, produce comparison match signal and export.
Can the timer method of computation delay automatically, comprise the following steps:
A., when enable signal is effective, timer circuit work also exports counting value continuously;
B. under time delay load signal effect, the latch signal of timing mode circuit evolving pulse, and produce more enable signal to timing matching circuit;
C. time delay latch cicuit receives the latch signal of timing mode circuit, and when it is effective, timing value and delay value is carried out addition summation operation and latch, and then exports delay latch signal to timing matching circuit;
D. timing matching circuit receives more enable signal, time delay latched value and timing value, when more enable signal is effective, time delay latched value and timing value is compared, and exports comparative result when the two is equal;
E., when timing mode is chosen as single timing mode, timing mode circuit, after receiving comparative result, is forbidden exporting more enable signal;
F. mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing.
When timing mode is chosen as continuous timing mode, timing mode circuit, after receiving comparative result, continues to generate latch signal pulse; Output mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing; Then step c is returned.
The present invention has following useful effect and advantage:
1. circuit face of the present invention is to the hardware implementing of industrial wireless network protocol standard, system level chip field on sheet, it is provided that a kind of can the timer circuit of computation delay.
2. circuit of the present invention adopts single timer, the structure of timing control circuit multiplexer, solves the shortcoming that tradition uses multiple timer, saves logic resource.
3. circuit of the present invention comprises the structure such as time delay latch cicuit, timing mode circuit, can directly carry out delay value calculating, avoiding traditional design needs treater to participate in the shortcoming calculated, and decreases treater resource overhead, also provides conveniently for devices at full hardware realizes agreement.
Accompanying drawing explanation
Fig. 1 is the structure block diagram of the present invention;
Fig. 2 is the structure block diagram of timing control circuit;
Embodiment
Below in conjunction with embodiment, the present invention is described in further detail.
Can the timer circuit of computation delay automatically, comprise timer circuit and timing control circuit two portions composition. Wherein timer circuit only needs one, and timing control circuit can comprise multiple.
Can the input/output port of the timer circuit of computation delay automatically comprise: external input port comprises that timer is enable, delay value, time delay loading, timing mode are selected, exported a model selection, and output port comprises comparison match. Wherein timer enable port only 1; Delay value, time delay loading, timing mode selection, output model selection and comparison match port form one group, when comprising multiple timing control circuit, can comprise and organize delay value, time delay loading, timing mode selection, output model selection and comparison match port more.
Timer circuit is under the control of enable signal, it is provided that counting value exports. This counting value can stablize, increases progressively, in satisfied timing length prerequisite periodical timing. This counting value can be subsequent conditioning circuit and provides time reference, compares interruption for generation of timing. Can in the timer circuit of computation delay automatically a kind of described in patent of the present invention, the timing value port of all timing control circuit accesses by the counting value port of timer circuit, and namely timer circuit is unique.
The function of timing control circuit comprises timing mode control, time delay is latched, timing coupling, output Schema control etc. The timing mode support of timing control circuit is timing and single timing two kinds of patterns periodically. The time delay latch of timing control circuit refers to, under the effect of latch signal, the delay value of the timing value of current timer circuit and outside input is carried out addition summation, and will ask and add result latch in a register. The timing coupling of timing control circuit refers to that the timing value of value and the timer circuit latch time delay compares, and generates comparison match signal. The output Schema control of timing control circuit supports that level exports pattern and edge exports pattern two kinds of patterns. Can in the timer circuit of computation delay automatically a kind of described in patent of the present invention, timing control circuit is not unique, it is possible to comprise multiple timing control circuit. Each timing control circuit can complete the function of a road timer, it is possible to by the function of multiple timing control circuit realiration multi-path timer.
Single time timing mode refers to that timer only completes once timing operation, produces the comparison match signal of single time; Cycle timing mode refers to and generates timing operation continuously, produces periodic comparison match signal.
The principles illustrated of circuit of the present invention is as follows:
Described timer circuit is cumulative type timer, comprises enable control. When enable control is effective, can continuous counter, when occur overflow time, again count from 0.
The effect of timing control circuit is the timer realizing one group of automatic computation delay. In actual applications, according to different function demands, it is possible to by multiple timing control circuit.
Described timing control circuit is made up of four partial circuits, is respectively time delay latch cicuit, timing matching circuit, timing mode circuit and exports mode selection circuit.
The effect of the time delay latch cicuit in described timing control circuit is the next time delay comparative figure of calculating and latches.
The effect of the timing matching circuit in timing control circuit is under the control of enable signal, compares current timing value and latches time delay signal, generates indicator signal when the two is equal.
Timing mode circuit in timing control circuit has two effects: one is realize timing mode to select control, it may be achieved single delay timing and periodically delay timing; Another realizes time delay Loading Control, comprises the support to two kinds of timing modes.
The effect of the output mode selection circuit in timing control circuit is as required, it is possible to generates pulse and exports comparison match signal or level output comparison match signal two kinds of patterns.
The timer control method of the present invention comprises following step:
A., when enable signal is effective, timer circuit work also exports counting value continuously;
B. under time delay load signal effect, the latch signal of timing mode circuit evolving pulse, and produce more enable signal to timing matching circuit;
C. time delay latch cicuit receives the latch signal of timing mode circuit, and when it is effective, timing value and delay value is carried out addition summation operation and latch, and then exports delay latch signal to timing matching circuit;
D. timing matching circuit receives more enable signal, time delay latched value and timing value, when more enable signal is effective, time delay latched value and timing value is compared, and exports comparative result when the two is equal;
E., when timing mode is chosen as single timing mode, timing mode circuit, after receiving comparative result, is forbidden exporting more enable signal;
F. mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing.
When timing mode is chosen as continuous timing mode, timing mode circuit, after receiving comparative result, continues to generate latch signal pulse; Output mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing; Then step c is returned.
The present embodiment uses Verilog code to write, it is possible to use SynopsysDesignCompiler synthesis tool comprehensively realizes.
The present embodiment structure block diagram and the relation of connection are as shown in Figure 1. In the present embodiment, it is achieved the timer of 3 groups of automatic computation delays. The present embodiment only embodies a kind of implementation of patent of the present invention, according to actual needs, it is possible to increase or reduce the number of timing control circuit.
What the present embodiment realized can the input/output port of the timer circuit of computation delay automatically comprise: external input port comprises that timer is enable, delay value 1, time delay load 1, timing mode selects 1, export model selection 1, delay value 2, time delay load 2, timing mode selects 2, export model selection 2, delay value 3, time delay load 3, timing mode selects 3, output model selection 3; External output port comprises comparison match 1, comparison match 2, comparison match 3.
The present embodiment realize can the timer circuit of computation delay automatically, its Functional Module draws together timer module, timing control module 1, timing control module 2, timing control module 3.
The connection relation of the present embodiment is as follows: the enable port of the enable signal access timer module of the timer of outside input, and the counting value port of timer module exports counter value signal; Timer module exports the timing value port of counter value signal access timing control circuit 1, the delay value 1 of outside input accesses the delay value port of timing control circuit 1, the time delay of outside input loads the time delay load port of 1 access timing control circuit 1, the timing mode of outside input selects the timing mode of 1 access timing control circuit 1 to select port, the output model selection 1 of outside input accesses the output model selection port of timing control circuit 1, and the comparison match port of timing control circuit 1 exports comparison match 1 signal;Timer module exports the timing value port of counter value signal access timing control circuit 2, the delay value 2 of outside input accesses the delay value port of timing control circuit 2, the time delay of outside input loads the time delay load port of 2 access timing control circuit 2, the timing mode of outside input selects the timing mode of 2 access timing control circuit 2 to select port, the output model selection 2 of outside input accesses the output model selection port of timing control circuit 1, and the comparison match port of timing control circuit 2 exports comparison match 2 signal; Timer module exports the timing value port of counter value signal access timing control circuit 3, the delay value 3 of outside input accesses the delay value port of timing control circuit 3, the time delay of outside input loads the time delay load port of 3 access timing control circuit 3, the timing mode of outside input selects the timing mode of 3 access timing control circuit 3 to select port, the output model selection 3 of outside input accesses the output model selection port of timing control circuit 3, and the comparison match port of timing control circuit 3 exports comparison match 3 signal.
Timing control module 1 in the present embodiment, timing control module 2, timing control module 3 are 3 identical circuit, have identical input/output port and circuit structure, i.e. timing control circuit described in summary of the invention.
The input port of the timing control circuit in the present embodiment comprises timing value, delay value, time delay loading, timing mode selection, exports model selection; Output port comprises comparison match result.
As shown in Figure 2, the Functional Module of the timing control circuit in the present embodiment draws together time delay latch cicuit, timing mode circuit, output mode selection circuit, timing matching circuit.
What the present embodiment realized can adopt general purpose timer circuit layout by the timer circuit timer circuit in the timer circuit of computation delay automatically, and it inputs port is enable, and output port is counting value.
The connection relation of timing control circuit is as follows: the A port of the timing value signal access delay latch cicuit of outside input, the D port of the delay value signal access delay latch cicuit of outside input, the LD port of the load signal access delay counting circuit that timing mode circuit exports, the C port output latch time delay signal of time delay latch cicuit; The A port of the latch time delay signal access timing matching circuit that time delay latch cicuit exports, the B port of the timing value signal access timing matching circuit of outside input, the EN port of the timing match-enable signal access timing matching circuit of timing mode circuit evolving, the C port of timing matching circuit exports timing matched signal; The A port of the timing matched signal access timing mode circuit that timing matching circuit exports, the B port of the time delay load signal access timing mode circuit of outside input, the timing mode of outside input selects the M port of signal access timing mode circuit, the C port of timing mode circuit exports load signal, and the D port of timing mode circuit exports timing match-enable signal; The M port of the output mode select signal input and output mode selection circuit of outside input, the C port exporting mode selection circuit exports comparison match signal.
The behavior description of time delay latch cicuit is when latch signal LD is effective, and the value of port A is added with the value of port D and latches in a register, and exports in port C.
The behavior description of timing matching circuit is the value of value and the port B comparing port A, and when the value of both is equal, port C exports useful signal, otherwise exports invalid signals.
The behavior description of timing mode circuit, for, after time delay load signal is effective, arranging delay timing mark effective, exports useful signal at C port simultaneously. Under single delay timing pattern, in the effective situation of delay timing mark, when A port inputs useful signal, cancel delay timing mark; Under periodicity delay timing pattern, even if A port input useful signal, the state of delay timing mark remains unchanged. Under periodicity delay timing pattern, when A port inputs useful signal, C port exports useful signal.
The behavior description exporting mode selection circuit is for when being chosen as the level way of output, when A port is effective, it is carried out latching output by C port, keeps level state; When being chosen as the pulse way of output, C port directly exports useful signal; The state of C port can be cancelled by exporting the selection of pattern. The output of C port and the comparison match output signal of timing control circuit.
Claims (7)
1. one kind can the timer circuit of computation delay automatically, it is characterised in that: comprise timer and connected timing control circuit;
Described timer, for generation of counting value, inputs enable signal, sends counting value to timing control circuit;
Timing control circuit is used for carrying out latch according to the delayed data inputted and compares, and exports comparative result.
2. according to claim 1 a kind of can the timer circuit of computation delay automatically, it is characterised in that described delayed data comprises delay value, time delay loading, timing mode are selected, exported model selection.
3. according to claim 1 a kind of can the timer circuit of computation delay automatically, it is characterised in that described timing control circuit is multiple.
4. according to claim 1 a kind of can the timer circuit of computation delay automatically, it is characterised in that described timing control circuit comprises time delay latch cicuit, timing matching circuit, timing mode circuit, exports mode selection circuit; Described time delay latch cicuit is connected with timing matching circuit, timing mode circuit, and timing matching circuit is connected with timing mode circuit, output mode selection circuit.
5. according to claim 1 a kind of can the timer circuit of computation delay automatically, it is characterised in that described timing control circuit
Time delay latch cicuit is used for the timing value inputted and delay value being sued for peace and latches, and exports time delay latched value to timing matching circuit, receives the latch signal of timing mode circuit;
Timing matching circuit, for timing value and time delay latched value being compared, exports comparative result to exporting mode selection circuit, receives the enable signal of timing mode circuit;
Timing mode circuit is for controlling single timing mode or cycle timing mode, and input time delay loads, timing mode selects information, also receives the comparative result of timing matching circuit, output latch signal and relatively enable signal;
Export mode selection circuit for controlling to produce the output of pulse or level mode, receive the Output rusults exporting mode selecting information and timing matching circuit, produce comparison match signal and export.
6. one kind can the timer method of computation delay automatically, it is characterised in that comprise the following steps:
A., when enable signal is effective, timer circuit work also exports counting value continuously;
B. under time delay load signal effect, the latch signal of timing mode circuit evolving pulse, and produce more enable signal to timing matching circuit;
C. time delay latch cicuit receives the latch signal of timing mode circuit, and when it is effective, timing value and delay value is carried out addition summation operation and latch, and then exports delay latch signal to timing matching circuit;
D. timing matching circuit receives more enable signal, time delay latched value and timing value, when more enable signal is effective, time delay latched value and timing value is compared, and exports comparative result when the two is equal;
E., when timing mode is chosen as single timing mode, timing mode circuit, after receiving comparative result, is forbidden exporting more enable signal;
F. output mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing.
7. according to claim 6 a kind of can the timer method of computation delay automatically, it is characterised in that when timing mode is chosen as continuous timing mode, timing mode circuit, after receiving comparative result, continues to generate latch signal pulse; Output mode selection circuit is according to output model selection, and compared result signal carries out directly exporting or latching exporting, and obtains pulse signal or the output of level signal, completion timing; Then step c is returned.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410680243.4A CN105652703B (en) | 2014-11-24 | 2014-11-24 | It is a kind of can computation delay automatically timer circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410680243.4A CN105652703B (en) | 2014-11-24 | 2014-11-24 | It is a kind of can computation delay automatically timer circuit and method |
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| CN105652703A true CN105652703A (en) | 2016-06-08 |
| CN105652703B CN105652703B (en) | 2018-06-19 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106100616A (en) * | 2016-06-17 | 2016-11-09 | 中国兵器工业集团第二四研究所苏州研发中心 | A kind of time-delay method of microminiature electronic delay circuit |
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| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
| CN103425058A (en) * | 2012-05-15 | 2013-12-04 | 安凯(广州)微电子技术有限公司 | Timing method, central processing unit and electronic device |
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| CN2161943Y (en) * | 1993-09-06 | 1994-04-13 | 钟日升 | Multichannel timing controller for microcomputer |
| WO1996033384A1 (en) * | 1995-04-10 | 1996-10-24 | The Ensign-Bickford Company | Programmable electronic timer circuit |
| CN2218378Y (en) * | 1995-06-28 | 1996-01-24 | 吴小平 | Multichannel and multi-character one-chip computer timer |
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| CN106100616A (en) * | 2016-06-17 | 2016-11-09 | 中国兵器工业集团第二四研究所苏州研发中心 | A kind of time-delay method of microminiature electronic delay circuit |
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| CN105652703B (en) | 2018-06-19 |
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