CN105652703B - It is a kind of can computation delay automatically timer circuit and method - Google Patents
It is a kind of can computation delay automatically timer circuit and method Download PDFInfo
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- CN105652703B CN105652703B CN201410680243.4A CN201410680243A CN105652703B CN 105652703 B CN105652703 B CN 105652703B CN 201410680243 A CN201410680243 A CN 201410680243A CN 105652703 B CN105652703 B CN 105652703B
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Abstract
The present invention relates to it is a kind of can computation delay automatically timer circuit, including timer and timing control circuit connected to it；The timer inputs enable signal, sends count value to timing control circuit for generating count value；Timing control circuit is used to carry out latch comparison according to the delayed data of input, exports comparison result.Its method is that the timer of automatic computation delay is completed by hardware computation delay latched value, traditional timer, timing mode control etc..Circuit of the present invention includes the structures such as delay latch cicuit, timing mode circuit, can directly carry out delay value calculating, avoids the shortcomings that traditional design needs processor to participate in calculating, reduces processor resource expense, also realizes that agreement provides a convenient for devices at full hardware.
Description
Technical field
The present invention relates to it is a kind of can computation delay automatically timer circuit and method, it is specifically a kind of towards industry
The hardware realization of wireless network standards, for system on chip grade chip can be with the timer circuit and method of computation delay.
Background technology
WIA-PA(Wireless Networks for Industrial Automation Process Automation
Towards the industry wireless network standard technique of industrial process automation) standard be Chinese industrial Wireless Consortion be directed to process automation
The WIA substandards that field is formulated are for technical process measurement, the nothing of monitoring and control based on IEEE 802.15.4 standards
Line network system (hereinafter referred to as WIA agreements).Needed in WIA agreements comprising a large amount of timing requirements, such as timing open receiver,
Receive the timing of time-out time-out, transmitter, channel switching timing etc. are opened in timing.
It is general at present that there are two types of this large amount of timing requirements of method solution：One kind is using multiple timers, Mei Geding
When device solve a kind of timing problems, this method is needed by largely being realized in timer, logical resource, power supply to system
Consumption all brings negative effect；Another method is using single timer, when carrying out delay timing operation, needs to locate
It manages device and reads current timing value, then delay value with timing value is added, is written back timing fiducial value, this results in processor again
The waste of resource.
Invention content
For above-mentioned technical deficiency, it is an object of the invention to provide a kind of industry wireless networks towards industrial process automation
Standard technique protocol realization, for system on chip grade chip can computation delay automatically timer circuit.The circuit is to passing
Circuit of uniting includes two improvement：First is the increase in delay computation circuitry；Second is to support multi-way shared pattern, can be at one
The function of multichannel timing simultaneously is realized under timer.
The present invention solves its technical problem and uses following technical scheme：It is a kind of can automatically computation delay timer electricity
Road, including timer and timing control circuit connected to it；
The timer inputs enable signal, sends count value to timing control circuit for generating count value；
Timing control circuit is used to carry out latch comparison according to the delayed data of input, exports comparison result.
The delayed data includes delay value, delay loading, timing mode selection, output mode selection.
The timing control circuit is multiple.
The timing control circuit includes delay latch cicuit, timing match circuit, timing mode circuit, output mode choosing
Select circuit；The delay latch cicuit is connect with timing match circuit, timing mode circuit, timing match circuit and timing mode
Circuit, the connection of output mode selection circuit.
The timing control circuit
Delay latch cicuit is for being summed and being latched to the timing value and delay value of input, and output delay latched value is extremely
Timing match circuit receives the latch signal of timing mode circuit；
Timing match circuit is used to be compared timing value and delay latched value, and output comparison result to output mode selects
Circuit is selected, receives the enable signal of timing mode circuit；
Timing mode circuit is for controlling single timing mode or period timing mode, and input time delay loads, timing mode
Information is selected, also receives the comparison result of timing match circuit, export latch signal and compares enable signal；
Output mode selection circuit generates pulse or the output of level mode for controlling, and receives output mode selection information
With the output result of timing match circuit, generate comparison match signal and export.
It is a kind of can computation delay automatically timer approach, include the following steps:
A. when enable signal is effective, timer circuit work simultaneously continuously exports count value；
B. in the case where delay loads signal function, the latch signal of timing mode circuit evolving pulse, and generate relatively more enabled
Signal is to timing match circuit；
C. delay latch cicuit receives the latch signal of timing mode circuit, and when its is effective to timing value and delay value
It carries out addition summation operation and is latched, then export delay latch signal to timing match circuit；
D. enable signal, delay latched value and timing value are compared in the reception of timing match circuit, effective in relatively enable signal
When, delay latched value and timing value are compared, comparison result is exported when the two is equal；
E. when timing mode selected as single timing mode, timing mode circuit is forbidden defeated after comparison result is received
Go out to compare enable signal；
F. mode selection circuit is selected according to output mode, and compared result signal carries out directly exporting or latching output,
Obtain pulse signal or level signal output, completion timing.
When the continuous timing mode of timing mode selected as, timing mode circuit continues to generate after comparison result is received
Latch signal pulse；Output mode selection circuit is selected according to output mode, and compared result signal directly export or lock
Output is deposited, obtains pulse signal or level signal output, completion timing；It is then back to step c.
The invention has the advantages that and advantage：
1. circuit of the present invention is carried towards the hardware realization of industrial wireless network protocol standard, system on chip grade chip field
For it is a kind of can be with the timer circuit of computation delay.
2. circuit of the present invention uses single timer, the structure of timing control circuit multiplexing solves traditional using multiple
The shortcomings that timer, saves logical resource.
3. circuit of the present invention includes the structures such as delay latch cicuit, timing mode circuit, delay value calculating can be directly carried out,
The shortcomings that traditional design needs processor to participate in calculating is avoided, reduces processor resource expense, also realizes and assists for devices at full hardware
View provides a convenient.
Description of the drawings
Fig. 1 is the structure diagram of the present invention；
Fig. 2 is the structure diagram of timing control circuit；
Specific embodiment
With reference to embodiment, the present invention is described in further detail.
It is a kind of can computation delay automatically timer circuit, including timer circuit and timing control circuit two parts group
Into.Wherein timer circuit only needs one, and timing control circuit can include multiple.
It is a kind of can the input/output port of the timer circuit of computation delay automatically include：External input port includes fixed
When device enable, delay value, delay loading, timing mode selection, output mode selection, output port include comparison match.Wherein
There was only 1 in timer enable port；Delay value, delay loading, timing mode selection, output mode selection and comparison match port
One group is formed, when comprising multiple timing control circuits, may include multigroup delay value, delay loading, timing mode selection, output
Model selection and comparison match port.
Timer circuit is under the control of enable signal, provides count value output.The count value can stablize, be incremented by,
Meet timed length premise periodical timing.The count value can provide time reference for subsequent conditioning circuit, for generating timing ratio
Compared with interruption.Can be automatically in the timer circuit of computation delay in a kind of described in patent of the present invention, all timing controlleds electricity
The timing value port on road is accessed by the count value port of timer circuit, i.e., timer circuit is unique.
The function of timing control circuit includes timing mode control, delay latch, timing match, output mode control etc..
The timing mode of timing control circuit supports periodically timing and single timing both of which.The delay of timing control circuit is latched
Refer to that the clocking value under the action of latch signal to current timer circuit and externally input delay value carry out addition and ask
With, and will ask and result is added to latch in a register.The timing match of timing control circuit refers to the value that delay is latched and timing
The clocking value of device circuit is compared, and generates comparison match signal.The output mode control of timing control circuit supports that level is defeated
Go out pattern and edge output mode both of which.Described in patent of the present invention it is a kind of can automatically computation delay timer electricity
Lu Zhong, timing control circuit are not unique, can include multiple timing control circuits.Each timing control circuit can be completed
The function of timer all the way can be realized the function of multi-path timer by multiple timing control circuits.
Single timing mode refers to that timer only completes a fixed cycle operator, generates the comparison match signal of single；Period
Timing mode refers to continuously generate fixed cycle operator, generates periodic comparison match signal.
The principles illustrated of circuit of the present invention is as follows：
The timer circuit is cumulative type timer, includes enabled control.When enabled control is effective, can continuously count
Number, when overflowing, counts again since 0.
The effect of timing control circuit is to realize the timer of one group of automatic computation delay.In practical applications, according to not
Same functional requirement, can be by multiple timing control circuits.
The timing control circuit is made of four partial circuits, and be respectively delayed latch cicuit, timing match circuit, timing
Mode circuit and output mode selection circuit.
The effect of delay latch cicuit in the timing control circuit is to calculate next delay fiducial value and locked
It deposits.
The effect of timing match circuit in timing control circuit is the more current timing under the control of enable signal
Value generates indication signal with latching time delayed signal when the two is equal.
There are two act on for timing mode circuit in timing control circuit：First, realize timing mode selection control, it can be real
Existing single delay timing and periodical delay timing；The other is delay Loading Control is realized, including to two kinds of timing modes
It supports.
The effect of output mode selection circuit in timing control circuit is as needed, can generate pulse output and compare
Matched signal or level output comparison match signal both of which.
The timer control method of the present invention comprises the steps of：
A. when enable signal is effective, timer circuit work simultaneously continuously exports count value；
B. in the case where delay loads signal function, the latch signal of timing mode circuit evolving pulse, and generate relatively more enabled
Signal is to timing match circuit；
C. delay latch cicuit receives the latch signal of timing mode circuit, and when its is effective to timing value and delay value
It carries out addition summation operation and is latched, then export delay latch signal to timing match circuit；
D. enable signal, delay latched value and timing value are compared in the reception of timing match circuit, effective in relatively enable signal
When, delay latched value and timing value are compared, comparison result is exported when the two is equal；
E. when timing mode selected as single timing mode, timing mode circuit is forbidden defeated after comparison result is received
Go out to compare enable signal；
F. mode selection circuit is selected according to output mode, and compared result signal carries out directly exporting or latching output,
Obtain pulse signal or level signal output, completion timing.
When the continuous timing mode of timing mode selected as, timing mode circuit continues to generate after comparison result is received
Latch signal pulse；Output mode selection circuit is selected according to output mode, and compared result signal directly export or lock
Output is deposited, obtains pulse signal or level signal output, completion timing；It is then back to step c.
The present embodiment is write using Verilog code, can use Synopsys DesignCompiler synthesis tools into
Row is comprehensive to be realized.
The present embodiment structure diagram and connection relation are as shown in Figure 1.In the present embodiment, 3 groups of automatic computation delays are realized
Timer.The present embodiment only embodies a kind of realization method of patent of the present invention, and according to actual needs, it is fixed to increase or decrease
When control circuit number.
The present embodiment realize can the input/output port of the timer circuit of computation delay automatically include：External input
Port is enabled including timer, delay value 1, delay loading 1, timing mode selection 1, output mode selection 1, delay value 2, is delayed
Loading 2, timing mode selection 2, output mode selection 2, delay value 3, delay loading 3, timing mode selection 3, output mode choosing
Select 3；External output port includes comparison match 1, comparison match 2, comparison match 3.
The present embodiment realize can computation delay automatically timer circuit, function module including timer module,
Timing control module 1, timing control module 2, timing control module 3.
The connection relation of the present embodiment is as follows：The Enable Pin of externally input timer enable signal access timer module
Mouthful, the count value port output counter value signal of timer module；Timer module output counter value signal access timing controlled
The timing value port of circuit 1, externally input delay value 1 accesses the delay value port of timing control circuit 1, externally input to prolong
When 1 access timing control circuit 1 of loading delay load port, 1 access timing controlled electricity of externally input timing mode selection
The timing mode selection port on road 1, the output mode selection of externally input 1 access timing control circuit 1 of output mode selection
Port, comparison match port output 1 signal of comparison match of timing control circuit 1；Timer module output counter value signal connects
Enter the timing value port of timing control circuit 2, externally input delay value 2 accesses the delay value port of timing control circuit 2, outside
The delay load port of the 2 access timing control circuit 2 of delay loading of portion's input, externally input 2 access of timing mode selection
The timing mode selection port of timing control circuit 2, externally input output mode selection 2 access the defeated of timing control circuit 1
Go out pattern selection port, comparison match port output 2 signal of comparison match of timing control circuit 2；Timer module output meter
Numerical signal accesses the timing value port of timing control circuit 3, and externally input delay value 3 accesses prolonging for timing control circuit 3
Duration port, the delay load port of externally input 3 access timing control circuit 3 of delay loading, externally input timing mould
The timing mode selection port of 3 access timing control circuit 3 of formula selection, externally input 3 access timing control of output mode selection
The output mode selection port of circuit 3 processed, comparison match port output 3 signal of comparison match of timing control circuit 3.
Timing control module 1, timing control module 2, timing control module 3 in the present embodiment are 3 identical circuits,
With identical input/output port and circuit structure, i.e. timing control circuit described in invention content.
The input port of timing control circuit in the present embodiment includes timing value, delay value, delay loading, timing mode
Selection, output mode selection；Output port includes comparison match result.
As shown in Fig. 2, the function module of the timing control circuit in the present embodiment includes delay latch cicuit, timing mode
Circuit, output mode selection circuit, timing match circuit.
The timer circuit timer circuit that can be automatically in the timer circuit of computation delay that the present embodiment is realized is adopted
With general purpose timer circuit design, input port is enabled, and output port is count value.
The connection relation of timing control circuit is as follows：The A ends of externally input timing value signal access delay latch cicuit
Mouthful, the D ports of externally input delay value signal access delay latch cicuit, the loading signal access of timing mode circuit output
Time delayed signal is latched in the LD ports of delay computation circuitry, the C-terminal mouth output for the latch cicuit that is delayed；Be delayed the lock that latch cicuit exports
Deposit the A ports of time delayed signal access timing match circuit, the B ends of externally input timing value signal access timing match circuit
Mouthful, the EN ports of the timing match enable signal access timing match circuit of timing mode circuit evolving, the C of timing match circuit
Port exports timing match signal；The A ports of the timing match signal access timing mode circuit of timing match circuit output, outside
The B ports of the delay loading signal access timing mode circuit of portion's input, externally input timing mode selection signal access are fixed
When mode circuit M port, timing mode circuit C-terminal mouth output loading signal, timing mode circuit D ports output timing
Match enable signal；The M port of externally input output mode selection signal input and output mode selection circuit, output mode choosing
Select the C-terminal mouth output comparison match signal of circuit.
The behavior description of delay latch cicuit is when latch signal LD is effective, and the value of port A is mutually locked with the value of port D
It deposits in a register, and is exported in the C of port.
The behavior description of timing match circuit is value of the value with port B for comparing port A, when the value of both is equal,
Port C exports useful signal, otherwise exports invalid signals.
The behavior description of timing mode circuit is after delay loading signal is effective, and setting delay timing mark is effective, together
When C-terminal mouth export useful signal.Under single delay timing pattern, in the case that delay timing mark is effective, when A ports are defeated
When entering useful signal, cancel delay timing mark；Under periodical delay timing pattern, even if A ports input useful signal, prolong
When timing index state remain unchanged.Under periodical delay timing pattern, when A ports input useful signal, C-terminal mouth is defeated
Go out useful signal.
The behavior description of output mode selection circuit be when the selected as level way of output, when A ports are effective, C-terminal
Mouth carries out it latch output, keeps level state；When the selected as pulse way of output, C-terminal mouth directly exports useful signal；
The state of C-terminal mouth can be cancelled by the selection of output mode.The output of C-terminal mouth is the comparison match output of timing control circuit
Signal.
Claims (6)
1. it is a kind of can computation delay automatically timer circuit, it is characterised in that:Including timer and connected to it fixed
When control circuit；
The timer inputs enable signal, sends count value to timing control circuit for generating count value；
Timing control circuit is used to carry out latch comparison according to the delayed data of input, exports comparison result；
The timing control circuit
Delay latch cicuit is for being summed and being latched to the timing value and delay value of input, output delay latched value to timing
Match circuit receives the latch signal of timing mode circuit；
Timing match circuit is used to be compared timing value and delay latched value, and output comparison result to output mode selects electricity
Road receives the enable signal of timing mode circuit；
For controlling single timing mode or period timing mode, input time delay loading, timing mode select timing mode circuit
Information also receives the comparison result of timing match circuit, exports latch signal and compares enable signal；
Output mode selection circuit generates pulse or the output of level mode for control, receives output mode selection information and determines
When match circuit output result, generate comparison match signal simultaneously export.
2. it is according to claim 1 it is a kind of can computation delay automatically timer circuit, it is characterised in that the delay
Information includes delay value, delay loading, timing mode selection, output mode selection.
3. it is according to claim 1 it is a kind of can computation delay automatically timer circuit, it is characterised in that the timing
Control circuit is multiple.
4. it is according to claim 1 it is a kind of can computation delay automatically timer circuit, it is characterised in that the timing
Control circuit includes delay latch cicuit, timing match circuit, timing mode circuit, output mode selection circuit；The delay
Latch cicuit is connect with timing match circuit, timing mode circuit, and timing match circuit is selected with timing mode circuit, output mode
Select circuit connection.
5. it is a kind of can computation delay automatically timer approach, it is characterised in that include the following steps:
A. when enable signal is effective, timer circuit work simultaneously continuously exports count value；
B. in the case where delay loads signal function, the latch signal of timing mode circuit evolving pulse, and generate and compare enable signal
To timing match circuit；
C. delay latch cicuit receives the latch signal of timing mode circuit, and timing value and delay value are carried out when its is effective
Addition summation operation is simultaneously latched, and then exports delay latch signal to timing match circuit；
D. enable signal, delay latched value and timing value are compared in the reception of timing match circuit, right when relatively enable signal is effective
Delay latched value and timing value are compared, and comparison result is exported when the two is equal；
E. when model selection is single timing mode, timing mode circuit forbids output relatively more enabled after comparison result is received
Signal；
F. mode selection circuit is selected according to output mode, and compared result signal carries out directly exporting or latching output, obtains
Pulse signal or level signal output, completion timing.
6. it is according to claim 5 it is a kind of can computation delay automatically timer approach, it is characterised in that when timing mould
During the continuous timing mode of formula selected as, timing mode circuit continues to generate latch signal pulse after comparison result is received；Output
Mode selection circuit is selected according to output mode, and compared result signal carries out directly exporting or latching output, obtains pulse letter
Number or level signal output, completion timing；It is then back to step c.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410680243.4A CN105652703B (en) | 2014-11-24 | 2014-11-24 | It is a kind of can computation delay automatically timer circuit and method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410680243.4A CN105652703B (en) | 2014-11-24 | 2014-11-24 | It is a kind of can computation delay automatically timer circuit and method |
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| Publication Number | Publication Date |
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| CN105652703A CN105652703A (en) | 2016-06-08 |
| CN105652703B true CN105652703B (en) | 2018-06-19 |
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| CN201410680243.4A Active CN105652703B (en) | 2014-11-24 | 2014-11-24 | It is a kind of can computation delay automatically timer circuit and method |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106100616A (en) * | 2016-06-17 | 2016-11-09 | 中国兵器工业集团第二四研究所苏州研发中心 | A kind of time-delay method of microminiature electronic delay circuit |
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|---|---|---|---|---|
| CN2161943Y (en) * | 1993-09-06 | 1994-04-13 | 钟日升 | Multichannel timing controller for microcomputer |
| CN2218378Y (en) * | 1995-06-28 | 1996-01-24 | 吴小平 | Multichannel and multi-character one-chip computer timer |
| CN1267364A (en) * | 1997-06-19 | 2000-09-20 | 恩赛-比克福德公司 | Electronic circuitry for timing and delay circuit |
| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
| CN103425058A (en) * | 2012-05-15 | 2013-12-04 | 安凯(广州)微电子技术有限公司 | Timing method, central processing unit and electronic device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5621184A (en) * | 1995-04-10 | 1997-04-15 | The Ensign-Bickford Company | Programmable electronic timer circuit |
-
2014
- 2014-11-24 CN CN201410680243.4A patent/CN105652703B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2161943Y (en) * | 1993-09-06 | 1994-04-13 | 钟日升 | Multichannel timing controller for microcomputer |
| CN2218378Y (en) * | 1995-06-28 | 1996-01-24 | 吴小平 | Multichannel and multi-character one-chip computer timer |
| CN1267364A (en) * | 1997-06-19 | 2000-09-20 | 恩赛-比克福德公司 | Electronic circuitry for timing and delay circuit |
| CN103425058A (en) * | 2012-05-15 | 2013-12-04 | 安凯(广州)微电子技术有限公司 | Timing method, central processing unit and electronic device |
| CN102931994A (en) * | 2012-09-26 | 2013-02-13 | 成都嘉纳海威科技有限责任公司 | High-speed signal sampling and synchronizing framework and method applied to signal processing chip |
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