CN105518847A - 改变多核的栅极长度的系统和方法 - Google Patents
改变多核的栅极长度的系统和方法 Download PDFInfo
- Publication number
- CN105518847A CN105518847A CN201480048426.2A CN201480048426A CN105518847A CN 105518847 A CN105518847 A CN 105518847A CN 201480048426 A CN201480048426 A CN 201480048426A CN 105518847 A CN105518847 A CN 105518847A
- Authority
- CN
- China
- Prior art keywords
- core
- length
- transistor
- polysilicon gate
- semiconductor die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0135—Manufacturing their gate conductors
- H10D84/0142—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/10—Integrated device layouts
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Evolutionary Computation (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/017,635 | 2013-09-04 | ||
| US14/017,635 US9076775B2 (en) | 2013-09-04 | 2013-09-04 | System and method of varying gate lengths of multiple cores |
| PCT/US2014/048944 WO2015034602A1 (en) | 2013-09-04 | 2014-07-30 | System and method of varying gate lengths of multiple cores |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105518847A true CN105518847A (zh) | 2016-04-20 |
Family
ID=51454951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480048426.2A Pending CN105518847A (zh) | 2013-09-04 | 2014-07-30 | 改变多核的栅极长度的系统和方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9076775B2 (enExample) |
| EP (1) | EP3042393A1 (enExample) |
| JP (1) | JP6360175B2 (enExample) |
| CN (1) | CN105518847A (enExample) |
| WO (1) | WO2015034602A1 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9076775B2 (en) | 2013-09-04 | 2015-07-07 | Qualcomm Incorporated | System and method of varying gate lengths of multiple cores |
| JP6513450B2 (ja) * | 2015-03-26 | 2019-05-15 | 三重富士通セミコンダクター株式会社 | 半導体装置 |
| CN108052838B (zh) * | 2017-11-23 | 2021-12-07 | 北京智芯微电子科技有限公司 | 芯片加密设计的泄漏定位系统及方法 |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7200824B1 (en) * | 2004-11-16 | 2007-04-03 | Altera Corporation | Performance/power mapping of a die |
| CN1965391A (zh) * | 2004-05-14 | 2007-05-16 | 松下电器产业株式会社 | 制造半导体器件的方法和设备 |
| CN101188212A (zh) * | 2006-11-15 | 2008-05-28 | 株式会社瑞萨科技 | 半导体装置的制造方法 |
| US8302064B1 (en) * | 2009-03-10 | 2012-10-30 | Xilinx, Inc. | Method of product performance improvement by selective feature sizing of semiconductor devices |
| US20130086395A1 (en) * | 2011-09-30 | 2013-04-04 | Qualcomm Incorporated | Multi-Core Microprocessor Reliability Optimization |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5600578A (en) | 1993-08-02 | 1997-02-04 | Advanced Micro Devices, Inc. | Test method for predicting hot-carrier induced leakage over time in short-channel IGFETs and products designed in accordance with test results |
| JP3152642B2 (ja) | 1998-01-29 | 2001-04-03 | 三洋電機株式会社 | 半導体集積回路装置 |
| JP2003282823A (ja) | 2002-03-26 | 2003-10-03 | Toshiba Corp | 半導体集積回路 |
| US6912705B2 (en) * | 2002-06-27 | 2005-06-28 | Sun Microsystems, Inc. | Method and apparatus for performing operation on physical design data |
| JP2007081249A (ja) * | 2005-09-15 | 2007-03-29 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP5561922B2 (ja) * | 2008-05-20 | 2014-07-30 | 三菱電機株式会社 | パワー半導体装置 |
| US8447547B2 (en) * | 2009-06-17 | 2013-05-21 | Qualcomm Incorporated | Static noise margin estimation |
| US8924975B2 (en) * | 2009-07-23 | 2014-12-30 | Empire Technology Development Llc | Core selection for applications running on multiprocessor systems based on core and application characteristics |
| US8390331B2 (en) | 2009-12-29 | 2013-03-05 | Nxp B.V. | Flexible CMOS library architecture for leakage power and variability reduction |
| JP2011253931A (ja) * | 2010-06-02 | 2011-12-15 | Panasonic Corp | 半導体装置及びその製造方法 |
| US20120042292A1 (en) | 2010-08-10 | 2012-02-16 | Stmicroelectronics S.A. | Method of synthesis of an electronic circuit |
| JP5592210B2 (ja) * | 2010-09-09 | 2014-09-17 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US8610176B2 (en) | 2011-01-11 | 2013-12-17 | Qualcomm Incorporated | Standard cell architecture using double poly patterning for multi VT devices |
| JP2013030602A (ja) | 2011-07-28 | 2013-02-07 | Panasonic Corp | 半導体集積回路装置 |
| US9076775B2 (en) | 2013-09-04 | 2015-07-07 | Qualcomm Incorporated | System and method of varying gate lengths of multiple cores |
-
2013
- 2013-09-04 US US14/017,635 patent/US9076775B2/en not_active Expired - Fee Related
-
2014
- 2014-07-30 JP JP2016540885A patent/JP6360175B2/ja not_active Expired - Fee Related
- 2014-07-30 CN CN201480048426.2A patent/CN105518847A/zh active Pending
- 2014-07-30 WO PCT/US2014/048944 patent/WO2015034602A1/en not_active Ceased
- 2014-07-30 EP EP14758437.9A patent/EP3042393A1/en not_active Withdrawn
-
2015
- 2015-07-06 US US14/792,363 patent/US9461040B2/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1965391A (zh) * | 2004-05-14 | 2007-05-16 | 松下电器产业株式会社 | 制造半导体器件的方法和设备 |
| US7200824B1 (en) * | 2004-11-16 | 2007-04-03 | Altera Corporation | Performance/power mapping of a die |
| CN101188212A (zh) * | 2006-11-15 | 2008-05-28 | 株式会社瑞萨科技 | 半导体装置的制造方法 |
| US8302064B1 (en) * | 2009-03-10 | 2012-10-30 | Xilinx, Inc. | Method of product performance improvement by selective feature sizing of semiconductor devices |
| US20130086395A1 (en) * | 2011-09-30 | 2013-04-04 | Qualcomm Incorporated | Multi-Core Microprocessor Reliability Optimization |
Also Published As
| Publication number | Publication date |
|---|---|
| US20150061037A1 (en) | 2015-03-05 |
| WO2015034602A1 (en) | 2015-03-12 |
| EP3042393A1 (en) | 2016-07-13 |
| JP2016534574A (ja) | 2016-11-04 |
| US20150311198A1 (en) | 2015-10-29 |
| JP6360175B2 (ja) | 2018-07-18 |
| US9461040B2 (en) | 2016-10-04 |
| US9076775B2 (en) | 2015-07-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160420 |
|
| WD01 | Invention patent application deemed withdrawn after publication |