CN105489588B - 传感器封装结构及其制备方法 - Google Patents

传感器封装结构及其制备方法 Download PDF

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CN105489588B
CN105489588B CN201510885822.7A CN201510885822A CN105489588B CN 105489588 B CN105489588 B CN 105489588B CN 201510885822 A CN201510885822 A CN 201510885822A CN 105489588 B CN105489588 B CN 105489588B
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chip
substrate
circuit
protection board
sensor
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CN105489588A (zh
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李扬渊
丁绍波
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Suzhou Mairui Microelectronic Co Ltd
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Suzhou Mairui Microelectronic Co Ltd
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Priority to CN201510885822.7A priority Critical patent/CN105489588B/zh
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Priority to PCT/CN2016/108039 priority patent/WO2017092677A1/zh
Priority to EP16869987.4A priority patent/EP3385984A4/en
Priority to US15/781,069 priority patent/US10804171B2/en
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Abstract

本发明揭示了一种传感器封装结构及其制备方法，传感器封装结构包括保护板、电路结构和填充结构。电路结构的正面与保护板的第一表面连接，以保护板的第二表面为传感功能表面；填充结构位于电路结构的外周侧，与保护板的第一表面连接。电路结构包括芯片和基板，芯片和基板背对背连接，芯片的正面位于电路结构的正面，并设置有功能电路，基板的正面位于电路结构的背面，并设置有焊盘，且焊盘与芯片正面的功能电路电性连接。本发明的传感器封装结构，使用保护板作为功能电路的保护层，能对传感器的功能电路起到有效的保护作用，同时，在制备方法中首先将保护板与电路结构连接，避免公差累积，提高了保护层的制造精度。

Description

传感器封装结构及其制备方法
技术领域
本发明涉及传感器封装结构的制造和封装技术领域。
背景技术
传感器的功能电路(传感面)可能面临苛刻的使用环境，需要优秀的保护层来实现结构保护、化学保护和静电保护。
现有技术中常见的封装结构为塑封结构，包括基板、芯片和填充部，芯片的功能电路位于芯片远离基板的一侧，功能电路通过打线和基板内部线路与焊盘电连接，填充部将整个芯片包裹在其中，芯片的功能电路依靠其表面的填充部作为保护层为其提供保护，由于保护层石头硬度不高的塑料所制成，将该封装技术用于传感器芯片封装，并不能有效保护传感器芯片的功能电路。
在传感器封装结构的制造技术领域，公差取决于组装顺序，越往后越容易因公差累积造成精度不高。在现有封装结构的制造过程中，是将芯片远离功能电路的一侧表面与基板贴合，然后将芯片和基板放入注塑机中注塑填充部，由于充当保护层的填充部最后制造，所以基板和芯片存在的公差都会累积在保护层上，造成保护层制造精度不高。
目前并没有一种应用于传感器封装的结构及其制备方法，既能有效保护传感器的功能电路又能保持较高的保护层制造精度。
发明内容
本发明的目的在于提供一种高制造精度，能够更好地保护传感器芯片的功能电路面的封装结构及其制备方法。
为实现上述发明目的，本发明采用如下技术方案：
一种传感器封装结构，所述传感器封装结构包括保护板、电路结构和填充结构，所述电路结构的正面与所述保护板的第一表面连接，以所述保护板的第二表面为传感功能表面；所述填充结构位于电路结构的外周侧，与所述保护板的第一表面连接；
所述电路结构包括芯片和基板，所述芯片与所述基板背对背连接，
所述芯片的正面位于所述电路结构的正面，且所述芯片的正面设置有功能电路；
所述基板的正面位于所述电路结构的背面，且所述基板的正面设置有焊盘。
进一步地，所述填充结构与所述保护板构成一侧开口的收容空间，所述电路结构位于所述收容空间内，所述电路结构的背面暴露于收容空间开口处。
作为本发明进一步改进的技术方案，所述芯片正面的功能电路与所述基板背面的焊盘电性连接。
作为本发明进一步改进的技术方案，所述基板的尺寸和形状与所述芯片的尺寸和形状相符。
作为本发明进一步改进的技术方案，所述基板的尺寸和形状与所述芯片的尺寸和形状不相符合。
一种传感器封装结构的制备方法，依次包括以下步骤：
S1、将芯片与基板背对背结合，并将设置于芯片正面的功能电路与设置于基板正面的焊盘电性连接，制得电路结构；
S2、将一个或多个所述电路结构的正面结合到保护板的第一表面；
S3、沿所述电路结构的外周侧注塑形成填充结构，填充结构同时结合到保护板的第一表面；
S4、以电路结构为单位分割所述填充结构和所述保护板。
作为本发明进一步改进的技术方案，步骤S1中，所述基板的背面与所述芯片的背面用粘贴方式结合。
作为本发明进一步改进的技术方案，步骤S1中，所述基板采用加成法直接生长于所述芯片的背面。
相对于现有技术，本发明的技术效果在于：
本发明的传感器封装结构，使用保护板作为功能电路的保护层，能对传感器的功能电路起到有效的保护作用，同时，在制备方法中将保护板与电路结构连接的工序提前，可以避免公差累积，保持较高的制造精度。
附图说明
图1是本发明实施例一所提供的传感器封装结构的剖视结构示意图；
图2是本发明实施例二所提供的传感器封装结构的剖视结构示意图；
图3是本发明实施例三所提供的传感器封装结构的剖视结构示意图；
图4是本发明中功能电路与焊盘电性连接方式的示意图一；
图5是本发明中功能电路与焊盘电性连接方式的示意图二；
图6是本发明所提供的传感器封装结构制备方法的流程示意图。
图7是本发明所提供的传感器封装结构制备方法的示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
本发明中芯片的背面定义为芯片和基板结合后，与基板相互接触的一侧芯片表面，芯片的正面定义为芯片和基板结合后，与芯片背面相对的另一侧芯片表面；本发明中基板的背面定义为芯片和基板结合后，与芯片相互接触的一侧基板表面，基板的正面定义为芯片和基板结合后，与基板背面相对的另一侧基板表面。
各实施例中相同或相似的结构采用了相同的标号。
实施例一
请参见图1，本发明提供了一种传感器封装结构，所述传感器封装结构包括保护板1、电路结构2和填充结构3，电路结构2的正面与所述保护板1的第一表面连接，以所述保护板1的第二表面(保护板与第一表面平行相对的另一侧表面)为传感功能表面，填充结构3位于电路结构2的外周侧，与所述保护板1的第一表面连接，且填充结构3与保护板1构成一侧开口的收容空间，电路结构2位于所述收容空间内，电路结构2的背面暴露于收容空间开口处。
电路结构2包括芯片23和基板24且芯片23与所述基板24背对背连接，芯片23的正面位于所述电路结构的正面，并设置有功能电路11；基板24的正面位于所述电路结构2的背面，并设置有焊盘22，并且焊盘22与所述芯片23正面的功能电路11电性连接。
一般的，在现有技术中保护板1由硬质高亮材质所制成，例如玻璃、蓝宝石、水晶、陶瓷等，设置于芯片23正面的功能电路11利用保护板1作为保护层，凭借保护板1为功能电路提供可靠的保护。
本实施例中，基板24的截面宽度D1大于芯片23的截面宽度D2。
进一步地，基板24的背面与芯片23的背面可以直接贴合连接，基板24也可通过加成法直接生长于芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
请参见图6,本发明还提供了一种传感器封装结构的制备方法，依次包括以下步骤：
S1、将芯片与基板背对背结合，并将设置于芯片正面的功能电路与设置于基板正面的焊盘电性连接，制得电路结构；
S2、将一个或多个所述电路结构的正面结合到保护板的第一表面；
S3、沿电路结构的外周侧注塑形成填充结构，填充结构同时结合到保护板的第一表面；
S4、以电路结构为单位分割填充结构和保护板。
请参见图7，将多个电路结构2的正面贴合在保护板1的第一表面后，沿电路结构2的外周侧注塑形成填充结构3，填充结构3同时结合到保护板1的第一表面，最后以电路结构2为单位沿分割线13分割填充结构2和保护板1。此处电路结构2的芯片23和基板24已连接，且焊盘22与芯片正面的功能电路11已电性连接。
进一步地，具体到步骤S1中，基板24的背面与芯片23的背面通过直接贴合的方式相结合，同时，基板24的背面也可以通过加成法直接生长于芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
本发明的传感器封装结构，使用保护板作为功能电路的保护层，能对传感器的功能电路起到有效的保护作用，同时，在制备方法中将作为功能电路保护层的保护板与电路结构连接的工序提前，可以避免公差累积，保持较高的制造精度。
实施例二
请参见图2，本发明提供了一种传感器封装结构，所述传感器封装结构包括保护板1、电路结构2和填充结构3，电路结构2的正面与保护板1的第一表面连接，以保护板1的第二表面(保护板与第一表面平行相对的另一侧表面)为传感功能表面，填充结构3位于电路结构2的外周侧，与保护板1的第一表面连接，且填充结构3与保护板1构成一侧开口的收容空间，电路结构2位于所述收容空间内，电路结构2的背面暴露于收容空间开口处。
电路结构2包括芯片23和基板24且芯片23与所述基板24背对背连接，芯片23的正面位于电路结构2的正面，并设置有功能电路11；基板24的正面位于电路结构2的背面，并设置有焊盘22，并且焊盘22与芯片23的功能电路11电性连接。
一般的，在现有技术中保护板1由硬质高亮材质所制成，例如玻璃、蓝宝石、水晶、陶瓷等，设置于芯片23正面的功能电路11利用保护板1作为保护层，凭借保护板1为功能电路提供可靠的保护。
本实施例中，基板24的截面宽度D1等于芯片23的截面宽度D2。
基板24的背面与芯片23的背面可以直接贴合连接，也可通过加成法直接生长与芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
请参见图6,本发明还提供了一种传感器封装结构的制备方法，依次包括以下步骤：
S1、将芯片与基板背对背结合，并将设置于芯片正面的功能电路与设置于基板正面的焊盘电性连接，制得电路结构；
S2、将一个或多个所述电路结构的正面结合到保护板的第一表面；
S3、沿电路结构的外周侧注塑形成填充结构，填充结构同时结合到保护板的第一表面；
S4、以电路结构为单位分割填充结构和保护板。
请参见图7，将多个电路结构2的正面贴合在保护板1的第一表面后，沿电路结构2的外周侧注塑形成填充结构3，填充结构3同时结合到保护板1的第一表面，最后以电路结构2为单位，沿分割线13分割填充结构2和保护板1。此处电路结构2的芯片23和基板24已连接，且焊盘22与芯片正面的功能电路11已电性连接。
进一步地，具体到步骤S1中，基板24的背面与芯片23的背面通过直接贴合的方式相结合，同时，基板24的背面也可以通过加成法直接生长于芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
本发明的传感器封装结构，使用保护板作为功能电路的保护层，能对传感器的功能电路起到有效的保护作用，同时，在制备方法中将作为功能电路保护层的保护板与电路结构连接的工序提前，可以避免公差累积，保持较高的制造精度。
实施例三
请参见图3，本发明提供了一种传感器封装结构，传感器封装结构包括保护板1、电路结构2和填充结构3，电路结构2的正面与保护板1的第一表面连接，以保护板1的第二表面(保护板与第一表面平行相对的另一侧表面)为传感功能表面，填充结构3位于电路结构2的外周侧，与保护板1的第一表面连接，且填充结构3与保护板1构成一侧开口的收容空间，电路结构2位于收容空间内，电路结构2的背面暴露于收容空间开口处。
电路结构2包括芯片23和基板24且芯片23与基板24背对背连接，芯片23的正面位于电路结构的正面，并设置有功能电路11；基板24的正面位于电路结构2的背面，并设置有焊盘22，并且焊盘22与所述芯片23的功能电路11电性连接。
一般的，在现有技术中保护板1由硬质高亮材质所制成，例如玻璃、蓝宝石、水晶、陶瓷等，设置于芯片23正面的功能电路11利用保护板1作为保护层，凭借保护板1为功能电路提供可靠的保护。
本实施例中，基板24的截面宽度D1小于芯片23的截面宽度D2。
基板24的背面与芯片23的背面可以直接贴合连接，也可通过加成法直接生长与芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
请参见图6,本发明还提供了一种传感器封装结构的制备方法，依次包括以下步骤：
S1、将芯片与基板背对背结合，并将设置于芯片正面的功能电路与设置于基板正面的焊盘电性连接，制得电路结构；
S2、将一个或多个所述电路结构的正面结合到保护板的第一表面；
S3、沿电路结构的外周侧注塑形成填充结构，填充结构同时结合到保护板的第一表面；
S4、以电路结构为单位分割填充结构和保护板。
请参见图7，将多个电路结构2的正面贴合在保护板1的第一表面后，沿电路结构2的外周侧注塑形成填充结构3，填充结构3同时结合到保护板1的第一表面，最后以电路结构2为单位沿分割线13分割填充结构2和保护板1。此处电路结构2的芯片23和基板24已连接，且焊盘22与芯片正面的功能电路11已电性连接。
进一步地，具体到步骤S1中，基板24的背面与芯片23的背面通过直接贴合的方式相结合，同时，基板24的背面也可以通过加成法直接生长于芯片23的背面。
请参见图4，芯片23正面的功能电路11与设置于基板24正面的焊盘22可以通过引线结合方式(引线结合方式为现有技术)电性连接。
请参见图5，芯片23正面的功能电路11与设置于基板24正面的焊盘22也可以通过硅通孔方式(硅通孔方式为现有技术)电性连接。
此处应该注意的是，焊盘22与芯片23正面功能电路11的电性连接方式并不局限于上述列举的两种方式，例如BGA(焊球阵列封装)方式，或者各种方法的组合方式等可以实现焊盘22与芯片23正面功能电路11电性连接的现有技术都应包含在内。
本发明的传感器封装结构，使用保护板作为功能电路的保护层，能对传感器的功能电路起到有效的保护作用，同时，在制备方法中将作为功能电路保护层的保护板与电路结构连接的工序提前，可以避免公差累积，保持较高的制造精度。
对于本领域技术人员而言，显然本发明不限于上述示范性实施例的细节，而且在不背离本发明的精神或基本特征的情况下，能够以其他的具体形式实现本发明。因此，无论从哪一点来看，均应将实施例看作是示范性的，而且是非限制性的，本发明的范围由所附权利要求而不是上述说明限定，因此旨在将落在权利要求的等同要件的含义和范围内的所有变化囊括在本发明内。不应将权利要求中的任何附图标记视为限制所涉及的权利要求。
此外，应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施例中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。

Claims (8)

1.一种传感器封装结构，所述传感器封装结构包括保护板、电路结构和填充结构，其特征在于，所述电路结构的正面与所述保护板第一表面连接，以所述保护板第二表面为传感功能表面；
所述填充结构位于电路结构的外周侧，与所述保护板第一表面连接；
所述电路结构包括芯片和基板，所述芯片与所述基板背对背连接，
所述芯片的正面位于所述电路结构的正面，且所述芯片的正面设置有功能电路；
所述基板的正面位于所述电路结构的背面，且所述基板的正面设置有焊盘。
2.根据权利要求1所述的一种传感器封装结构，其特征在于，所述填充结构与所述保护板构成一侧开口的收容空间，所述电路结构位于所述收容空间内，所述电路结构背面暴露于收容空间开口处。
3.根据权利要求1所述的一种传感器封装结构，其特征在于，所述功能电路与所述焊盘电性连接。
4.根据权利要求1所述的一种传感器封装结构，其特征在于，所述基板的尺寸和形状与所述芯片的尺寸和形状相符。
5.根据权利要求1所述的一种传感器封装结构，其特征在于，所述基板的尺寸和形状与所述芯片的尺寸和形状不相符合。
6.一种传感器封装结构的制备方法，其特征在于，依次包括以下步骤：
S1、将芯片与基板背对背结合，并将设置于芯片正面的功能电路与设置于基板正面的焊盘电性连接，制得电路结构；
S2、将一个或多个所述电路结构的正面结合到保护板的第一表面；
S3、沿所述电路结构的外周侧注塑形成填充结构，填充结构同时结合到保护板的第一表面；
S4、以电路结构为单位分割所述填充结构和所述保护板。
7.根据权利要求6所述的一种传感器封装结构的制备方法，其特征在于，步骤S1中，所述基板的背面与所述芯片的背面用粘贴方式结合。
8.根据权利要求6所述的一种传感器封装结构的制备方法，其特征在于，步骤S1中，所述基板采用加成法直接生长于所述芯片的背面。
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162698A (zh) * 2006-10-12 2008-04-16 矽品精密工业股份有限公司 感测式封装件及其制法
CN103915393A (zh) * 2012-12-28 2014-07-09 群丰科技股份有限公司 光电封装体及其制造方法
CN104269393A (zh) * 2014-09-15 2015-01-07 江苏长电科技股份有限公司 一体金属框架静电释放圈用于指纹传感器结构及制造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003198897A (ja) 2001-12-27 2003-07-11 Seiko Epson Corp 光モジュール、回路基板及び電子機器
JP4970845B2 (ja) * 2006-05-16 2012-07-11 ルネサスエレクトロニクス株式会社 固体撮像装置
CN101567333A (zh) * 2008-04-25 2009-10-28 印像科技股份有限公司 图像感测装置及其封装方法
CN101683966B (zh) 2008-09-24 2012-05-02 中国科学院电子学研究所 微型电场传感器的封装结构与封装方法
JP5401292B2 (ja) * 2009-12-15 2014-01-29 ルネサスエレクトロニクス株式会社 半導体装置及び通信方法
TWI466278B (zh) * 2010-04-06 2014-12-21 Kingpak Tech Inc 晶圓級影像感測器構裝結構及其製造方法
CN104201116B (zh) * 2014-09-12 2018-04-20 苏州晶方半导体科技股份有限公司 指纹识别芯片封装方法和封装结构
CN104484660A (zh) * 2014-12-31 2015-04-01 华天科技（西安）有限公司 一种芯片集成的指纹识别传感器及其制作方法
CN105046239B (zh) 2015-08-19 2018-09-28 南昌欧菲生物识别技术有限公司 指纹识别装置及其终端设备
CN205177822U (zh) * 2015-12-04 2016-04-20 苏州迈瑞微电子有限公司 传感器封装结构
CN105489588B (zh) 2015-12-04 2019-05-31 苏州迈瑞微电子有限公司 传感器封装结构及其制备方法

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101162698A (zh) * 2006-10-12 2008-04-16 矽品精密工业股份有限公司 感测式封装件及其制法
CN103915393A (zh) * 2012-12-28 2014-07-09 群丰科技股份有限公司 光电封装体及其制造方法
CN104269393A (zh) * 2014-09-15 2015-01-07 江苏长电科技股份有限公司 一体金属框架静电释放圈用于指纹传感器结构及制造方法

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