CN105474405B - 具有垂直结构的氮化镓功率半导体器件 - Google Patents
具有垂直结构的氮化镓功率半导体器件 Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims abstract description 45
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Abstract
本发明公开了一种半导体器件，所述半导体器件包括衬底和第一有源层，所述衬底具有第一面和第二面，并且所述第一有源层设置在所述衬底的所述第一面上方。第二有源层设置在所述第一有源层上。所述第二有源层具有比所述第一有源层更高的带隙，使得在所述第一有源层与所述第二有源层之间出现二维电子气层。至少一个沟槽延伸穿过所述第一有源层和所述第二有源层及所述二维电子气层并进入所述衬底中。导电材料内衬于所述沟槽上。第一电极设置在所述第二有源层上并且第二电极设置在所述衬底的所述第二面上。
Description
背景技术
氮化镓(GaN)是替代高功率应用中的硅(Si)的潜在材料。GaN具有高击穿电压、优异输运性质、快速切换速度和良好热稳定性。氮化镓还比碳化硅更具成本效益。另一个优点是由氮化铝镓(AlGaN)和氮化镓形成的异质结构产生高迁移率电子的二维沟道，从而使GaN器件能够在相同反向偏压下实现比硅和碳化硅更低的导通电阻。
GaN可提供多种多样不同半导体器件的技术平台，所述半导体器件包括例如二极管和晶体管。二极管用于范围广泛的电子电路。在用于高电压切换应用的电路中使用的二极管理想地需要下列特性。当以反向偏压时(即，阴极处于比阳极更高的电压)，二极管应能够支持大电压，同时允许尽可能少的电流通过。必须支持的电压的量取决于应用；例如，许多高功率切换应用需要这样的二极管，所述二极管可支持至少600V的反向偏压而不会通过大量电流。最后，在二极管被反向偏压时二极管中存储的电荷的量应尽可能少以便在二极管两端的电压变化时减少电路中的瞬态电流，从而减少切换损耗。
图1示出了常规GaN基二极管的例子。二极管100包括衬底110、GaN缓冲层120、GaN外延(“epi”)层130和氮化铝镓势垒层135。第一金属层形成与氮化铝镓势垒层135接触的肖特基接触140并且第二金属层形成与氮化铝镓势垒层135接触的欧姆接触150。肖特基接触140充当器件阳极并且欧姆接触150充当器件阴极。钝化层160位于肖特基接触140与欧姆接触150之间。
在AlGaN层与GaN层之间的异质结界面处形成量子阱，所述AlGaN层具有大带隙，并且所述GaN层具有较窄带隙。因此，电子被俘获在量子阱中。被俘获的电子由GaN外延层中的二维(2DEG)电子气170表示，并且因此，电子沿着阳极与阴极之间的沟道流动。从而，由于其操作基于二维电子气，沟道中的电荷载流子建立横向方向上的电流。
图1所示的二极管的一个问题是其导通电阻因增加的总接触电阻而相对较大，这是由于2DEG电子气的正向电流必须流过AlGaN势垒层135才能到达阴极150，其中与硅相比，对GaN基材料的欧姆接触电阻一般显著更高。另外，因为阳极和阴极位于器件的相同面上，所需的管芯面积也相对较大。此外，二极管的热性能相对较差，因为热耗散受限于管芯的仅一个面。
发明内容
根据本发明，半导体器件包括衬底和第一有源层，所述衬底具有第一面和第二面，并且所述第一有源层设置在衬底的第一面上方。第二有源层设置在所述第一有源层上。第二有源层具有比第一有源层更高的带隙，使得在第一有源层与第二有源层之间出现二维电子气层。至少一个沟槽延伸穿过第一有源层和第二有源层及二维电子气层并进入衬底中。导电材料内衬于所述沟槽上。第一电极设置在第二有源层上并且第二电极设置在衬底的第二面上。
附图说明
图1示出了常规GaN基二极管的例子。
图2示出了根据本发明构造的GaN基二极管的例子。
图3-图7示出了可用于制造图2所示GaN基二极管的一系列工艺步骤的一个例子。
图8和图9示出了根据本发明构造的GaN基金属-绝缘体-半导体(MIS)晶体管的例子。
图10和图11示出了根据本发明构造的GaN基高电子迁移率晶体管(HEMT)的例子。
具体实施方式
值得注意的是，本文对“一个实施例”或“实施例”的任何引用意指结合该实施例描述的具体特征、结构或特性包括在本发明的至少一个实施例中。短语“在一个实施例中”在说明书各个位置的出现不一定全都指相同实施例。此外，各种实施例可以许多方式组合，从而得出未在本文明确示出的另外实施例。
如下文详述，提供了例如GaN基功率器件诸如二极管或晶体管，其具有相对较低导通电阻。如此前提及，存在因横向GaN基器件(诸如图1所示)的使用而产生的多个缺点。这些缺点包括导通电阻增大、器件所占面积增加以及热耗散较差。
相比之下，如下文详述，垂直GaN基功率器件诸如二极管或晶体管可克服这些问题。这种器件可通过将阴极从器件的顶部(如图1的常规器件中所示)移动到器件的背部来实现，其中阴极与低电阻率衬底210接触。这样，电流在横向(穿过2-D沟道)和垂直两种方向上于阳极与阴极之间传导。因此，从顶部电极流出的电流可在2D沟道中传输，然后流动到底部电极，从而降低总电阻。在2-D沟道与阴极之间提供导电通路以将电流传导到阴极。在一个实施例中，通过用导电材料内衬一个或多个沟槽来提供导电通路。
图2示出了根据本发明构造的GaN基二极管的例子。二极管包括低电阻率衬底210、GaN缓冲层220、第一有源层诸如GaN外延层230以及第二有源层诸如氮化铝镓(AlXGa1-XN；0<X<1)势垒层235。一对沟槽240被蚀刻穿过势垒层235、GaN外延层230和GaN缓冲层220，并延伸到低电阻率衬底210中。沟槽240上内衬有导电材料245，诸如钛、铝或金。第一金属层与氮化铝镓势垒层235形成肖特基接触250并充当阳极。第二金属层与衬底210的背侧形成欧姆接触260并充当阴极。钝化层270填充沟槽240并覆盖势垒层235的暴露部分。
如图2中所指出，现在在横向方向上穿过2D沟道225且在垂直方向上穿过内衬于沟槽240的导电材料245来提供连续导电通路。这样，当在阳极与阴极之间施加电压差时，在这两者之间产生电流。有利的是，与图1的器件相比，电流必须穿过图2所示器件中的二维沟道传输的横向距离减小。此外，电流可穿过低电阻率衬底传导到阴极，从而降低总电阻。
可以使用外延生长工艺来制造GaN基二极管。例如，可以使用反应溅射工艺，在该工艺中，在紧邻衬底设置的金属靶和衬底都处于包括氮和一个或多个掺杂物的气氛中时，从金属靶逐出诸如镓、铝和/或铟的半导体的金属组分。作为另外一种选择，可以采用金属有机化学气相沉积(MOCVD)，其中在将衬底保持在升高的温度，通常在700℃至1100℃左右下的同时，将衬底暴露于包含金属的有机化合物的气氛，以及诸如氨的反应含氮气体和含掺杂物气体中。气体化合物分解，并且在衬底的表面上形成晶体材料膜的形式的掺杂的半导体。然后将衬底和生长的膜冷却。作为另外的替代形式，可以使用诸如分子束外延(MBE)或原子层外延的其它外延生长方法。可以采用的另外的技术包括但不限于流量调制有机金属气相外延(FM-OMVPE)、有机金属气相外延(OMVPE)、氢化物气相外延(HVPE)和物理气相沉积(PVD)。
图3-图5示出了可用于制造图2所示GaN基二极管的一系列工艺步骤的一个例子。为了开始生长结构，可以在衬底210上沉积任选的成核层212(图3)。衬底210是适用于GaN沉积的低电阻率衬底。合适衬底的示例性例子可由例如重掺杂硅或重掺杂碳化硅形成。成核层212可以是例如富铝层，诸如AlXGa1-XN，其中X在0至1的范围内。成核层212通过形成衬底210的晶体结构与GaN缓冲层220的晶体结构之间的界面，而起到校正GaN缓冲层220与衬底210之间的晶格失配的作用。
在沉积成核层212(如果采用的话)之后，在成核层212上沉积GaN缓冲层220，在缓冲层220上形成GaN外延层230，并且在GaN外延层230上沉积AlXGa1-XN势垒层235(图4)。二维导电沟道225为薄的高迁移率沟道，其使载流子局限于GaN外延层230与AlXGa1-XN势垒层235之间的界面区域。
延伸到衬底210中的沟槽240可通过蚀刻工艺形成(图5)。例如，可采用光刻技术，其中光致抗蚀剂涂覆在氧化物层上，所述氧化物层形成于势垒层235上以限定沟槽240，所述沟槽240使用例如等离子体蚀刻工艺诸如反应离子蚀刻(RIE)或电感耦合等离子体蚀刻(ICP)来蚀刻。应该指出的是，沟槽底部可具有多种构型，包括例如v形、倒圆u形和正方形构型。
内衬于沟槽上的导电层245(参见图6)可通过低电阻率导电金属的溅镀、沉积或真空蒸镀来形成，并且使用光刻和后续的蚀刻步骤来图案化。可通过使用诸如物理气相沉积(PVD)、等离子增强化学气相沉积(PECVD)、低压化学气相沉积(LPCVD)或原子层沉积(ALD)的技术生长介电材料的一个或多个高质量层，来制造钝化层270。
图7示出了在形成阳极250和阴极260之后最终的器件结构。可通过如下方式形成阳极250：首先使钝化层270轮廓成形，接着以溅镀、沉积或真空蒸镀方式沉积肖特基金属。然后使用光刻和后续的蚀刻步骤使阳极250图案化。可通过使用诸如溅镀、沉积或真空蒸镀的技术沉积欧姆金属，从而制造阴极260。
图8和图9示出了GaN基器件的其他例子，所述GaN基器件可设置有穿过二维沟道325的横向导电通路以及垂直导电通路。更具体地讲，示出了晶体管或开关，所述晶体管或开关具有位于衬底顶侧上的其源极和栅极(其中它们与AlXGa1-XN势垒层接触)以及位于衬底底侧上的其漏极。
图8示出了金属-绝缘体-半导体(MIS)晶体管，其包括衬底310、GaN缓冲层320、第一有源层诸如GaN外延层330以及第二有源层诸如氮化铝镓(AlXGa1-XN；0<X<1)势垒层335。一对沟槽340被蚀刻穿过势垒层330并延伸到衬底310中。沟槽340上内衬有导电材料345，诸如钛、铝或金。一对肖特基接触355形成于介电材料365上，所述介电材料365可为二氧化硅、氮化硅、氧化铝、氮化铝等等。介电材料365形成于氮化铝镓势垒层335上与沟槽340相邻的地方，并充当栅极。欧姆电极350直接形成于氮化铝镓势垒层335上并位于各栅极电极35之间。欧姆电极350充当源极。欧姆漏极电极360形成于衬底310的背侧上并充当漏极。钝化层370填充沟槽340并覆盖栅极电极355。在图9所示的可供选择的实施例中，栅极电极355暴露。
图10展示了高电子迁移率晶体管(HEMT)，其包括衬底410、GaN缓冲层420、第一有源层诸如GaN外延层430以及第二有源层诸如氮化铝镓(AlXGa1-XN；0<X<1)势垒层435。一对沟槽440被蚀刻穿过势垒层430和2D沟道425并延伸到衬底410中。沟槽440上内衬有导电材料445，诸如钛、铝或金。一对肖特基接触455形成于氮化铝镓势垒层435上与沟槽440相邻的地方并充当栅极。欧姆电极450直接形成于氮化铝镓势垒层435上两个栅极电极455之间，并充当源极。欧姆漏极电极460形成于衬底410的背侧上并充当漏极。钝化层470填充沟槽440并覆盖栅极电极455。在图11所示的可供选择的实施例中，栅极电极455暴露。
在其其他优点当中，上述功率半导体器件具有穿过低电阻率导电通路的降低的总电阻。另外，就二极管而言，因为阳极和阴极位于器件的相反面上，所需的管芯面积可减小(在一些实施例中减小约20％)。从而，器件也具有降低的导通电阻。此外，热性能器件被增强，因为在管芯的两个面上都发生热耗散。
虽然本文明确示出并描述了各种实施例，但应当理解在不脱离本发明的精神和预期范围的情况下，本发明的修改形式和变型形式被上面的教导内容所涵盖并且在所附权利要求书的范围内。例如，虽然功率半导体器件已被描述为GaN基器件，但本发明更一般地涵盖由任何III族氮化物化合物半导体形成的功率半导体器件，其中III族元素可为镓(Ga)、铝(Al)或铟(In)。
Claims (17)
1.一种半导体器件，所述半导体器件包括：
衬底，所述衬底具有第一面和第二面；
第一有源层，所述第一有源层设置在所述衬底的所述第一面上方；
第二有源层，所述第二有源层设置在所述第一有源层上，所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层与所述第二有源层之间出现二维电子气层；
至少一个沟槽，所述至少一个沟槽延伸穿过所述第一有源层和所述第二有源层以及所述二维电子气层并且进入所述衬底中；
导电材料，所述导电材料内衬于所述沟槽；
第一电极，所述第一电极设置在所述第二有源层上；
第二电极，所述第二电极设置在所述衬底的所述第二面上，以及
设置在所述第二有源层上的第三电极，所述第一电极、所述第二电极和所述第三电极分别为源极电极、漏极电极和栅极电极，
其中，在横向方向上穿过所述二维电子气层并且在垂直方向上穿过所述导电材料来提供连续导电通路。
2.根据权利要求1所述的半导体器件，其中所述至少一个沟槽包括一对沟槽，所述一对沟槽延伸穿过所述第一有源层和所述第二有源层以及所述二维电子气层并且进入所述衬底中，所述沟槽中的每一个内衬有导电材料。
3.根据权利要求1所述的半导体器件，其中所述第一有源层包括外延层。
4.根据权利要求1所述的半导体器件，其中所述第一电极是肖特基接触。
5.根据权利要求4所述的半导体器件，其中所述第二电极是欧姆接触。
6.根据权利要求1所述的半导体器件，其中所述第一有源层包括III族氮化物半导体材料。
7.根据权利要求6所述的半导体器件，其中所述第一有源层包括GaN。
8.根据权利要求1所述的半导体器件，其中所述第二有源层包括III族氮化物半导体材料。
9.根据权利要求8所述的半导体器件，其中所述第二有源层包括AlXGa1-XN，其中0<X<1。
10.根据权利要求1所述的半导体器件，还包括介电层，所述介电层设置在所述第三电极中的每一个与所述第二有源层之间。
11.根据权利要求1所述的半导体器件，其中所述第三电极是肖特基电极。
12.根据权利要求1所述的半导体器件，还包括填充所述沟槽的钝化材料。
13.一种形成半导体器件的方法，所述方法包括：
在衬底上形成第一有源层；
在所述第一有源层上方形成第二有源层，所述第二有源层具有比所述第一有源层高的带隙，使得在所述第一有源层与所述第二有源层之间出现二维电子气层；
形成至少一个沟槽，所述至少一个沟槽延伸穿过所述第一有源层和所述第二有源层以及所述二维电子气层并且进入所述衬底中；
用导电材料内衬所述沟槽；
用钝化材料填充所述沟槽；
在所述第二有源层上形成第一电极；
在所述衬底的底面上形成第二电极；以及
形成设置在所述第二有源层上的第三电极，所述第一电极、所述第二电极和所述第三电极分别为源极电极、漏极电极和栅极电极，
其中，在横向方向上穿过所述二维电子气层并且在垂直方向上穿过所述导电材料来提供连续导电通路。
14.根据权利要求13所述的方法，其中所述至少一个沟槽包括一对沟槽，并且还包括形成所述一对沟槽，使得所述沟槽中的每一个延伸穿过所述第一有源层和所述第二有源层以及所述二维电子气层并且进入所述衬底中，所述沟槽中的每一个内衬有导电材料并且填充有钝化材料。
15.根据权利要求13所述的方法，其中所述第一电极是肖特基接触。
16.根据权利要求15所述的方法，其中所述第二电极是欧姆接触。
17.根据权利要求13所述的方法，其中所述第一有源层包括III族氮化物半导体材料。
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| US9269789B2 (en) * | 2013-03-15 | 2016-02-23 | Semiconductor Components Industries, Llc | Method of forming a high electron mobility semiconductor device and structure therefor |
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2013
- 2013-07-09 US US13/937,724 patent/US9368584B2/en active Active
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| US20150014696A1 (en) | 2015-01-15 |
| WO2015006028A1 (en) | 2015-01-15 |
| KR20160030254A (ko) | 2016-03-16 |
| EP3020070A1 (en) | 2016-05-18 |
| EP3020070A4 (en) | 2017-03-08 |
| US9368584B2 (en) | 2016-06-14 |
| CN105474405A (zh) | 2016-04-06 |
| JP6448637B2 (ja) | 2019-01-09 |
| TWI533453B (zh) | 2016-05-11 |
| KR101771022B1 (ko) | 2017-09-05 |
| JP2016526802A (ja) | 2016-09-05 |
| TW201515220A (zh) | 2015-04-16 |
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