CN105470131A - Method for fabricating back hole of gallium arsenide-based HEMT device - Google Patents
Method for fabricating back hole of gallium arsenide-based HEMT device Download PDFInfo
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- CN105470131A CN105470131A CN201511032303.2A CN201511032303A CN105470131A CN 105470131 A CN105470131 A CN 105470131A CN 201511032303 A CN201511032303 A CN 201511032303A CN 105470131 A CN105470131 A CN 105470131A
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- Prior art keywords
- gallium arsenide
- hemt device
- dorsal pore
- plating
- semiconductor substrate
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- 229910001218 Gallium arsenide Inorganic materials 0.000 title claims abstract description 41
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 title claims abstract description 40
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 23
- 150000001875 compounds Chemical class 0.000 claims abstract description 13
- 238000001259 photo etching Methods 0.000 claims abstract description 12
- 238000009713 electroplating Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims abstract description 6
- 238000005498 polishing Methods 0.000 claims abstract description 5
- 238000001020 plasma etching Methods 0.000 claims abstract description 4
- 239000011148 porous material Substances 0.000 claims description 23
- 239000010931 gold Substances 0.000 claims description 12
- 238000007747 plating Methods 0.000 claims description 9
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000004544 sputter deposition Methods 0.000 claims description 8
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- 238000007772 electroless plating Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 claims description 4
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910001258 titanium gold Inorganic materials 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000005260 corrosion Methods 0.000 claims 1
- 230000007797 corrosion Effects 0.000 claims 1
- 238000004806 packaging method and process Methods 0.000 claims 1
- 238000010894 electron beam technology Methods 0.000 description 9
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 9
- 239000004926 polymethyl methacrylate Substances 0.000 description 9
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 3
- 239000003960 organic solvent Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 239000005357 flat glass Substances 0.000 description 1
- -1 gallium arsenide compound Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention discloses a method for fabricating a back hole of a gallium arsenide-based HEMT device. The method comprises the following steps: (1) fabricating an active region of the gallium arsenide-based HEMT device; (2) forming the back hole in the front surface of a compound semiconductor substrate by photoetching and etching methods, fabricating a backmetal process in manners of electroplating and the like and finishing device fabrication; (3) adhering a gallium arsenide substrate and a temporary substrate; (4) carrying out thinning and polishing on the compound semiconductor substrate until the thickness of the compound substrate is reduced to 100 microns; (5) etching the back surface of the substrate in a plasma etching manner until backmetal is exposed out of a back hole region; and (6) finally electroplating the back surface of gallium arsenide with the backmetal, and finishing the gallium arsenide-based HEMT device.
Description
Technical field
The present invention relates to a kind of manufacture method of GaAs based HEMT device dorsal pore, belong to the technical field of semiconductor manufacturing.
Technical background
Along with the continuous progress of GaAs based semiconductor device, GaAs based compound semiconductor materials can the physical characteristic such as band structure, high electron mobility of cutting be used widely in THz devices technical field with it, but dorsal pore and back of the body gold process are still the fundamental technologies in GaAs based semiconductor device, making quality is good, the degree of depth is controlled, the good GaAs based HEMT device of consistency for improving in the industry device reliability, reduce technique and become not there is very large effect.The dorsal pore of traditional GaAs based HEMT device be all thinning overleaf after, carry out back side photoetching and carry out.But owing to adopting back side photoetching, this adds increased photoetching cost, can reduce photoetching cost greatly by front through hole technology, for this reason, the front through hole of GaAs based HEMT device is all a significant technology issues all the time.
Summary of the invention
(1) technical problem that will solve
The important technological problems that high, the thinning severity control difficulty of photoetching cost that technical problem to be solved by this invention is back side photoetching, etching makes dorsal pore is large, in direct thinning process, due to very thin substrate will be realized, etch with dorsal pore, this just needs special back side mask aligner to carry out lithography alignment, in the process of etching dorsal pore, etching must terminate on the metal in front, and the monitoring of backside through vias etching is more difficult.Particularly special double face photoetching machine adds fixed assets investment, cost is high.So realize GaAs device through hole to become a kind of economical and practical technology from front.
(2) technical scheme
In order to solve the technical problem that etching monitoring difficulty is large, cost is high that above back side making GaAs dorsal pore brings, 1 being described by reference to the accompanying drawings, the invention provides a kind of method that front makes GaAs based HEMT dorsal pore: it comprises the steps:
(1) complete HEMT device active area on GaAs based epitaxial material, comprises the steps such as source and drain, grid and mesa-isolated;
(2) then adopt photoetching, the method for etching forms required dorsal pore in compound semiconductor substrate sheet front, etch into 60-100 micron dark, and soak with organic solvent and remove photoresist;
(3) adopt the method sputtering furling plating Ti/Au of sputtering, thickness is 20/50 nanometer, and adopts electroless plating mode to make via metal technique, completes GaAs HEMT device front technique;
(4) be coated with electron beam resist PMMA in gallium arsenide semiconductor substrate slice front, thickness is 5 microns, 180 degree of hot plate bake 3min;
(5) on temporary substrates sheet, high temperature wax is smeared;
(6) gallium arsenide semiconductor substrate and temporary substrates sheet are adhered to;
(7) to GaAs based Semiconductor substrate sheet carry out fast thinning, thinning, polishing is until compound base substrate thickness down is to 120 microns at a slow speed;
(8) mode of using plasma etching, the etched substrate back side, until back of the body gold is exposed in dorsal pore region;
(9) back side watery hydrochloric acid is cleaned up;
(10) sputtered with Ti/Au is as playing plating overleaf to adopt sputtering method, and thickness is 30/80 nanometer, adopts the method electroplating mild alloy 30 microns overleaf of electroless plating, completes double-edged GaAs HEMT device.
(11) mode adopting organic solvent to soak removes adhesive high temperature wax and electron beam resist PMMA.Take off gallium arsenide substrate sheet, and carry out scribing process.
In described step (1), HEMT device has completed all techniques of device except dorsal pore electroplating technology.
In described step (2), etch mask is photoresist 4620, and thickness is 15 microns, and etching mode is ICP etching.
In described step (2), remove photoresist and adopt the cleaning of acetone, ethanol, DI water.
In described step (4), on the gallium arsenide semiconductor epitaxial wafer being etched with through hole, be first coated with PMMA electron beam resist 2 microns, 180 drying glues 2 minutes; And then be coated with PMMA electron beam resist 3 microns, 180 degree of thick glue of hot plate 2 minutes, be coated with PMMA electron beam resist 5 microns altogether thereon.
In described step (5); can be nitrogenize silicon chip, sheet glass, quartz plate etc. to temporary substrates sheet; silica dioxide medium protection is carried out on temporary substrates sheet surface; be mainly used in the secondary recovery recycling of substrate slice; complete again thinning after; silicon dioxide etching is fallen, good substrate surface can be recovered.
In described step (7), thinning to compound semiconductor substrate, be divided into three phases, the first stage is thinning fast, can be thinned to 120 microns of micron thickness; Second stage is thinning at a slow speed, can be thinned to 100 microns of microns; Phase III is that polishing is thinning.
In described step (8), etching process must carry out etching monitoring at table top exterior domain, and etch rate controls within 1 micrometers per minutes, because photoresist is different from the etch rate of compound semiconductor, to having etched compound semiconductor, after over etching 30sec, complete etching.
(3) beneficial effect
As can be seen from technique scheme, the present invention has following beneficial effect:
The gallium arsenide semiconductor dorsal pore manufacture method that the present invention adopts, first active area technique is carried out in front, then lithographic definition lead to the hole site is carried out in front, adopt the through hole of the method etching desired depth of ICP etching, then electroplating ventilating hole metal, the method etching adopting thinning back side, large area to etch again exposes via metal region, finally makes back of the body gold.The advantage of this technique is first to adopt double face photoetching machine just can complete via process, and next reduces the degree of dependence to thinning back side equipment precision, can make greatly cost-saving for gallium arsenide semiconductor HEMT device.
Accompanying drawing illustrates:
Fig. 1 is the fabrication processing figure of GaAs based HEMT device dorsal pore.
Embodiment
The present embodiment provides a kind of method of gaas compound semiconductor substrate thinning, comprises the steps:
(1) complete HEMT device active area on gallium arsenide compound epitaxial material;
(2) AZ4620 photoresist is adopted to form out through hole, post bake 2 minutes on 115 degree of hot plates as mask in the definition of HEMT device source; Adopt ICP etching machine again, etching gas is chlorine and boron chloride, and etching depth is the through hole of 100 microns, finally soaks with acetone and removes photoresist, and adopt acetone, ethanol, washed with de-ionized water clean;
(3) adopt the method sputtering furling plating Ti/Au of sputtering, thickness is 20/50 nanometer, and adopts electroless plating mode to make via metal, and the thickness of via metal is 10 microns, completes the front technique of GaAs based HEMT device;
(4) complete on the gallium arsenide epitaxy sheet of HEMT device in front, be first coated with PMMA electron beam resist 2 microns, 180 drying glues 2 minutes; And then be coated with PMMA electron beam resist 3 microns, 180 degree of thick glue of hot plate 2 minutes, be coated with PMMA electron beam resist 5 microns altogether thereon.
(5) on temporary substrates sheet, high temperature wax is smeared;
(6) gallium arsenide semiconductor substrate and temporary substrates sheet are adhered to;
(7) to GaAs based Semiconductor substrate sheet carry out fast thinning, thinning, polishing is until compound base substrate thickness down is to 120 microns at a slow speed;
(8) mode of using plasma etching, the etched substrate back side, until back of the body gold is exposed in dorsal pore region;
(9) back side watery hydrochloric acid is cleaned up;
(10) sputtered with Ti/Au is as playing plating overleaf to adopt sputtering method, and thickness is 30/80 nanometer, adopts the method electroplating mild alloy 30 microns overleaf of electroless plating, completes GaAsHEMT device.
(11) mode adopting organic solvent to soak removes adhesive high temperature wax and electron beam resist PMMA.Take off gallium arsenide substrate sheet, and carry out scribing process.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. make a method for GaAs based HEMT device dorsal pore, it comprises the steps:
(1) complete HEMT device active area on GaAs based epitaxial material;
(2) then adopt photoetching, the method for etching forms required packaging dorsal pore in compound semiconductor substrate sheet front, etch into 60-100 micron dark, and adopt the modes such as plating to make back of the body gold process, complete element manufacturing;
(3) at gallium arsenide semiconductor substrate slice front resist coating;
(4) on temporary substrates sheet, high temperature wax is smeared;
(5) gallium arsenide semiconductor substrate and temporary substrates sheet are adhered to;
(6) to GaAs based Semiconductor substrate sheet carry out fast thinning, thinning, polishing is until compound base substrate thickness down is to 100 microns at a slow speed;
(7) mode of using plasma etching, the etched substrate back side, until back of the body gold is exposed in dorsal pore region;
(8) back side watery hydrochloric acid is cleaned up;
(9) sputtered with Ti Au is as playing plating overleaf finally to adopt sputtering method, and the method electroplating mild alloy 30 microns overleaf of employing electroless plating, completes existing dorsal pore back of the body gold, have again the GaAsHEMT device that active area is heat sink.
2. a kind of method making GaAs based HEMT device dorsal pore according to claim 1, it is characterized in that: described in step (2), define dorsal pore after, first the method for sputtering is adopted to make TiAu as furling plating, then the method definition plating area of photoetching is adopted, electrogilding, then remove photoresist, corrosion furling plating TiAu layer.
3. a kind of method making GaAs based HEMT device dorsal pore according to claim 1, is characterized in that: described adopt in the step (7) in ICP etching machine with end-point detecting system aim at dorsal pore position, detect and whether expose back of the body gold.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032303.2A CN105470131A (en) | 2015-12-30 | 2015-12-30 | Method for fabricating back hole of gallium arsenide-based HEMT device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511032303.2A CN105470131A (en) | 2015-12-30 | 2015-12-30 | Method for fabricating back hole of gallium arsenide-based HEMT device |
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| CN105470131A true CN105470131A (en) | 2016-04-06 |
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| CN201511032303.2A Pending CN105470131A (en) | 2015-12-30 | 2015-12-30 | Method for fabricating back hole of gallium arsenide-based HEMT device |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870007A (en) * | 2016-04-22 | 2016-08-17 | 杭州立昂东芯微电子有限公司 | Gallium arsenide back hole dry-etching process by inductive coupling plasma |
| CN106409671A (en) * | 2016-07-21 | 2017-02-15 | 东莞市青麦田数码科技有限公司 | Compound-based semiconductor ultrathin substrate manufacturing method |
| CN106505007A (en) * | 2016-12-26 | 2017-03-15 | 成都海威华芯科技有限公司 | A kind of endpoint monitoring suitable of HEMT dorsal pore etching |
| CN107946274A (en) * | 2017-11-23 | 2018-04-20 | 成都海威华芯科技有限公司 | A kind of mmic chip and its back side dicing lane manufacture craft |
| CN113808948A (en) * | 2021-09-06 | 2021-12-17 | 中国电子科技集团公司第五十五研究所 | Method for preparing back hole of GaN device on diamond substrate |
| CN114566461A (en) * | 2022-03-02 | 2022-05-31 | 成都海威华芯科技有限公司 | Semiconductor device deep back hole manufacturing method and device based on front and back side through holes |
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| CN101442071A (en) * | 2008-12-18 | 2009-05-27 | 中国科学院微电子研究所 | Gallium nitride based field effect transistor and preparation method thereof |
| CN102214565A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for thinning silicon carbide wafer |
| CN102339751A (en) * | 2010-07-21 | 2012-02-01 | 中国科学院微电子研究所 | Method for improving gallium nitride base field effect tube post-process |
| CN103811413A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Process for manufacturing semiconductor substrate |
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2015
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105870007A (en) * | 2016-04-22 | 2016-08-17 | 杭州立昂东芯微电子有限公司 | Gallium arsenide back hole dry-etching process by inductive coupling plasma |
| CN106409671A (en) * | 2016-07-21 | 2017-02-15 | 东莞市青麦田数码科技有限公司 | Compound-based semiconductor ultrathin substrate manufacturing method |
| CN106505007A (en) * | 2016-12-26 | 2017-03-15 | 成都海威华芯科技有限公司 | A kind of endpoint monitoring suitable of HEMT dorsal pore etching |
| CN106505007B (en) * | 2016-12-26 | 2019-03-26 | 成都海威华芯科技有限公司 | A kind of endpoint monitoring suitable of high electron mobility transistor dorsal pore etching |
| CN107946274A (en) * | 2017-11-23 | 2018-04-20 | 成都海威华芯科技有限公司 | A kind of mmic chip and its back side dicing lane manufacture craft |
| CN113808948A (en) * | 2021-09-06 | 2021-12-17 | 中国电子科技集团公司第五十五研究所 | Method for preparing back hole of GaN device on diamond substrate |
| CN114566461A (en) * | 2022-03-02 | 2022-05-31 | 成都海威华芯科技有限公司 | Semiconductor device deep back hole manufacturing method and device based on front and back side through holes |
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Application publication date: 20160406 |