CN106409671A - Compound-based semiconductor ultrathin substrate manufacturing method - Google Patents
Compound-based semiconductor ultrathin substrate manufacturing method Download PDFInfo
- Publication number
- CN106409671A CN106409671A CN201511031287.5A CN201511031287A CN106409671A CN 106409671 A CN106409671 A CN 106409671A CN 201511031287 A CN201511031287 A CN 201511031287A CN 106409671 A CN106409671 A CN 106409671A
- Authority
- CN
- China
- Prior art keywords
- compound
- substrate
- etching
- semiconductor substrate
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
The invention discloses a compound-based semiconductor ultrathin substrate manufacturing method. The method includes 1) manufacturing a device in a compound-based epitaxial material layer; 2) and then forming an isolated table top of a device to be packaged on the right side of a compound semiconductor substrate sheet by means of lithography and etching methods, and etching to the depth of 3-10 micrometers; 3) coating a photoresist on the right side of the compound semiconductor substrate sheet; 4) growing 20 nm of protective medium silica on a temporary substrate sheet; 5) bonding the compound semiconductor substrate to the temporary substrate sheet; 6) performing rapid thinning, slow thinning, polishing on the compound-based semiconductor substrate sheet until the thickness of the compound-based substrate is thinned to 20-30 micrometers; 7) etching the back side of the substrate by means of plasma etching until the epitaxial layer outside the table top are fully etched; and 8) removing the adhesive and photoresist by organic solvent immersion to obtain a compound-based semiconductor device having a substrate thickness of 3 to 10 micrometers.
Description
Technical field
The present invention relates to a kind of ultra-thin substrate preparation method of compound base semiconductor, belong to the technical field of semiconductor manufacturing.
Technical background
Continuous progress with Terahertz Technology, compound semiconductor materials can the physical characteristic such as the band structure of cutting, high electron mobility be used widely in THz devices technical field with it, but because operating frequency is high, the substrate loss of Terahertz solid state device can not be ignored, the substrate thickness reducing Terahertz solid state device is all unanimously the important means that industry improves THz devices performance, is also significant technology issues.
Existing using the method that directly thinning mode reduces THz devices substrate thickness, during actual process, operating error is big, and substrate planarization is poor, and causes to operate airplane crash to subsequent technique, need to improve this traditional thinning mode.
Content of the invention
（One）Technical problem to be solved
The technical problem to be solved is the problem that substrate planarization is poor, error is big that directly thinning making THz devices cause, in direct thinning process, due to very thin substrate will be realized, in post production process, thinning speed must drop to very low, and because substrate is as thin as less than 10 microns, during such as going adhesive, scribing etc. to subsequent technique, suffer from very big operation easier.
（Two）Technical scheme
In order to solve above technical problem, illustrate in conjunction with accompanying drawing 1-6, the invention provides a kind of ultra-thin substrate preparation method of compound base semiconductor：It comprises the steps：
(1) complete on compound base epitaxial material THz devices；
(2) form the isolation table top of depth around THz devices using the method for photoetching, etching, etching depth is 3-10 micron, removes photoresist, and cleans up；
(3) in compound semiconductor substrate piece front resist coating, photoresist is PMMA electron beam resist, and carries out 180 DEG C of 3 minutes post bakes；
(4) 20 nanometers of growth protecting medium silica on temporary substrates piece, growth pattern is PECVD；
(5) compound semiconductor substrate is adhered to temporary substrates piece, adhesive is low-temperature wax；
(6) compound base semiconductor substrate slice is carried out with quickly thinning, thinning, polishing at a slow speed, until compound base substrate thickness down is to 20-30 micron；
(7) mode of using plasma etching, the etched substrate back side, the epitaxial layer outside table top all etches away；
(8) remove adhesive and photoresist by the way of organic solvent immersion, obtain the compound based semiconductor device that substrate thickness is 3-10 micron.
Described compound semiconductor is the semi-conducting material such as GaAs, indium phosphide, gallium nitride, carborundum.
In described step (1), THz devices include heterojunction bipolar transistor, HEMT, Schottky diode, honest and just formula diode etc..
In described step (2), etch mask is photoresist 4620, and thickness is 15 microns, and etching mode etches for ICP.
In described step (2), remove photoresist using acetone, ethanol, the cleaning of DI water.
In described step (3), on the compound semiconductor epitaxial piece being etched with isolation deep trouth, first apply 4 microns of PMMA electron beam resist, 180 drying glues 2 minutes；Then apply 6 microns of PMMA electron beam resist, 180 degree hot plate thickness glue 2 minutes again, apply altogether 10 microns of PMMA electron beam resist thereon.
In described step (4); can be silicon chip, nitridation silicon chip, sheet glass, quartz plate etc. to temporary substrates piece; carry out silica dioxide medium protection on temporary substrates piece surface; the secondary recovery being mainly used in substrate slice recycles; complete again thinning after; silicon dioxide etching is fallen, you can recover good substrate surface.
In described step (4), can be silicon nitride, alundum (Al2O3) etc. to interim protection medium.
In described step (6), thinning to compound semiconductor substrate, it is divided into three phases, the first stage is quickly thinning, 35-50 micron micron thickness can be thinned to；Second stage is thinning at a slow speed, can be thinned to 20-25 micron micron；Phase III is that polishing is thinning.
In described step (7), etching process must perform etching monitoring in table top exterior domain, and etch rate controls within 1 micrometers per minutes, because photoresist is different from the etch rate of compound semiconductor, to having etched compound semiconductor, complete after over etching 30sec to etch.
In described step (8), remove initially with going wax liquor low-temperature wax to be carried out soak, then from acetone, ethanol, DI water, substrate slice is carried out, thus obtaining the compound based semiconductor device that substrate thickness is 3-10 micron.
（Three）Beneficial effect
From technique scheme as can be seen that the present invention has following beneficial effect：
The compound semiconductor substrate thining method that the present invention adopts, carry out mesa-isolated in front first and substrate thickness is demarcated, and then obtain thinning accordingly and etching technics, mainly substrate thickness, process is simple are determined by front etching technics, thickness controllability is good, secondly the method overleaf adopting etching in technique, monitored by etching and ensure that substrate thickness error it is possible to reduce the thickness error of substrate by adjusting etch rate, the parametric stability for THz devices provides guarantee.
Brief description：
Fig. 1 makes schematic diagram after deep mesa for compound semiconductor substrate
Fig. 2 is structural representation after compound semiconductor substrate piece resist coating adhesive
Fig. 3 is schematic diagram after temporary substrates piece growth SiO2
Fig. 4 is the structural representation after being adhered to compound semiconductor substrate piece and temporary substrates piece
Fig. 5 is that compound semiconductor substrate carries out the structural representation after attenuated polishing
Fig. 6 is that compound semiconductor substrate piece carries out the structural representation after back-etching
In accompanying drawing, mark is expressed as：1- compound semiconductor substrate piece, 2-PMMA and adhesive-low-temperature wax, 3- temporary substrates piece, 4- silica.
Specific embodiment
The present embodiment provides a kind of method of gaas compound semiconductor substrate thinning, comprises the steps：
(1) complete on gallium arsenide compound epitaxial material Schottky diode THz devices；
(2) adopt AZ4620 photoresist to define around THz devices as mask and form deep isolation table top, using ICP etching, etching gas are chlorine and boron chloride, and etching depth is 6 microns, removed photoresist with acetone, and cleaned up using acetone, ethanol, deionized water；
(3) on the gallium arsenide epitaxy piece being etched with isolation deep trouth, 4 microns of PMMA electron beam resist, 180 drying glues 2 minutes are first applied；Then apply 6 microns of PMMA electron beam resist, 180 degree hot plate thickness glue 2 minutes again, apply altogether 10 microns of PMMA electron beam resist thereon.
(4) 20 nanometers of growth protecting medium silica on quartz substrate piece, growth pattern is PECVD；
(5) gallium arsenide semiconductor substrate face is adhered to quartz substrate piece, adhesive is low-temperature wax；
(6) gallium arsenide semiconductor substrate slice is carried out with quickly thinning, thinning, polishing at a slow speed, until compound base substrate thickness down is to 25 microns；
(7) by the way of ICP plasma etching, etching gas are chlorine and boron chloride, the etched substrate back side, monitoring is performed etching using the end-point detecting system that ICP system carries, the epitaxial layer outside table top all etches away, expose PMMA photoresist, over etching 30sec, stops etching；
(8) remove adhesive and photoresist by the way of going the organic solvents such as wax liquor, acetone, ethanol to soak, obtain the compound based semiconductor device that substrate thickness is 6 microns.
Particular embodiments described above; the purpose of the present invention, technical scheme and beneficial effect are further described; be should be understood that; the foregoing is only the specific embodiment of the present invention; it is not limited to the present invention; all any modification, equivalent substitution and improvement within the spirit and principles in the present invention, done etc., should be included within the scope of the present invention.
Claims (1)
1. the ultra-thin substrate preparation method of a kind of compound base semiconductor, it comprises the steps：
(1) complete on compound base epitaxial material THz devices；
(2) form the isolation table top of depth around THz devices using the method for photoetching, etching, etching depth is 3-10 micron, removes photoresist, and cleans up；
(3) in compound semiconductor substrate piece front resist coating, photoresist is PMMA electron beam resist, and carries out 180 DEG C of 3 minutes post bakes；
(4) 20 nanometers of growth protecting medium silica on temporary substrates piece, growth pattern is PECVD；
(5) compound semiconductor substrate is adhered to temporary substrates piece, adhesive is low-temperature wax；
(6) compound base semiconductor substrate slice is carried out with quickly thinning, thinning, polishing at a slow speed, until compound base substrate thickness down is to 20-30 micron；
(7) mode of using plasma etching, the etched substrate back side, the epitaxial layer outside table top all etches away；
(8) remove adhesive and photoresist by the way of organic solvent immersion, obtain the compound based semiconductor device that substrate thickness is 3-10 micron.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511031287.5A CN106409671A (en) | 2016-07-21 | 2016-07-21 | Compound-based semiconductor ultrathin substrate manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511031287.5A CN106409671A (en) | 2016-07-21 | 2016-07-21 | Compound-based semiconductor ultrathin substrate manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106409671A true CN106409671A (en) | 2017-02-15 |
Family
ID=58007847
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511031287.5A Pending CN106409671A (en) | 2016-07-21 | 2016-07-21 | Compound-based semiconductor ultrathin substrate manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106409671A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110405546A (en) * | 2018-04-27 | 2019-11-05 | 半导体元件工业有限责任公司 | System and correlation technique is thinned in wafer |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7420225B1 (en) * | 2005-11-30 | 2008-09-02 | Sandia Corporation | Direct detector for terahertz radiation |
| CN102214555A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for thinning sapphire wafer |
| CN102427034A (en) * | 2011-11-23 | 2012-04-25 | 中国科学院微电子研究所 | Method of carrying out mirror polishing and thinning on GaAs wafer with ultrathin thickness |
| CN103489756A (en) * | 2013-10-11 | 2014-01-01 | 中国科学院微电子研究所 | Sheet bonding method in substrate thinning technique |
| CN105470131A (en) * | 2015-12-30 | 2016-04-06 | 东莞市青麦田数码科技有限公司 | Method for fabricating back hole of gallium arsenide-based HEMT device |
-
2016
- 2016-07-21 CN CN201511031287.5A patent/CN106409671A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7420225B1 (en) * | 2005-11-30 | 2008-09-02 | Sandia Corporation | Direct detector for terahertz radiation |
| CN102214555A (en) * | 2010-04-09 | 2011-10-12 | 中国科学院微电子研究所 | Method for thinning sapphire wafer |
| CN102427034A (en) * | 2011-11-23 | 2012-04-25 | 中国科学院微电子研究所 | Method of carrying out mirror polishing and thinning on GaAs wafer with ultrathin thickness |
| CN103489756A (en) * | 2013-10-11 | 2014-01-01 | 中国科学院微电子研究所 | Sheet bonding method in substrate thinning technique |
| CN105470131A (en) * | 2015-12-30 | 2016-04-06 | 东莞市青麦田数码科技有限公司 | Method for fabricating back hole of gallium arsenide-based HEMT device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110405546A (en) * | 2018-04-27 | 2019-11-05 | 半导体元件工业有限责任公司 | System and correlation technique is thinned in wafer |
| CN110405546B (en) * | 2018-04-27 | 2023-05-30 | 半导体元件工业有限责任公司 | Wafer thinning system and related method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI635569B (en) | Laser scribing and plasma etch for high die break strength and smooth sidewall | |
| JP6360477B2 (en) | Laser, plasma etching, and back grinding processes for wafer dicing | |
| JP6223325B2 (en) | In-situ deposition mask layer for device singulation by laser scribing and plasma etching | |
| KR102365042B1 (en) | Laser scribing and plasma etch for high die break strength and clean sidewall | |
| CN101523566B (en) | bonding method of chips and chips stacking pieces | |
| TWI698954B (en) | Dicing wafers having solder bumps on wafer backside | |
| TW201430935A (en) | Substrate dicing by laser ablation & plasma etch damage removal for ultra-thin wafers | |
| JP2016506087A (en) | Laser-plasma etched wafer dicing using an etch chamber shield ring for film frame wafer applications | |
| CN108288582B (en) | Wafer-level GaN device substrate transfer method | |
| JP2017500740A (en) | Method for dicing wafer and carrier therefor | |
| CN105470131A (en) | Method for fabricating back hole of gallium arsenide-based HEMT device | |
| WO2022166472A1 (en) | Preparation method for gan-on-diamond field effect transistor | |
| CN107634033B (en) | The inexpensive heterogeneous integrated approach in multi-chip constituency based on CMOS silicon based platform | |
| JPH10177974A (en) | Manufacturing method of device chip on hetero epistaxial wafer | |
| CN109950142B (en) | Transient adhesive tape transfer method without adhesion promoter | |
| CN106409671A (en) | Compound-based semiconductor ultrathin substrate manufacturing method | |
| CN111540710B (en) | Preparation method of high-heat-conductivity gallium nitride high-power HEMT device | |
| CN103094094B (en) | Prepared method of ultrathin semiconductor chip | |
| JP2004221423A (en) | Method for manufacturing semiconductor device | |
| CN100449686C (en) | Manufacturing method of power semi-conductor discrete device first floor photolithography para-position making | |
| TWI556303B (en) | Wafer dicing methods | |
| TW201810402A (en) | Etching method, etching apparatus and method for dividing a semiconductor wafer | |
| CN114068329A (en) | Method for preparing groove gate enhanced HEMT device based on CMP etching technology | |
| JPS60233831A (en) | Separation of semiconductor defect | |
| JP6561804B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180831 Address after: 523000 Room 301, 6B International Finance Innovation Park, Songshan Lake high tech Industrial Development Zone, Dongguan, Guangdong Applicant after: Dongguan Guangxin Intellectual Property Services Limited Address before: 523000 C10, 6 floor, brilliant business building, 81 South Central Road, Dongcheng District, Dongguan, Guangdong. Applicant before: DONGGUAN QINGMAITIAN DIGITAL TECHNOLOGY CO., LTD. |
|
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170215 |