CN108807162A - T-type grid preparation method - Google Patents
T-type grid preparation method Download PDFInfo
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- CN108807162A CN108807162A CN201810519181.7A CN201810519181A CN108807162A CN 108807162 A CN108807162 A CN 108807162A CN 201810519181 A CN201810519181 A CN 201810519181A CN 108807162 A CN108807162 A CN 108807162A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 22
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 37
- 230000004888 barrier function Effects 0.000 claims abstract description 27
- 229910052751 metal Inorganic materials 0.000 claims abstract description 25
- 239000002184 metal Substances 0.000 claims abstract description 25
- 238000000276 deep-ultraviolet lithography Methods 0.000 claims abstract description 21
- 238000005530 etching Methods 0.000 claims abstract description 5
- 239000004922 lacquer Substances 0.000 claims description 11
- 239000000463 material Substances 0.000 claims description 10
- 238000001259 photo etching Methods 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 3
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 claims description 3
- 239000002904 solvent Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 15
- 238000000034 method Methods 0.000 description 10
- 230000008569 process Effects 0.000 description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000609 electron-beam lithography Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 235000012431 wafers Nutrition 0.000 description 4
- 229910002601 GaN Inorganic materials 0.000 description 3
- 229910017083 AlN Inorganic materials 0.000 description 2
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- -1 InN Chemical compound 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910000943 NiAl Inorganic materials 0.000 description 1
- 229910018949 PtAu Inorganic materials 0.000 description 1
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical compound [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000004411 aluminium Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 235000011114 ammonium hydroxide Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The present invention relates to a kind of T-type grid preparation methods, including：Form barrier layer；Deep-UV lithography glue-line is formed on the barrier layer, and forms grid root groove in the photoresist layer；In the grid root groove and form metal layer on the deep-UV lithography glue-line；Photoresist layer is formed on the metal layer, and forms grid cover figure in the photoresist layer；Etching is not by the metal layer of the grid cover figure covering part；Remove the deep-UV lithography glue-line and grid cover figure photoresist.Above-mentioned T-type grid preparation method can make the line width of T-type grid be less than the preparation efficiency for the T-type grid that 100 nanometers improve again simultaneously.And since medium being not present between grid cover and barrier layer, there is smaller grid capacitance, improve the performance of semiconductor devices.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of T-type grid preparation method.
Background technology
There are many excellent characteristics with GaAs (GaAs), the compound semiconductor materials that gallium nitride (GaN) is representative,
Such as high critical breakdown electric field, high electron mobility, high two-dimensional electron gas and good high temperature operation capability.Based on chemical combination
The devices such as the high electron mobility transistor (HEMT) of object semiconductor, hetero-structure field effect transistor (HFET) have been obtained for
Extensive use especially needs high-power and high-frequency field to have a clear superiority in radio frequency, microwave etc..
In the manufacture craft of compound semiconductor RF power device, the making of gate electrode is the manufacture craft of key, T
The processing technology of type grid is even more the difficult point in difficult point；Currently, in the making of deep-submicron compound semiconductor device, it is general to use
The method of electron beam lithography and multilayer glue makes T-type grid.T-type grid refer to that mushroom-shaped T-shaped gate electrode is presented in cross sectional shape, in this way
The grid root that its underpart contacts semiconductor surface is very narrow, so as to improve device by frequency, and the grid cover on top is very wide, can
To reduce the resistance of grid.It, can be by the line width of grid most using the photoetching process of I line uv-exposures in actual process making
It is low to accomplish 0.35 microns, line width can be accomplished to 0.1 micron or less using electron beam lithography.But due to by equipment
Limitation, electron beam lithography, which makes T-type grid, can only carry out point by point scanning, therefore its processing efficiency is extremely low, and use I line ultraviolet lights
The T-type grid line for scribing work is wide and cannot meet device to linewidth requirements.
Invention content
Based on this, it is necessary to for the extremely low problem of the processing efficiency of Electron Beam Fabrication T-type grid, provide a kind of new T-type
Grid preparation method.
The present invention provides a kind of T-type grid preparation method, including：
Form barrier layer；
The first photoresist layer is formed on the barrier layer, and forms grid root groove in first photoresist layer, wherein
First photoresist layer is deep-UV lithography glue-line；
In the grid root groove and form metal layer on the deep-UV lithography glue-line；
The second photoresist layer is formed on the metal layer, and forms grid cover figure in second photoresist layer；
Etching is not by the metal layer of the grid cover figure covering part；
Remove the deep-UV lithography glue-line and grid cover figure.
Optionally, described to include the step of forming deep-UV lithography glue-line on the barrier layer：
One layer of deep ultraviolet light-sensitive lacquer for being used for 193 nanometer of -248 nano wave length photoetching is coated on the barrier layer, big
At a temperature of 90 degrees Celsius, the time of baking 60 seconds or more.
Optionally, described to include the step of the photoresist layer forms grid root groove：To the deep ultraviolet light-sensitive lacquer into
Then row exposure and baking are developed with generating chemical amplifying type light reaction in developing solution, deep ultraviolet light-sensitive lacquer is made to generate grid
Root groove.
Optionally, the metal layer includes multiple layer metal film.
Optionally, the thickness of the deep ultraviolet light-sensitive lacquer is 0.5 micron or more.
Optionally, described the step of removing the deep-UV lithography glue-line and grid cover figure, includes：By the deep ultraviolet light
Photoresist layer and the dissolving of grid cover figure are in a solvent.
Optionally, the barrier layer is any one or more material in AlGaAs, AlGaN, InGaP, ScAlN and InAlN
The superposition of material.
Optionally, second photoresist layer is i-line photoresists either g-line photoresists or deep-UV lithography
Glue.
Above-mentioned T-type grid preparation method can make the contact line width of T-type grid be less than 200 nanometers of T-type grid improved again simultaneously
Preparation efficiency.And since medium being not present between grid cover and barrier layer, there is smaller grid capacitance, improve semiconductor
The performance of device.
Description of the drawings
Fig. 1 be etc. the semiconductor devices of grid to be produced schematic diagram；
Fig. 2-Fig. 8 is the schematic diagram for indicating to prepare T-type grid according to some embodiments of the present invention.
Figure label：
1- substrates；2- buffer layers；3- barrier layers；4- source electrodes；5- drains；6- deep-UV lithography glue-lines；7- grid root grooves；8-
Metal layer；9- photoresist layers；10-T type grid.
Specific implementation mode
T-type grid preparation method proposed by the present invention is described in further detail below in conjunction with the drawings and specific embodiments.
According to following explanation and claims, advantages and features of the invention will become apparent from.It should be noted that attached drawing is all made of very
Simplified form and non-accurate ratio is used, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
A kind of compound semiconductor structure is schematically illustrated in Fig. 1.Including：Substrate 1, the substrate material include but
It is not limited to the materials such as sapphire, silicon carbide, silicon, diamond, GaAs, gallium nitride and aluminium nitride.The thickness of the substrate 1 is 50
To 1000 microns.Buffer layer 2 can be formed on the substrate 1, the path for providing electric current flowing.The buffer layer 2 can be with
For GaAs, one or more combinations of materials such as GaN, InP, InN, AlN, InGaAs or InGaN.The thickness of the buffer layer 2
It is 50 to 10000 nanometers.Can form barrier layer 3 on the buffer layer 2, the barrier layer 3 can be AlGaAs, AlGaN,
The one or more superposition of the alloy materials such as InGaP, ScAlN, InAlN.The thickness of the barrier layer 3 is 3 to 100 nanometers.
After above-mentioned material has been grown, it is usually initially formed Ohm contact electrode, i.e. source electrode 4 and drain electrode 5.The source electrode 4
It is located on the buffer layer 2 of 3 both sides of the barrier layer with drain electrode 5.Region between the source electrode 4 and drain electrode 5 can be with
Referred to as raceway groove, after source electrode 4 and drain electrode 5 are applied in voltage, carrier is moved to drain electrode 5 from source electrode 4.The source electrode 4 and drain electrode 5
It can be the alloy of arbitrary a variety of compositions in the metals such as titanium, aluminium, nickel, gold, platinum.After the source electrode 4 and drain electrode 5 are formed, under
One step then needs to be formed grid on the barrier layer 3 to control the flowing of carrier.And on the one hand, in order to improve semiconductor
The contact line width needs of the working frequency of device, the grid are small as far as possible；On the other hand, the resistance of grid and grid-source
Electrode capacitance must be more likely to low.Therefore very high requirement is proposed to grid formation process.
T-type grid preparation method provided by the present invention is specifically described below with reference to Fig. 2-Fig. 7.
Referring to FIG. 2, after forming structure as shown in Figure 1, deep-UV lithography glue-line 6 is formed on the barrier layer 3,
The deep-UV lithography glue-line 6 needs certain thickness to have the function that protect raceway groove, its usual thickness to be more than 0.5 micron.
The deep-UV lithography glue-line 6 covers the barrier layer 3, while can also cover the source electrode 4 and drain electrode 5.Specifically, can be with
One layer of deep ultraviolet light-sensitive lacquer for being used for 193 nanometer of -248 nano wave length photoetching is coated on the barrier layer 3, Celsius more than 90
At a temperature of degree, the time more than 60 seconds is toasted.It, can be in the deep ultraviolet in the case where 3 surface of the barrier layer is smooth
Anti-reflecting layer is coated in the upper surface or lower surface of photoresist layer, inhibits the reflection of ultraviolet light.
Referring to FIG. 3, the wafer to the spin coating deep ultraviolet light-sensitive lacquer 4 is exposed using deep ultraviolet stepper
With baking to generate chemical amplifying type light reaction, then develop in developing solution, deep ultraviolet light-sensitive lacquer 4 is made to generate grid root groove
7.Using suitable photoetching process condition, the width for the grid root groove 7 that the present invention is formed can be less than 200 nanometers, to
The line width for the grid root being subsequently formed can be made to be less than 200 nanometers.The developing solution can be tetramethyl aqua ammonia.
Referring to FIG. 4, forming metal layer 8 in the grid root groove 7 and on the deep-UV lithography glue-line 6.The gold
Belong to layer 8 to be made of multiple layer metal film, the metallic film can be NiAu, NiAl, PtAu etc..The metal layer 8 can be with
It is formed using physical gas-phase deposition.First choice deposition is relatively thin metallic film, and thickness is about 10-100 nanometers, and can be with
Good Schottky contacts are formed with barrier layer 3.Then thicker metallic film is deposited, to improve the conductivity of grid.It is described
The metal filled in grid root groove 7 forms the grid root of T-type grid.The grid root can be less than with the contact line width of potential barrier layer by layer
200 nanometers.
Referring to FIG. 5, spin coating forms the second photoresist layer 9 above the metal layer 8, second photoresist layer 9 covers
Cover the metal layer 8.Second photoresist layer 9 can be deep ultraviolet, i-line g-line type photoresists.
Referring to FIG. 6, carrying out photoetching process to second photoresist layer 9, grid cover is formed on second photoresist 9
Figure retains the part photoresist layer that grid root groove 7 corresponds to top, the grid cover figure is with the grid root groove in vertical side
It overlaps upwards.
Referring to FIG. 7, to not performed etching by the metal layer 8 that the second photoresist layer 9 covers, remove not by the second photoresist
The metal layer 8 of 9 covering of layer, to form grid cover.The grid cover and grid root constitute T-type grid 10.The etching can be plasma
Dry etching, the process conditions of the dry plasma etch depend on the material category of the metal layer, can be from pure physics
Ise variation is reactive chemical etching, also needs to carry out wet etching in some cases to remove specific metal foil
Layer.
Referring to FIG. 8, removing 6 and second photoresist layer 9 of remaining deep-UV lithography glue-line.It can be by remaining photoresist
Solvent dissolving removal is used in the case of a high temperature, and T-type grid 10 are finally only retained on the barrier layer 3.
Above-described embodiment on semiconductor devices shown in Fig. 1 for forming T-type grid, it is to be understood that this field skill
Art personnel form T-type grid also in the protection domain of the application on other semiconductor devices, using method provided by the present invention
Within.Method provided by the invention is suitable for any GaAs, gallium nitride, indium phosphide and corresponding ternary or quaternary chemical combination
Object semiconductor material systems.
The efficiency of T-type grid is prepared using this method can reach 100 wafers per hour and (have on wafer and multiple contain
Have the chip of T-type grid structure), and the wafer that traditional e-beam lithography prepares a same structure needs nearly one day
Time.Therefore, preparation method provided by the present invention is less than 200 nanometers in the contact line width that can make T-type grid and improves again simultaneously
T-type grid preparation efficiency.And since medium being not present between grid cover and barrier layer, there is smaller grid capacitance, improve
The performance of semiconductor devices.
Each technical characteristic of embodiment described above can be combined arbitrarily, to keep description succinct, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, it is all considered to be the range of this specification record.
Several embodiments of the invention above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to the protection of the present invention
Range.Therefore, the protection domain of patent of the present invention should be determined by the appended claims.
Claims (8)
1. a kind of T-type grid preparation method, which is characterized in that including：
Form barrier layer；
The first photoresist layer is formed on the barrier layer, and forms grid root groove in first photoresist layer, wherein described
First photoresist layer is deep-UV lithography glue-line；
In the grid root groove and form metal layer on the deep-UV lithography glue-line；
The second photoresist layer is formed on the metal layer, and forms grid cover figure in second photoresist layer；
Etching is not by the metal layer of the grid cover figure covering part；
Remove the deep-UV lithography glue-line and grid cover figure.
2. T-type grid preparation method according to claim 1, which is characterized in that form deep ultraviolet light on the barrier layer
The step of photoresist layer include：
One layer of deep ultraviolet light-sensitive lacquer for being used for 193 nanometer of -248 nano wave length photoetching is coated on the barrier layer, more than 90
At a temperature of degree Celsius, the time of baking 60 seconds or more.
3. T-type grid preparation method according to claim 1, which is characterized in that form grid root in first photoresist layer
The step of groove includes：The deep ultraviolet light-sensitive lacquer is exposed and is toasted to generate chemical amplifying type light reaction, then existed
Develop in developing solution, deep ultraviolet light-sensitive lacquer is made to generate grid root groove.
4. T-type grid preparation method according to claim 1, which is characterized in that the metal layer includes multiple layer metal
Film.
5. T-type grid preparation method according to claim 1, which is characterized in that the thickness of the deep-UV lithography glue-line is big
In 0.5 micron.
6. T-type grid preparation method according to claim 1, which is characterized in that the removal deep-UV lithography glue-line
Include with the step of grid cover figure：In a solvent by the deep-UV lithography glue-line and the dissolving of grid cover figure.
7. T-type grid preparation method according to claim 1, which is characterized in that the barrier layer be AlGaAs, AlGaN,
The superposition of any one or more material in InGaP, ScAlN and InAlN.
8. T-type grid preparation method according to claim 1, which is characterized in that second photoresist layer is i-line light
Photoresist either g-line photoresists or deep ultraviolet light-sensitive lacquer.
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| CN201810519181.7A CN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810519181.7A CN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
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| CN108807162A true CN108807162A (en) | 2018-11-13 |
Family
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| CN201810519181.7A Pending CN108807162A (en) | 2018-05-28 | 2018-05-28 | T-type grid preparation method |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110571143A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | Manufacturing method of novel high-frequency semiconductor grid |
| CN110571145A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | preparation method of floating Y-shaped grid |
| CN110571144A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | manufacturing method of novel semiconductor grid |
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Cited By (3)
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|---|---|---|---|---|
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| CN110571145A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | preparation method of floating Y-shaped grid |
| CN110571144A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | manufacturing method of novel semiconductor grid |
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