CN105467533A - 具有磁场抵消的光电子封装件 - Google Patents

具有磁场抵消的光电子封装件 Download PDF

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CN105467533A
CN105467533A CN201510624188.1A CN201510624188A CN105467533A CN 105467533 A CN105467533 A CN 105467533A CN 201510624188 A CN201510624188 A CN 201510624188A CN 105467533 A CN105467533 A CN 105467533A
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trace
mould
die
top surface
sealed
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CN105467533B (zh
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R·帕萨
W·弗兰茨
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

本申请公开一种层叠光电子封装设备(100),其包括具有顶表面的底模(251),该顶表面包括底部电迹线(356、359、361、358)和耦合到至少一个底部电迹线的光源模(180)。第一腔模(252)位于底模上。光学器件模(321a)位于第一腔模上且第二腔模(328)位于光学器件模上。安装基板(351)位于包括顶部电迹线(378、379)的第二腔模(328)上。光电探测器模(110)光学地耦合以便从光源接收光。底部和顶部电迹线均大致对称地定位在镜平面(105)的侧面上,使得当传导相等且相反的电流时,源于第一侧的第一磁场以及源于第二侧的第二磁场彼此抵消,以在光学器件模上的一个或多个模位置处提供超过50%的磁通密度减少。

Description

具有磁场抵消的光电子封装件
相关申请的交叉引用
本申请要求于2014年9月26日提交的题为“Microfabricatedatomicclocks(MFAC)&magnetometers(MFAM):highvolumemanufactural(HVM)magneticcharacterization(微加工原子钟(MFAC)和磁力计(MFAM):大体积制造(HVM)磁特征)”的美国临时专利申请序列号62/055,827的权益,其通过引用全部并入本文。
技术领域
所公开的实施例涉及层叠光电子封装件,其实现光泵浦传感器或基准件,诸如MFAC和MFAM。
背景技术
多种光电子设备为封装设备,其包括光电探测器(PD)以及在真空下操作的至少一个光源。常规MFAC和MFAM封装件包括在封装材料内部垂直层叠的结构,其包括作为具有电迹线的支撑件的底模/底部管芯(bottomdie)以及安装于其上的至少一个光源模(die)(例如,激光器模诸如垂直腔表面发射激光器(VCSEL)),在光源上方提供腔室的在底模上的第一腔模,以及在第一腔模上的光学器件模。
在底模上的电迹线连接驱动所述光源的外部驱动器,并且包括被配置用作电阻式加热器元件的迹线,诸如提供热量以将光源模加热到大约60℃到80℃的温度。第二腔模位于光学器件模上,其他光学设备(例如,偏光器)位于第二腔模上,并且光电探测器(PD)模位于其他光学设备上方的介电基板上。该封装件为真空密封的封装件。
发明内容
本发明内容被提供用于以简化形式介绍下面在包括所提供的附图的具体实施方式中进一步描述的所公开的概念的简要选择。本发明内容不旨在限制要求保护的主题的范围。
一种层叠光电子封装件包括底模/底部管芯(bottomdie)和光源模,其中底模具有包括底部电迹线的顶表面,并且光源模耦合到至少一个底部电迹线。第一腔模在底模上。光学器件模在第一腔模上并且第二腔模在光学器件模上。第二安装基板在第二腔模上并且在其上包括顶部电迹线。光电探测器模被光学地耦合以便从光源接收光。底部和顶部电迹线在XZ镜平面的侧面上均大致对称地定位在XY平面表面上,以便当相反地偏置时传导相等且相反的电流,以使源于第一侧的第一磁场和源于第二侧的第二磁场在Z方向上彼此抵消,从而在光学器件模上的一个或多个模位置处提供超过50%的磁通密度减少。
附图说明
现在将参考附图,这些附图不必按比例绘制,其中:
图1A为根据示例实施例的示例层叠光电子封装设备的横截面图,所述层叠光电子封装设备在封装件中的光学器件模上方的第二安装基板和下方的底模的镜平面的相对侧上具有至少大致对称的电迹线布置,使得当这些迹线被相反地偏置时,它们在镜平面的各个侧上传导相等且相反的电流,以提供光学器件模的磁场抵消并因此提供噪音消减。
图1B为根据示例实施例的示例层叠光电子封装设备连同键合线的横截面图,所述层叠光电子封装设备在包括多个层级的两个不同迹线上具有大致对称的电迹线布置,使得当被相反地偏置以传导相等且相反的电流时,二者提供磁场抵消,并且键合线被示出用于使第二安装基板上的电迹线与每侧的底模上的电迹线短路。
图2为根据示例实施例的示例模的描绘,所述示例模在至少一个模的表面上具有大致对称布置的第一和第二电迹线,使得当被相反地偏置以传导相同且相反的电流时,在Z方向上提供磁场抵消。
图3为根据示例实施例的示例封装层叠光电子设备,其在模的表面上包括所公开的大致对称布置的第一和第二电迹线,使得当被相反地偏置以传导相等且相反的电流时,在Z方向上提供磁场抵消。
具体实施方式
参考附图描述示例实施例,其中相同的符图标记用于指示类似或等效的元件。由于一些动作或事件可以以不同的顺序发生以及/或者与其他动作或事件同时发生,因此所示出的动作或事件的顺序不应被理解为是限制性的。此外,实施根据本公开的方法可能不需要一些示出的动作或事件。
对于层叠光电子封装件诸如微加工原子钟(MFAC)和磁力计(MFAM)以及运动传感器设备,在操作期间,在光源的加热器和驱动器以及在光源上方通常容纳碱金属蒸汽的上部腔室的加热器的电迹线中流动的电流被认识到导致磁场感应的噪音(电磁干扰,EMI),其可显著地降低设备的性能诸如灵敏度。所公开的实施例包括使得在包括沿光学器件模表面的Z(高度)方向上引入的磁场最小化的光电子封装件,该最小化由封装件中的光学器件模上方的模/基板和下方的模/基板的镜平面的相对侧上的电迹线的至少大致对称布置来提供。当被相反地偏置时,在镜平面的相应侧上提供相等且相反的电流,已认识到该布局在光学器件模上提供磁场抵消并因此提供噪音消减。
图1A为根据示例实施例的示例层叠光电子封装设备(封装设备)100的横截面图,所述层叠光电子封装设备100在封装件中的光学器件模321a上方的第二安装基板351和下方的底模251两者的XZ镜平面(镜平面)105的相对侧上具有至少大致对称布置的电迹线,使得当被相反地偏置时,传导相等且相反的电流以提供光学器件模321a的磁场抵消并因此提供噪音消减。尽管在图1A和图1B中未示出,每个电迹线包括通常在模或基板的周边(边缘)上的键合焊盘,以允许与其进行电连接(参见以下所描述的图2)。迹线通常包括金属或金属合金,诸如铝或铂。
当在XY平面上的电流传导迹线上方或下方的Z方向上移动距离(z)时,已知的是磁场强度下降为1/z。所公开的实施例认识到,当XY平面上的电迹线相对于镜平面(诸如镜平面105)的两侧大致对称地定位,并且被相反地偏置以使得镜平面的一侧上的电迹线的电流相对于流过镜平面的另一侧上的电迹线的电流以相等的幅值和相反的方向流动,由于源于相应侧的磁场的磁场抵消,因此在相应电迹线之间的XY平面上方或下方的Z方向上的距离z处的磁通密度可以被很大程度地抵消(并因此减小)。
封装设备100包括封装件内的多个层叠部件,所述封装件包括封装材料,其具有为封装件提供侧壁和底壁的封装主体171以及用于密封封装件的顶部的盖子174。多个层叠部件包括在封装件的底壁上的底模/管芯(die)251,该底模具有顶表面,该顶表面包括多个底部电迹线,所述多个底部电迹线被显示为驱动器迹线359和361以及每个实施电阻式加热元件的加热器迹线356和358,并且还包括耦合到驱动器迹线359和361的用于发射光的光源模/管芯(die)180,所述驱动器迹线359和361分别通过键合线181和182向光源模180的电极提供电偏置。以下描述的图2中示出示例加热器迹线布局。
具有顶表面和底表面的第一腔模252位于底模251的顶表面上。光学器件模321a位于第一腔模252的顶表面上,并且光学透明的密封件或模片材(密封模,用于腔密封)321b位于光学器件模321a上。第二腔模328位于密封模321b上。
第二安装基板351具有包括多个顶部电迹线的顶表面,所述多个顶部电迹线被显示为每个实施电阻式加热元件的加热器迹线378和379。光电探测器(PD)模110被光学地耦合以便接收源自光源180的光,其在图1A中被显示为处于视线位置。
镜平面105在图1A中被显示为正交于全部沿XY平面取向的封装设备100的各种模来取向。驱动器迹线359、加热器迹线356和加热器迹线378全部被显示为在镜平面105的第一侧上,而驱动器迹线361、加热器迹线358和加热器迹线379全部在镜平面105的第二侧上。因此,当被电源相反地偏置以在驱动器迹线359和361、加热器迹线356和358以及加热器迹线378和379中传导相等且相反的电流时,源于镜平面105的第一侧的第一磁场以及源于镜平面105的第二侧的第二磁场彼此抵消,以便在光学器件模321a上的一个或多个模位置处提供超过50%的磁通密度减少。
例如,假设在光学器件模的中心处的操作期间,源于第一侧的第一磁通密度B为x牛-米每安培(Nm/A)或特斯拉(T),并且源于第二侧的第二磁通密度B为0.9xT。50%的磁通密度减少意味着光学器件模的中心处的净余B小于0.5T。如上所述,磁场抵消为光学器件模321a提供噪音消减,从而导致封装设备100的改善性能。
图1B为根据示例实施例的示例层叠光电子封装设备160的横截面图,所述层叠光电子封装设备160在封装件中的光学器件模321a上方的第二安装基板351以及下方的底模251两者的镜平面105的相对侧上具有至少大致对称布置的电迹线,使得当在镜平面105的相应侧面上被相反地偏置时,为光学器件模321a提供磁场抵消并因此提供噪音消减。电迹线136在第二安装基板351的第一侧上且电迹线137在第二安装基板351的第二侧上,并且电迹线359和加热器迹线356在底模251的第一侧上,而电迹线361和加热器迹线358在底模251的第二侧上。
由于电迹线136、137可以为加热元件提供布线(routing),所述布线还使得能够在DC加热信号的顶上添加RF信号,以便在需要将第二腔模328放置在已知磁场内的诸如MFAC的应用中生成内部磁场,因此它们被标记为“加热器+驱动器”。电迹线359和361为分离的迹线,用于将光源180从外部驱动器源偏置到光源180的键合焊盘。
键合线196和197被包括在内以使得底模251上的加热器迹线356与第二安装基板351上的电迹线136之间短路,并使得底模251上的加热器迹线358与第二安装基板351上的电迹线137之间短路。键合线196和197还提供围绕设备的基本上完整的回路,以便通过单一的一对偏置信号抵消第二腔中的磁场,并且如上所述在需要的情况下还可选择地通过所施加的RF偏置向电迹线136、137施加RF信号。该布局可以与具有用于顶部和底部加热元件的电隔离的分离迹线的已知方法进行比较。
图2是根据示例实施例的示例模200的图示,所述示例模200包括基板205,该基板205在镜平面105的相对的第一侧和第二侧上具有大致对称布置的电迹线的简化示例,使得当被相反地偏置以在镜平面105的相应侧面上提供相同且相反的电流时,在上方或下方的Z方向上提供磁场抵消。如图所示,在第一侧上存在电迹线211、212和213以及键合焊盘216和217,并且在第二侧上存在电迹线221、222和223以及键合焊盘226和227。电迹线211、212和213以及电迹线221、222和223可被看作是彼此关于镜平面105的镜像。电迹线211、212和213可以提供第一加热元件,并且电迹线221、222和223可以提供第二加热元件,诸如用于在第二安装基板351上提供加热器迹线378和379,如图1A所示。
键合焊盘216和227在图2中被标注为高(H)压键合焊盘,而键合焊盘217和226被标注为低(L)压键合焊盘。例如,向作为接地的键合焊盘216和227以及键合焊盘217和226施加5V电压可以用于加热,同时在电迹线211、212和213以及电迹线221、222和223之间的区域中提供基板205上方或下方的Z方向上的磁场抵消。
各个迹线的宽度在图2中被显示为随着更加靠近模200的中心而减小,其中迹线213宽于迹线211和212,并且迹线223宽于迹线221和222。这种布置导致更少的电流流过靠近模的中心的迹线,从而导致产生更少的磁场并因此在第二腔模328的中间生成更少的噪音。
图3是根据示例实施例的示例封装层叠光电子设备(封装光电子设备)300,其在封装件中的至少一个模的表面上包括所公开的大致对称布置的第一和第二电迹线,使得当被相反地偏置以传导相等且相反的电流时,在Z方向上提供磁场抵消。已封装的光电子设备300包括在底模251上的第一腔模252,所述底模251在其顶表面上具有带有关联键合焊盘155和159的电迹线359以及带有关联键合焊盘156和158的电迹线361。尽管未示出,但在底模251上可以存在类似于图1A中所示的加热器迹线356和358的一对对称布置的加热器迹线。第二安装基板351包括由被显示为357的金属迹线耦合在一起的键合焊盘352和353,以及由所示出的金属迹线358耦合在一起的键合焊盘354和355。电迹线359和361在镜平面105的相应侧面上大致对称地定位,电迹线357和358同样如此。
已封装的光电子封装件300被显示为包括在外封装件(OP)170内部的内封装件350。内封装件350具有与面向封装件的底壁的其基底部分相反的开放顶部。
PD模110包括第一接触件,该第一接触件包括通过包括内部键合线115的布线连接到第一外部键合焊盘(FEBP)111的前接触件110a。PD模110还包括第二接触件,该第二接触件包括通过包括后侧金属层102的布线连接到第二外部键合焊盘(SEBP)112的后接触件110b。
所示出的内封装件350包括多层第一介电基板,其包括第一介电层级101以及在第一介电层级101上方的第二介电层级106。如本领域所知,多层第一介电基板可以是整体的(单片式)基板,使得在不需要任何粘合剂的情况下配置第一介电层级101和第二介电层级106以及任何介于中间的金属层。例如,陶瓷封装件具有内建层,其允许整合的金属连接件侧向地和垂直地到达封装件的外表面。
第一介电层级101包括顶侧,该顶侧包括在其上具有后侧金属层102的第一模附连区,所述后侧金属层102延伸到内封装件350的第一外部边缘,并且FEBP111和SEBP112在第一介电层级101的底侧的一部分上方延伸。第二介电层级106在第一介电层级101上方划定(framing)包括线键合区的模附连区,所述线键合区具有延伸到内封装件350的第二外部边缘的第二金属层119。
前接触件110a可以包括连接到n+区域的键合焊盘金属,并且后接触件110b可以包括连接到p+区域的键合焊盘金属。后接触件110b可以是PD模110的整个底侧。内部键合线115将前接触件110a连接到第二金属层119。
PD模110可以包括任何合适的前侧照明PD,其包括光电二极管、光电晶体管或电荷耦合设备(CCD),其全都可以是现成的(off-the-shelf)PD模。在一个实施例中,PD模110包括具有第一导电性(例如,n+)的第一有源层、具有与第一导电性相反的第二导电性(例如,P+)的第二有源层以及分离第一和第二有源层(以形成PIN二极管)的本征层。
内封装件350位于第二安装基板351上。键合线161a将FEBP111连接到键合焊盘353,并且键合线161b将键合焊盘352连接到上部线键合区177a。键合线162a将SEBP112连接到键合焊盘354,而键合线162b将键合焊盘355连接到上部线键合区177b。
被显示为键合线161a和键合线161b的第一键合线一起将FEBP111连接到与OP170的第一端子191连接的线键合区177a,并且第二键合线162a和162b一起将SEBP112连接到与OP170的第二端子192连接的线键合区177b,第三键合线165将金属迹线359的末端处的键合焊盘155连接到下键合焊盘176a,其通过金属迹线359以及键合焊盘159与第一电极181之间的键合线将第一电极181连接到OP170的第三端子193,并且从键合焊盘158到下键合焊盘176b的第四键合线166通过从金属迹线361的末端处的键合焊盘156的线键合将第二电极182连接到OP170的第三端子194。盖子174气密地密封OP170。
已封装的光电子封装件300包括具有电极181和182的光源模180,以允许通过来自(连接到第三端子193的)下键合焊盘区域176a的第三键合线165以及通过来自(连接到第三端子194的)下键合焊盘区域176b的第四键合线166提供的图3所示的偏置(例如,电泵浦)。在一个特定实施例中,光源模180可以包括VCSEL。光学器件模321a上的光学透明密封件或模片材(密封模)321b被显示为在第一腔模252和第二腔模328之间。密封模321b可以包括密封由第二腔模328限定的上部腔体的下端的光学玻璃,所述第二腔模328由第二安装基板351在上端上密封。光学器件模321a可以包括滤光器或偏光器。第二安装基板351包括光学玻璃,诸如硼硅酸盐玻璃,例如BOROFLOAT33。
经晶片/管芯级处理的所公开实施例提供低成本、高产量制造,并且凭借所公开的大致对称布置的电迹线为封装的光电子设备提供低噪音性能。所公开的实施例的应用通常包括具有光源诸如激光二极管以及内置的监测器光电探测器的所有应用。一个具体示例是磁力计物理封装。其他示例包括原子钟和运动传感器设备。
所公开的实施例可以被整合成多个装配流,以形成多种不同的光电子设备和相关产品。本公开所涉及的领域的技术人员将理解在所要求保护的发明的范围内,许多其他实施例和实施例的变型是可能的,并且可以在不脱离本公开的范围的情况下对所描述的实施例作出替换和修改。

Claims (14)

1.一种层叠光电子封装设备(封装设备),其包括:
在包括封装材料的封装件内的多个层叠部件,所述封装材料具有为所述封装件提供侧壁和底壁的封装主体,以及用于密封所述封装件的顶部的盖子,所述多个层叠部件包括:
具有顶表面的在所述底壁上的底模,所述顶表面包括多个底部电迹线以及耦合到所述多个底部电迹线中的至少一个的用于发射光的光源模;
在所述底模的所述顶表面上的第一腔模,其具有顶表面和底表面;
在所述第一腔模的所述顶表面上的至少一个光学器件模;
在所述光学器件模上的第二腔模;
在所述第二腔模上的第二安装基板,其具有包括多个顶部电迹线的顶表面;以及
光电探测器模即PD模,其被光学地耦合以便接收源自所述光源模的所述光,
其中所述多个底部电迹线和所述多个顶部电迹线均分别大致对称地定位在底部镜平面和顶部镜平面的第一侧和第二侧上,因此当传导相等且相反的电流时,源于所述第一侧的第一磁场以及源于所述第二侧的第二磁场彼此抵消,以在所述光学器件模上的一个或多个模位置处提供超过50%的磁通密度减少。
2.根据权利要求1所述的封装设备,其中所述多个底部电迹线提供关于所述底部镜平面的镜像,并且所述多个顶部电迹线提供关于所述顶部镜平面的镜像。
3.根据权利要求1所述的封装设备,其中所述光学器件模包括偏光器。
4.根据权利要求1所述的封装设备,其中所述多个底部电迹线在所述第一侧上提供第一加热器迹线和分离的第一驱动器迹线,并在所述第二侧上提供第二驱动器迹线和分离的第二加热器迹线。
5.根据权利要求4所述的封装设备,其进一步包括:第一键合线,其将所述第一加热器迹线短接到所述第一侧上的所述多个顶部电迹线中的第一个;以及第二键合线,其将所述第二加热器迹线短接到所述第二侧上的所述多个顶部电迹线中的第二个。
6.根据权利要求1所述的封装设备,其中所述第一腔模包括玻璃。
7.根据权利要求1所述的封装设备,其中所述第一腔模包括硅。
8.根据权利要求1所述的封装设备,其中所述PD模安装在所述封装件内部的内封装件的基底部分上,其中所述内封装件具有与面向所述封装件的所述底壁的所述基底部分相反的开放顶部。
9.一种方法,其包括:
提供包括多个层叠部件的层叠光电子封装设备(封装设备),所述多个层叠部件包括在底壁上具有顶表面的底模,所述顶表面包括多个底部电迹线以及耦合到所述多个底部电迹线中的至少一个的用于发射光的光源模,在所述底模的所述顶表面上具有顶表面和底表面的第一腔模,在所述第一腔模的所述顶表面上的光学器件模,在所述光学器件模上的第二腔模,在所述第二腔模上具有包括多个顶部电迹线的顶表面的第二安装基板,以及被光学地耦合以便接收源自所述光源模的所述光的光电探测器模即PD模,其中所述多个底部电迹线和所述多个顶部电迹线均分别大致对称地定位在底部镜平面和顶部镜平面的第一侧和第二侧上,以及
相反地偏置所述多个底部电迹线以便传导沿相反方向在所述第一侧和所述第二侧上流动的相应电流,以及相反地偏置所述第一侧和所述第二侧上的所述多个顶部电迹线以便传导沿相反方向流动的所述相应电流,
其中所述多个底部电迹线和所述多个顶部电迹线两者的源于所述第一侧的第一磁场以及源于所述第二侧的第二磁场在所述光学器件模上的一个或多个模位置处彼此抵消,以在所述模位置处提供超过50%的磁通密度减少。
10.根据权利要求9所述的方法,其中所述多个底部电迹线提供关于所述底部镜平面的镜像,并且所述多个顶部电迹线提供关于所述顶部镜平面的镜像。
11.根据权利要求9所述的方法,其中所述光学器件模包括偏光器。
12.根据权利要求9所述的方法,其中所述多个底部电迹线在所述第一侧上提供第一加热器迹线和分离的第一驱动器迹线,并在所述第二侧上提供第二驱动器迹线和分离的第二加热器迹线,并且其中所述第一加热器迹线与所述第一侧上的所述多个顶部电迹线中的第一个短接,以及所述第二加热器迹线与所述第二侧上的所述多个顶部电迹线中的第二个短接。
13.根据权利要求12所述的方法,其中所述相反地偏置包括施加DC信号和在所述DC信号的顶部上的RF信号以及独立的偏置信号,所述DC信号和所述RF信号相对于所述第二加热器迹线和所述多个顶部电迹线中的所述第二个被施加到所述第一加热器迹线和所述多个顶部电迹线中的所述第一个,并且所述偏置信号被施加在所述第一驱动器迹线和所述第二驱动器迹线之间。
14.根据权利要求9所述的方法,其中所述PD模安装在所述封装设备内部的内封装件的基底部分上,所述内封装件具有与面向所述封装件的所述底壁的所述基底部分相反的开放顶部。
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