CN105453265B - 具有深沟槽隔离结构的方法及半导体结构 - Google Patents
具有深沟槽隔离结构的方法及半导体结构 Download PDFInfo
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- CN105453265B CN105453265B CN201480040611.7A CN201480040611A CN105453265B CN 105453265 B CN105453265 B CN 105453265B CN 201480040611 A CN201480040611 A CN 201480040611A CN 105453265 B CN105453265 B CN 105453265B
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- isolation structure
- epitaxial layer
- deep trench
- trench isolation
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/603—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0151—Manufacturing their isolation regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
- H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
- H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/351—Substrate regions of field-effect devices
- H10D62/357—Substrate regions of field-effect devices of FETs
- H10D62/364—Substrate regions of field-effect devices of FETs of IGFETs
- H10D62/371—Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/944,864 | 2013-07-17 | ||
| US13/944,864 US9076863B2 (en) | 2013-07-17 | 2013-07-17 | Semiconductor structure with a doped region between two deep trench isolation structures |
| PCT/US2014/046955 WO2015009891A1 (en) | 2013-07-17 | 2014-07-17 | Method and semiconductor structure with deep trench isolation structures |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105453265A CN105453265A (zh) | 2016-03-30 |
| CN105453265B true CN105453265B (zh) | 2019-06-04 |
Family
ID=52342890
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201480040611.7A Active CN105453265B (zh) | 2013-07-17 | 2014-07-17 | 具有深沟槽隔离结构的方法及半导体结构 |
Country Status (5)
| Country | Link |
|---|---|
| US (2) | US9076863B2 (enExample) |
| EP (1) | EP3022770B1 (enExample) |
| JP (1) | JP6713708B2 (enExample) |
| CN (1) | CN105453265B (enExample) |
| WO (1) | WO2015009891A1 (enExample) |
Families Citing this family (24)
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| US7676228B2 (en) | 2005-09-19 | 2010-03-09 | Plant Equipment Inc. | Radio interoperability system and method |
| US9525060B2 (en) * | 2013-12-17 | 2016-12-20 | Texas Instruments Incorporated | Reduced area power devices using deep trench isolation |
| US9929140B2 (en) | 2014-05-22 | 2018-03-27 | Texas Instruments Incorporated | Isolation structure for IC with EPI regions sharing the same tank |
| US9543299B1 (en) * | 2015-09-22 | 2017-01-10 | Texas Instruments Incorporated | P-N bimodal conduction resurf LDMOS |
| EP3151283A1 (en) * | 2015-09-29 | 2017-04-05 | Nexperia B.V. | Vertical dmos bjt semiconductor device |
| CN106057656A (zh) * | 2016-06-06 | 2016-10-26 | 中航(重庆)微电子有限公司 | 一种功率半导体器件的制备方法 |
| CN107482003B (zh) * | 2016-06-08 | 2020-03-13 | 中芯国际集成电路制造(上海)有限公司 | 晶体管的版图结构、晶体管及其制造方法 |
| KR102140358B1 (ko) * | 2016-12-23 | 2020-08-03 | 매그나칩 반도체 유한회사 | 잡음 감소를 위한 분리 구조를 갖는 통합 반도체 소자 |
| US10510776B2 (en) * | 2018-03-29 | 2019-12-17 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device with common active area and method for manufacturing the same |
| US10461182B1 (en) | 2018-06-28 | 2019-10-29 | Texas Instruments Incorporated | Drain centered LDMOS transistor with integrated dummy patterns |
| US11374124B2 (en) | 2018-06-28 | 2022-06-28 | Texas Instruments Incorporated | Protection of drain extended transistor field oxide |
| US11152505B2 (en) | 2018-06-28 | 2021-10-19 | Texas Instruments Incorporated | Drain extended transistor |
| CN109346466B (zh) * | 2018-08-17 | 2020-10-16 | 矽力杰半导体技术(杭州)有限公司 | 半导体结构和驱动芯片 |
| US20200194581A1 (en) * | 2018-12-18 | 2020-06-18 | Vanguard International Semiconductor Corporation | Semiconductor device and method for forming the same |
| WO2021102789A1 (en) * | 2019-11-28 | 2021-06-03 | Yangtze Memory Technologies Co., Ltd. | Local word line driver device, memory device, and fabrication method thereof |
| US11031303B1 (en) * | 2020-01-15 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company Limited | Deep trench isolation structure and method of making the same |
| CN114068701B (zh) * | 2020-07-30 | 2024-03-19 | 中芯北方集成电路制造(北京)有限公司 | 半导体结构及其形成方法 |
| KR20220094866A (ko) * | 2020-12-29 | 2022-07-06 | 에스케이하이닉스 주식회사 | 이미지 센싱 장치 |
| US11855071B2 (en) * | 2021-04-28 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company Limited | BCD device layout area defined by a deep trench isolation structure and methods for forming the same |
| KR102633398B1 (ko) * | 2021-05-27 | 2024-02-06 | 에스케이키파운드리 주식회사 | 반도체 소자를 위한 딥 트렌치 마스크 레이아웃 설계 방법 |
| US11830944B2 (en) * | 2021-07-20 | 2023-11-28 | Renesas Electronics Corporation | Semiconductor device and method of manufacturing the same |
| US12474421B2 (en) | 2021-08-13 | 2025-11-18 | Texas Instruments Incorporated | Hall effect sensor with reduced JFET effect |
| US11996441B2 (en) | 2021-12-10 | 2024-05-28 | Globalfoundries Singapore Pte. Ltd. | Semiconductor device for high voltage applications |
| CN114503264B (zh) * | 2022-01-04 | 2025-11-07 | 长江存储科技有限责任公司 | 半导体器件、存储器器件及其形成方法 |
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| CN1698208A (zh) * | 2002-08-14 | 2005-11-16 | 先进模拟科技公司 | 具有槽限制的隔离扩散的互补模拟双极型晶体管 |
| EP1868239A1 (en) * | 2006-06-12 | 2007-12-19 | Austriamicrosystems AG | Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body |
| CN101266930A (zh) * | 2008-04-11 | 2008-09-17 | 北京大学 | 一种横向双扩散场效应晶体管的制备方法 |
| CN101510551A (zh) * | 2009-03-30 | 2009-08-19 | 电子科技大学 | 等离子平板显示器驱动芯片用高压器件 |
| CN102136494A (zh) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | 高压隔离型ldnmos及其制造方法 |
| CN102237357A (zh) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | 一种集成电路装置及其制造方法 |
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2013
- 2013-07-17 US US13/944,864 patent/US9076863B2/en active Active
-
2014
- 2014-07-17 CN CN201480040611.7A patent/CN105453265B/zh active Active
- 2014-07-17 JP JP2016527088A patent/JP6713708B2/ja active Active
- 2014-07-17 WO PCT/US2014/046955 patent/WO2015009891A1/en not_active Ceased
- 2014-07-17 EP EP14825887.4A patent/EP3022770B1/en active Active
-
2015
- 2015-06-04 US US14/730,748 patent/US9608105B2/en active Active
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| CN1698208A (zh) * | 2002-08-14 | 2005-11-16 | 先进模拟科技公司 | 具有槽限制的隔离扩散的互补模拟双极型晶体管 |
| EP1868239A1 (en) * | 2006-06-12 | 2007-12-19 | Austriamicrosystems AG | Semiconductor device with a trench isolation and method of manufacturing trenches in a semiconductor body |
| CN101266930A (zh) * | 2008-04-11 | 2008-09-17 | 北京大学 | 一种横向双扩散场效应晶体管的制备方法 |
| CN101510551A (zh) * | 2009-03-30 | 2009-08-19 | 电子科技大学 | 等离子平板显示器驱动芯片用高压器件 |
| CN102136494A (zh) * | 2010-01-21 | 2011-07-27 | 上海华虹Nec电子有限公司 | 高压隔离型ldnmos及其制造方法 |
| CN102237357A (zh) * | 2010-04-23 | 2011-11-09 | 台湾积体电路制造股份有限公司 | 一种集成电路装置及其制造方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| EP3022770A4 (en) | 2017-05-17 |
| WO2015009891A1 (en) | 2015-01-22 |
| US20150270391A1 (en) | 2015-09-24 |
| US20150021687A1 (en) | 2015-01-22 |
| CN105453265A (zh) | 2016-03-30 |
| US9076863B2 (en) | 2015-07-07 |
| EP3022770A1 (en) | 2016-05-25 |
| JP6713708B2 (ja) | 2020-06-24 |
| EP3022770B1 (en) | 2021-10-27 |
| US9608105B2 (en) | 2017-03-28 |
| JP2016528730A (ja) | 2016-09-15 |
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