CN105448966B - 场效应功率晶体管的金属化结构 - Google Patents

场效应功率晶体管的金属化结构 Download PDF

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CN105448966B
CN105448966B CN201510596082.5A CN201510596082A CN105448966B CN 105448966 B CN105448966 B CN 105448966B CN 201510596082 A CN201510596082 A CN 201510596082A CN 105448966 B CN105448966 B CN 105448966B
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metallization structure
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G·普雷科托
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Infineon Technologies Austria AG
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Abstract

涉及一种基于在绝缘衬底(5)或本征的半导体衬底上的横向半导体层(3,4)的场效应功率晶体管(1)的金属化结构。所述横向半导体层(3,4)具有不同的带间隔,使得在所述横向半导体层的半导体边界层(6)中能够形成二维电子气。在源极电极接触面(7)与漏极电极接触面(8)之间或在源极(S)与漏极(D)之间施加电压的情况下电流能够流过横向半导体边界层(6)。能够通过栅极电极接触面(9)借助于栅极电压控制在源极电极接触面(7)与漏极电极接触面(8)之间的通道区域中的电流强度。

Description

场效应功率晶体管的金属化结构
技术领域
本申请涉及一种基于在绝缘衬底或本征或掺杂半导体衬底上的横向半导体层场效应功率晶体管的金属化结构。所述横向半导体层如此具有不同的带间隔,使得在所述横向半导体层的半导体边界层中能够形成二维电子气,所述二维电子气在源极电极接触面与漏极电极接触面之间使电流在施加电压在源极电极金属化结构与漏极电极金属化结构之间的情况下基于二维电子气能够流过横向半导体边界层。在源极电极接触面与漏极电极接触面之间的通道区域中的电流强度通过栅极电极接触面借助于栅极电压和作用的场效应来控制。
背景技术
在源极电极接触面、漏极电极接触面和栅极电极接触面上施加多层金属化结构,其中最上的功率金属化结构仅仅在源极电极接触面和漏极电极接触面上是需要的,所述源极电极接触面和漏极电极接触面然而相互间隔并且齿形地相互啮合,而齿无需接触。相互啮合和相互间隔的齿也称为接触爪并且在常规场效应功率晶体管中具有矩形轮廓,其中栅极电极接触面的条形金属化结构在源极电极接触面的金属化结构之下并且通过绝缘层与之绝缘地布置。
具有矩形接触爪或齿的这样的金属化结构由文献US 7,550,821B2已知。延伸的接触爪的缺点在于,电流密度由接触爪底直至接触爪尖减小,从而在接触爪底的区域中的宽度限制源极电极接触面和漏极电极接触面的金属化结构的最大电流密度,而矩形接触爪尖的宽度是超尺寸的。
US 7,550,821 B2,JP 2 602 360 B2,US 2012/0 012 945 A1以及JP H02 102546 A分别公开了金属化结构。
发明内容
本发明基本目的在于,实现一种场效应功率晶体管的金属化结构,该金属化结构利用半导体芯片的表面,使得功率金属化结构直至源极电极和漏极电极的金属化结构的接触爪尖在避免电子迁移的情况下允许改善的电流密度分布。
该目的以独立权利要求1的内容实现。有利的改进由从属权利要求给出。
设置有一种基于在绝缘衬底或本征半导体衬底上的横向半导体层场效应功率晶体管的金属化结构。所述横向半导体层具有不同的带间隔,使得在所述横向半导体层的半导体边界层中能够形成二维电子气。在源极电极接触面与漏极电极接触面之间或在源极电极与漏极电极之间施加电压的情况下电流能够流过横向半导体边界层。在源极电极接触面与漏极电极接触面之间的通道区域中的电流强度通过栅极电极接触面借助于栅极电压控制。源极电极接触面、漏极电极接触面和栅极电极接触面在半导体层的半导体表面上的金属化结构具有多个金属化层,在这多个金属化层之间沿横向布置绝缘层。金属化层不仅对于源极电极金属化结构而且对于漏极电极金属化结构具有包括接触爪的梳状结构。源极电极金属化结构和漏极电极金属化结构的接触爪间隔地相互啮合。每个接触爪具有接触爪底和接触爪尖。接触爪底的宽度在此大于接触爪尖的宽度。漏极电极接触面的功率金属化结构伸出超过相互咬合的所述场板金属化层的三角形的所述接触爪的边缘,其中所述源极电极接触面的所述场板金属化层伸出超过所述功率金属化层的边缘并且利用所述场板金属化层覆盖布置在所述源极电极接触面两侧的所述栅极电极接触面并且通过所述第二绝缘层与所述栅极电极接触面电绝缘。
场效应功率晶体管的金属化结构的优点在于多层金属化层,该多层金属化层可以优化如下:作为最外的功率金属化层应用耐腐蚀的材料,而对于布置在其下并且由环境保护的金属化层如例如场板金属化可以应用如下金属化层,该金属化层具有优化的导电能力和由金属层到金属层的最小接触电阻,而无需使用自身腐蚀保护装置。除此之外可以设有用于到半导体层的优化过渡的金属化材料,而无需考虑与场效应功率晶体管的外部环境的可能的反应。
另一优点在于不仅对于源极电极接触面、漏极电极接触面而且栅极电极接触面的金属化在此使用的梳状结构的几何结构。通过金属化层匹配于源极电极接触面、漏极电极接触面的结构和轮廓,其中接触爪底的宽度大于接触爪尖的宽度,并且省去金属化结构在以常规的平行延伸的梳状结构形式的半导体层上的平行引导,可以附加地确保:避免在各个金属接触层之间的电子迁移。
此外可以通过在接触底区域中几微米的宽度和朝接触爪尖不断减小的宽度的逐渐尖锐的接触爪使得金属化的电流负载均匀化。附加地通过导入小角度伽马需要的面积相比于常规梳状结果的常规矩形爪设计保持几乎不变。假如晶体管结构通过强力金属设计规则限制,那么可以通过接触面大小的变化甚至实现面积更易协调的晶体管。
在本发明的一个实施方式中,接触爪在接触爪尖的区域中的宽度趋向于零,其中源极电极金属化结构和漏极电极金属化结构的接触爪具有等边三角形,所述等边三角形具有相对于底边的顶角γ,该顶角为0°≤γ≤3°之间,优选为0.1°≤γ≤1.5°之间,特别优选为0.1°≤γ≤0.5°之间。对此接触爪底视为底边。在接触爪尖的区域中极其尖锐的角能实现对于按照本发明的梳状结构的相互啮合的接触爪延伸的细长的结构。
在此所述底边可以满足30μm≤c≤40μm之间、优选c=36μm的底边宽c。为此源极电极金属化结构和漏极电极金属化结构可以如此布置,使得在源极电极金属化结构的两个三角形接触爪的接触爪底的区域中设置漏极电极金属化结构的三角形接触爪的接触爪尖,并且反之亦然。
在本发明的另一实施方式中设置,多个金属化层首先具有在用于第一绝缘层的源极电极、漏极电极和栅极电极的相应的第一接触窗口中在半导体表面上的第一选择性接触层。在该第一接触层上布置另一所谓的欧姆接触层。对于第一选择性接触层通过接触窗在第一绝缘层中选择地构造,而欧姆接触层首先全面地沉积在第一绝缘层上并且紧接着选择性地构造,以便提供几何结构方面匹配于第一接触层的欧姆接触层。这样的欧姆接触层设有如下材料,该材料具有高度导电能力以及对于布置在其下的第一选择性接触层的最小接触电阻。
在此应用欧姆接触金属化和栅极电极金属化结构。栅极电极金属化结构必须可以仅仅承载再充电流,该再充电流可以在没有强力金属化的情况下实现。对于引导功率的漏极电极金属化结构和源极电极金属化结构需要另外的金属化层。
在源极电极金属化结构和漏极电极金属化结构的相应欧姆接触层上在第二绝缘层的相应的第二接触窗口中设有场板金属化层,该场板金属化层平面地在第二绝缘层上延伸并且覆盖第二绝缘层的第二接触窗口的面积的多倍。
第二接触窗口的平面面积本质上与第一绝缘层的第一接触窗口没有区别,而特别是源极电极金属化结构的场板金属化层悬置第二接触窗,使得源极电极金属化结构的场板金属化层完全重叠栅极电极金属化结构。
这具有的优点在于,在朝漏极侧方向的栅极边棱上的高电场大幅减小。通过安装该场板可以确保对该构件的寿命和可靠性要求。场板金属化层优选由铜合金构成。为了优化该屏蔽作用,优选地场板金属化层由铜合金构成。
即使其增大的面积扩展,源极电极金属化结构的场板金属化层与漏极电极金属化结构的场板金属化层均匀地间隔并且平面地相互啮合地根据源极电极接触面和漏极电极接触面的结构布置。为此必须遵循如下最小间隔,该最小间隔用于:在源极与漏极电极金属化结构之间的电场不太高,以便可以确保该电子构件的寿命和可靠性要求。如果所述间隔太小地选择,那么可以已经在需要的寿命内导致在应用的绝缘层中的电弧或击穿/短路。
在本发明的另一实施方式中,源极电极金属化结构和漏极电极金属化结构的多个金属化层在第三绝缘层的相应的第三接触窗口中相应的场板金属化层上具有源极电极接触面和漏极电极接触面的功率金属化层,所述功率金属化层平面地在第三绝缘层上延伸并且覆盖第三绝缘层的第三接触窗口的面积的多倍。
而且对于源极电极金属化结构和漏极电极金属化结构的功率金属化层首先第三接触窗口的面积大小等于第二和第一接触窗口,从而源极电极金属化结构和漏极电极金属化结构的第一、第二和第三接触窗口具有相同大小的梳状和爪结构。因为功率金属化结构必须接收在源极电极与漏极电极之间可切换的总电流,这两个梳状结果大约完全覆盖半导体层直至在源极电极金属化结构与漏极电极金属化结构的边缘之间预定的间隔。源极电极接触面的相互啮合的功率金属化结构和漏极电极接触面的功率金属化结构之间的该间隔a根据其150V/μm的电压等级位于在优选1μm≤a≤10μm并且特别优选1μm≤a≤6μm。
漏极电极接触面的功率金属化结构从漏极电极接触面相互啮合的场板金属化的三角形接触爪的边缘伸出,而源极电极接触面的场板金属化从源极电极接触面的功率金属化结构的边缘伸出。该区别支持通过用于栅极电极接触面的源极电极接触面的场板金属化电场的减小,因为场板金属化覆盖在源极电极金属化结构两侧布置的栅极电极接触面并且通过第二绝缘层与之电绝缘。
对于场效应功率晶体管的极为有效的功能具有决定性的是:漏极电极接触面的功率金属化结构与栅极电极接触面的欧姆接触层不重叠并且根据其150V/μm的电压等级具有与栅极电极接触面的优选1μm≤d≤30μm、特别优选1μm≤d≤10μm的最小间隔d。
在本发明的另一实施方式中设置,功率金属化结构的梯形爪在爪底上具有底角α,其中底角α小于所属的场板金属化层的梯形爪的底角β。由此涉及的优点在于,可用的晶体表面还可以更密集地应用。
在本发明的另一实施方式中设置,漏极电极金属化结构的功率金属化结构布置在源极电极金属化结构的两个彼此镜像布置的咬合的功率金属化结构之间的中间,从而漏极电极金属化结构的功率金属化的咬合具有圣诞树结构。
漏极电极金属化结构的功率金属化结构的该圣诞树结构有利地由源极电极金属化结构的功率金属化结构的两个相互对置的梳状结构环绕,从而可能的是,栅极电极接触面环绕该圣诞树结构布置并且由此确保:在施加漏极电极-源极电极电压或源极电极-漏极电极电压时在二维电子层中的电流可以通过栅极电极金属化结构控制并且不出现边缘侧的漏泄电流。
另一优点在于,由此避免负面的边缘效应,如其在常规平行的梳状结构中可能出现的那样,因为具有漏极电极金属化结构的功率金属化结构的圣诞树结构实际上由栅极电极金属化结构包围,而在按照本发明的可选的梳状结构中栅极电极金属化结构朝两个边缘侧结束。
在此设置,场效应功率晶体管的按照本发明的金属化用于高电子迁移率晶体管(HEM-晶体管)、或者用于调制掺杂场效应晶体管(MODFE-晶体管)、或者二维电子气场效应晶体管(TEGFE-晶体管)、或者选择性掺杂异质结晶体管(SDH-晶体管)或异质结场效应晶体管(HFE-晶体管)。为此对于具有不同带间隔的横向半导体层应用以下半导体材料系统中之一:AlGaAs/GaAs、AlInN/GaN、AlGaN/GaN、Si/SiGe、InGaAs/InP/AlInAs。
在本发明的另一实施方式中,场效应功率晶体管是HEM晶体管,其具有氮化铝镓层(AlGaN)作为对于源极电极接触面、漏极电极接触面和栅极电极接触面的第一金属接触层的最上过渡半导体层,其中为了构成二维电子气层将氮化铝镓层布置在本征的、未掺杂的氮化镓层上。
此外设置,具有其不同带间隔的半导体层布置在作为绝缘衬底的未掺杂或掺杂的碳化硅衬底或蓝宝石衬底上。可选地掺杂的硅晶片也可以用作衬底。
附图说明
现在根据实施方式参照附图进一步阐明本发明。
图1示出沿着按照图2的截面线A-A作为场效应功率晶体管1的HEMT功率晶体管(高电子迁移率晶体管)的金属化的示意性横截面;
图2A示出具有与图1的横截面视图的截面A-A的情况大小相同的三角形金属化爪的底角的HEMT功率晶体管的金属化的示意性俯视图;
图2B示出具有三角形的金属化爪的不同底角的HEMT功率晶体管的金属化的示意性俯视图;
图3示出按照本发明的另一实施方式场效应功率晶体管1A的功率金属化结构的示意性俯视图;
图4示出按照本发明的另一实施方式场效应功率晶体管1B的功率金属化结构的示意性俯视图。
具体实施方式
图1示出沿着按照图2的截面线A-A作为场效应功率晶体管1的HEMT功率晶体管的金属化结构2的示意横截面。该场效应功率晶体管1在示出的实施方式中具有由蓝宝石31组成的绝缘衬底5。在衬底5的上侧32上布置半导体层3和4,其中在本发明的该实施方式中半导体层3由本征氮化镓(i-GaN)26组成,其中i-GaN掺杂碳或铁离子以便补偿晶格缺陷。i-GaN层与布置在其上的氮化铝镓层(AlGaN)形成半导体边界层6。
在该半导体边界层6中构成二维电子气层,其中基于在二维电子气层中电子的高度可动性HEMT晶体管适用于直至千兆赫的最高频率。在施加电压在源极电极S与漏极电极D之间的情况下可以借助于栅极电极金属化结构29在施加高频栅极电压的情况下高频地调制和控制在二维电子气层中在源极电极S与漏极电极D之间的电流。
为此场效应功率晶体管1具有多层的金属化结构2,其如图1所示在该实施方式中由四个金属化层15、20、25和30组成,这四个金属化层由三个绝缘层21、22和23横向和选择地分隔。在此源极电极金属化结构27和漏极电极金属化结构28在位置、厚度和横向扩展上显著有别于栅极电极金属化结构29。
为了将大电流施加到在源极电极S与漏极电极D之间的半导体边界层6或二维电子气层中,作为外部的上面的功率金属化层30不仅对于在源极电极接触面7上的源极电极金属化结构27而且对于在漏极电极接触面8上的漏极电极金属化结构28设有相对厚的、导电良好的相对于外部环境影响耐腐蚀的功率金属化层30。
在图1中示出的在两个漏极电极接触面8和源极电极接触面7上的多层结构按照本发明没有如该截面首先可能被建议的那样彼此平行地延伸,而是源极电极金属化结构27朝图平面内越来越细并且从图平面拓宽或扩展出来。相比之下漏极电极金属化结构28朝图平面中扩展并且从图平面出来以锐角延伸,如以下的俯视图显而易见的那样。
为了避免在电极之间的电弧和大电场,可遵循在源极电极金属化结构27、漏极电极金属化结构28以及栅极电极金属化结构29之间的间隔。相应地栅极电极金属化结构29也不相对于衬底5的边缘不平行地延伸,而是在源极电极金属化结构27的功率金属化30的边缘33和34之下或者沿着该边缘。为了维持在源极电极接触面7与漏极电极接触面8之间的场效应功能,栅极电极接触面9在源极电极接触面两侧包围源极电极接触面直至在附图平面之下源极电极接触面7的不可见的尖端。
栅极电极接触面9具有仅仅一个构造的欧姆接触层20G。
多层金属化结构2对于源极电极金属化结构27和漏极电极金属化结构28具有两层,亦即在第一接触窗口17中第一接触层15S或15D以及欧姆接触层20S或20D,欧姆接触层布置在该第一接触层15S或15D中,以便减小接触电阻。该欧姆接触层20S或20D仅仅稍微地悬置第一接触层17S或17D。
对于源极电极金属化结构27和漏极电极金属化结构28,连接到欧姆接触层20S和20D的是增大的金属化,该增大的金属化对于源极电极金属化结构27以场板金属化层25S的形式,而对于漏极电极金属化结构28以场板金属化层25D的形式。最后功率金属化层30S或30D形成上端部。
源极电极金属化结构27在场板金属化层25中不同于漏极电极金属化结构28。源极电极接触面7的场板金属化层25S,其布置在第二绝缘层22的第二接触窗口18中并且在第二绝缘层22上相对于漏极电极金属化结构28的场板金属化层25D扩展多倍。
漏极电极金属化结构28的场板金属化层25D相对于在第二绝缘层22上的第二接触窗口18仅仅稍微地扩展。源极电极金属化结构27的场板金属化层25S在第二绝缘层22上扩展,使得该场板金属化层在两侧覆盖栅极电极金属化结构29并且大幅降低在栅边棱上朝漏极侧的方向的高电场并因此屏蔽电干扰场。为了进一步改善屏蔽作用,场板金属化层25在本发明的该实施方式中具有铜合金,该铜合金然而已知地对于表面氧化和腐蚀是敏感的。场板金属化层25然而尽可能地由一氧化物层形式的第三绝缘层23保护和覆盖。
在第三绝缘层23中布置接触窗口19,通过该接触窗口功率金属化结构30不仅在源极电极金属化结构27的区域中而且在漏极电极金属化结构28的区域中接触场板金属化层25。同时功率金属化层30在第三绝缘层23上在保持在此例如6μm的最小间隔a的情况下扩展,以便维护在源极电极S与漏极电极D之间的电压稳定性。作为用于功率金属化层的材料在本发明的该实施方式中应用铝合金,该铝合金在环境条件下形成保护的氧化铝外壳(AI2O3)并因此变得耐腐蚀。
例如6μm的间隔a也保持在源极电极金属化结构27的场板金属化层25S与漏极电极金属化结构28的场板金属化层25D之间。
图2A示出具有对于图1的横截面视图的截面A-A的位置的HEMT功率晶体管的金属化结构2的示意俯视图。该俯视图仅仅是源极电极S的梳状结构11S和漏极D的梳状结构11D的子视图,该梳状结构以其三角形的接触爪12S或12D在保持大约6μm的间隔a的情况下相互啮合。在此实线示出对于漏极D的功率金属化层30D以及对于源极电极S的功率金属化层30S的轮廓。
点划线标记布置在其下的对于源极电极S具有附图标记25S和对于漏极电极D具有附图标记25D的场板金属化层的边界。在图2中通过双点划线标记用于栅极电极G的电极接触面。此外电极接触面不仅对于源极电极S而且对于漏极电极D通过三重点划线标记,从而显著地可见源极电极接触面7S、漏极电极接触面8D和漏极电极D的轮廓,源极电极接触面、漏极电极接触面和漏极接触半导体表面。
由于顶角γ,源极电极S的接触爪12S和漏极电极D的接触爪12D朝其尖端越来越细,这在该原理图中及其增大地示出,以便可以更好地示出不同的金属化层的配置。接触爪12S和12D相对地显著更细长,从而顶角γ构成为相对于底边仅仅在0°≤γ≤3°,优选为0.1°≤γ≤1.5°,特别优选为0.1°≤γ≤0.5°的范围中。此外图2A示出,在功率金属化结构之下分别在到HEMT结构的接触爪12S和12D的过渡处布置绝缘条35或36,该绝缘条电气分离接触爪12S和12D的尖端,从而构成接触爪的梯形几何结构。这样的绝缘条35或36可以在源极电极S之下或在漏极电极D之下延伸直至相应的半导体芯片边缘37或38。
功率金属化结构30S和30D的梯形爪在爪底上具有底角αS或αD。场板金属化层25S和25D的梯形爪具有底角βS或βD,其中在图2A中示出的实施方式中底角αS和αD相等。而且角αS和βS相互相应并且大小相等。同样角αD和βD大小相等。
为了更好地利用可用的晶体表面,图2B示出具有功率金属化结构30S和30D的梯形爪的不同底角αS和αD的HEMT功率晶体管的金属化的示意俯视图。此外源极电极接触爪的底角αS可以不等于源极电极场板金属化层25S的梯形爪的底角βS。同样漏极电极接触爪的底角αD可以不等于漏极电极场板金属化层25D的梯形爪的底角βD。然而可以保持在栅极电极接触面9的边缘与漏极电极接触面8D的边缘之间足够的电压稳定性的预定间隔g。相应的附图标记和点划线以及其功能的意义相应于图2A中的意义。
图4示出按照本发明的另一实施方式场效应功率晶体管1A的功率金属化结构30的示意俯视图。图4仅仅示出不仅对于具有梳状结构11D的漏极电极D的功率金属化结构30D而且对于具有梳状结构11S的源极S的功率金属化结构30S的梳状结构11的原理。梳状结构11D形成逐渐尖锐的接触爪12D,该接触爪在其接触爪底13D中具有宽度b,该宽度等于等边三角形的底边宽c,该等边三角形形成接触爪12D的外轮廓,其中尖端也可以是倒圆的。
宽度b在本发明的该实施方式中为32μm,其中角γ位于在上述值范围中并且从接触爪底13D延伸直至接触爪尖14D。在此,在两个底部区域13D之间分别布置源极电极S的梳状结构11S的接触爪尖14S。布置在由AlGaN层24组成的半导体表面上的栅极电极金属化结构29在图3中仅仅以虚线标明并且示出欧姆接触层20G。然而如上所述,欧姆接触层20G由源极电极金属化结构27的在此未示出的场板金属化结构25S重叠或覆盖,以便减小在栅边棱上朝漏极的方向的电场。
此外可说明的是,在按照图3的本发明的该实施方式中栅极电极金属化结构在两个对置的边缘上结束并且在此蜿蜒曲折地包围源极S的梳状结构11S。
图5示出按照本发明的另一实施方式场效应功率晶体管1B的功率金属化结构30的示意俯视图。具有相同功能的构件如在上述图中以相同附图标记表示并且不再进一步阐明。
场效应功率晶体管1B的另一实施方式相对于按照图4的场效应功率晶体管1A的上述实施方式的区别在于,漏极电极D现在布置在半导体芯片上的中间并且由源极的两个梳状结构11S围绕。因此,漏极电极D示出用于其功率金属化结构30D的圣诞树结构16并且由闭合的栅极电极G包围或围绕,从而此外通常的边缘效应对于栅极电极的开始和结束在本发明的该实施方式中取消。
因此该HEMT功率晶体管的效率和安全如上所述通过接触爪的三角形结构相对于平行结构改善并且使得在接触爪12S和12D之间的电流密度由接触爪底13D或13S直至接触爪尖14S或14D均匀化。除此之外,多个接触爪可以安装在相同的半导体面上,这表示:每个半导体芯片面的最大可控的电流可以增大,因为通道宽度扩展。
虽然在上述说明中示出至少一个示例性的实施方式,但是可以进行不同的变化和修改。所述实施方式仅仅是例子并且设置不用于以任意方式限制有效性范围、可用性或布置。而是上述说明对于本领域内技术人员提供用于实现至少一个示例性的实施方式的规划,其中可以做出在示例性的实施方式中所示元件的功能和布置上的多个变化,而不会离开所附权利要求及其法律上的等同的保护范围。
附图标记列表:
1 场效应功率晶体管
2 金属化结构
3 半导体层
4 半导体层
5 绝缘衬底
6 半导体边界层
7 源极电极接触面
8 漏极电极接触面
9 栅极电极接触面
10 半导体表面
11、11S、11D 梳状结构
12、12S、12D 接触爪
13、13S、13D 接触爪底
14、14S、14D 接触爪尖
15、15S、15D、15G 第一接触层
16 圣诞树结构
17 第一接触窗口
18 第二接触窗口
19 第三接触窗口
20、20S、20D、20G 欧姆接触层
21 第一绝缘层
22 第二绝缘层
23 第三绝缘层
24 高度掺杂n+-AlGaN层
25、25S、25D 场板金属化层
26 本征氮化镓层
27 源极电极金属化结构
28 漏极电极金属化结构。
29 栅极电极金属化结构
30、30S、30D 功率金属化层
31 蓝宝石衬底
32 上侧
33 功率金属化结构的边缘
34 功率金属化结构的边缘
35 绝缘条
36 绝缘条
a 间隔
b 宽度
c 底边宽度
g 间隔
D 漏极
G 栅极
S 源极
α 底角
β 底角
γ 顶角

Claims (24)

1.一种基于在绝缘衬底(5)或本征或掺杂半导体衬底上的横向半导体层(3,4)的场效应功率晶体管(1)的金属化结构,其中所述横向半导体层(3,4)具有不同的带间隔,使得在所述横向半导体层的半导体边界层(6)中能够形成二维电子气,所述二维电子气在源极电极接触面(7)与漏极电极接触面(8)之间、在将电压施加在源极(S)与漏极(D)之间的情况下能够流过所述横向半导体的边界层,其中能够通过栅极电极接触面(9)借助于栅极电压来控制在所述源极电极接触面(7)与所述漏极电极接触面(8)之间的通道区域中的电流强度,其中在所述半导体层(3,4)的半导体表面(10)上的所述源极电极接触面(7)、所述漏极电极接触面(8)和所述栅极电极接触面(9)的金属化结构具有多个金属化层,在所述多个金属化层之间在横向方向上布置绝缘层,其中,所述金属化层包括功率金属化层和场板金属化层,所述场板金属化层布置在所述功率金属化层的下方,其中,不仅针对源极电极金属化结构(27)还针对漏极电极金属化结构(28)中的一个漏极电极金属化结构,所述金属化层具有带有接触爪(12)的梳状结构(11),其中所述源极电极金属化结构(27)和所述漏极电极金属化结构(28)的所述接触爪(12)相互间隔地啮合并且每个接触爪(12)具有接触爪底(13)和接触爪尖(14),其中所述接触爪底(13)的宽度(b)大于所述接触爪尖(14)的宽度,
其特征在于,
所述漏极电极接触面(8)的功率金属化层(30)伸出超过相互咬合的场板金属化层(25)的所述接触爪(12)的边缘,并且其中所述源极电极接触面(7)的所述场板金属化层(25)伸出超过所述功率金属化层(30)的边缘并且利用所述场板金属化层(25)覆盖布置在所述源极电极接触面(7)两侧的所述栅极电极接触面(9)并且通过第二绝缘层(22)与所述栅极电极接触面电绝缘。
2.根据权利要求1所述的场效应功率晶体管(1)的金属化结构,其中,在所述接触爪尖(14)上的所述宽度趋向于零。
3.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极金属化结构(27)和所述漏极电极金属化结构(28)的所述接触爪(12)具有等腰三角形的形状,所述等腰三角形具有相对于所述三角形的底边为0°≤γ≤3°的顶角γ。
4.根据权利要求3所述的场效应功率晶体管(1)的金属化结构,其中,所述底边具有30μm≤c≤40μm的底边宽度c。
5.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,在所述源极电极金属化结构(27)的两个三角形的接触爪(12)的所述接触爪底(13)的区域中布置所述漏极电极金属化结构(28)的三角形的接触爪(12)的接触爪尖(14),并且反之亦然。
6.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述多个金属化层首先具有第一选择性接触层(15)和选择性欧姆接触层(20),所述第一选择性接触层(15)在第一绝缘层(21)的用于源极(S)、漏极(D)和栅极(G)的相应的第一接触窗口(17)中在半导体表面(10)上,所述选择性欧姆接触层布置在第一选择性接触层(15)上。
7.根据权利要求6所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极金属化结构(27)和所述漏极电极金属化结构(28)的多个金属化层在第二绝缘层(22)的各自的第二接触窗口中在相应的选择性欧姆接触层(20)上具有场板金属化层(25),所述场板金属化层平面地在所述第二绝缘层(22)上延伸并且覆盖所述第二绝缘层(22)的所述第二接触窗口的面积的多倍。
8.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极金属化结构(27)的所述场板金属化层(25)和所述漏极电极金属化结构(28)的所述场板金属化层(25)相互间隔并且平面地彼此咬合地根据所述源极电极接触面(7)和所述漏极电极接触面(8)的结构来被布置。
9.根据权利要求7所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极金属化结构(27)和所述漏极电极金属化结构(28)的所述多个金属化层在第三绝缘层(23)的相应的第三接触窗口中在各自的所述场板金属化层(25)上具有所述源极电极接触面(7)和所述漏极电极接触面(8)的功率金属化层(30),所述功率金属化层平面地在所述第三绝缘层(23)上延伸并且覆盖所述第三绝缘层(23)的所述第三接触窗口的面积的多倍。
10.根据权利要求9所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极金属化结构(7)和所述漏极电极金属化结构(8)的第一接触窗口、第二接触窗口和第三接触窗口(17,18,19)具有相同大小的梳状结构和接触爪结构。
11.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,相互咬合的所述源极电极接触面(7)和所述漏极电极接触面(8)的所述场板金属化层(25)具有铜合金,并且所述源极电极接触面(7)和所述漏极电极接触面(8)的所述功率金属化层(30)具有铝合金。
12.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述漏极电极接触面(8)的所述功率金属化层(30)中心地布置在所述源极电极接触面(7)的两个彼此镜像布置的咬合的所述功率金属化层(30)之间,使得所述漏极电极接触面(8)的所述功率金属化层(30)的啮合具有圣诞树结构(16)。
13.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,带有不同带间隔的所述横向半导体层(3,4)具有以下半导体材料体系中的一个:Si/SiGe、AlGaAs/GaAs、InGaAs/InP/AlInAs、AlInN/GaN、AlGaN/GaN。
14.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述源极电极接触面(7)的相互咬合的所述功率金属化层(30)和所述漏极电极接触面(8)的所述功率金属化层彼此具有根据其150V/μm的电压等级的间隔a。
15.根据权利要求1所述的场效应功率晶体管(1)的金属化结构,其中,所述功率金属化层(30S和30D)的梯形爪在爪底上对于所述源极电极接触爪具有底角αS以及对于所述漏极电极接触爪具有底角αD,其中αS和αD不相等,并且其中所述源极电极接触爪的所述底角αS不等于所述源极电极场板金属化层(25S)的梯形爪的底角βS,并且所述漏极电极接触爪的所述底角αD不等于所述漏极电极场板金属化层(25D)的梯形爪的底角βD
16.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述场效应功率晶体管(1)是高电子迁移率晶体管、调制掺杂场效应晶体管、二维电子气场效应晶体管、选择性掺杂异质结晶体管或异质结场效应晶体管。
17.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,所述场效应功率晶体管(1)是具有作为对于金属源极电极接触面(7)、漏极电极接触面(8)和栅极电极接触面(9)的最上的过渡半导体层的高度掺杂的n型导通型氮化铝镓层(24)的HEM晶体管,其中为了构成二维电子气层,所述氮化铝镓层(24)布置在本征的、未掺杂的、掺杂碳或铁的氮化镓层(26)上。
18.根据权利要求1或2所述的场效应功率晶体管(1)的金属化结构,其中,具有不同带间隔的半导体层(3,4)布置在未掺杂的碳化硅衬底或蓝宝石衬底(31)上。
19.根据权利要求3所述的场效应功率晶体管(1)的金属化结构,其中,所述顶角γ为0.1°≤γ≤1.5°。
20.根据权利要求19所述的场效应功率晶体管(1)的金属化结构,其中,所述顶角γ为0.1°≤γ≤0.5°。
21.根据权利要求4所述的场效应功率晶体管(1)的金属化结构,其中,所述底边宽度c=36μm。
22.根据权利要求14所述的场效应功率晶体管(1)的金属化结构,其中,所述间隔a是1μm≤a≤10μm。
23.根据权利要求22所述的场效应功率晶体管(1)的金属化结构,其中,所述间隔a是1μm≤a≤6μm。
24.根据权利要求17所述的场效应功率晶体管(1)的金属化结构,其中,当所述氮化镓层是碳或铁掺杂的时,所述氮化镓层(26)是被补偿的。
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10217819B2 (en) * 2015-05-20 2019-02-26 Samsung Electronics Co., Ltd. Semiconductor device including metal-2 dimensional material-semiconductor contact
US10217827B2 (en) * 2016-05-11 2019-02-26 Rfhic Corporation High electron mobility transistor (HEMT)
KR102576999B1 (ko) * 2016-07-05 2023-09-12 삼성디스플레이 주식회사 액정표시장치
US10249725B2 (en) * 2016-08-15 2019-04-02 Delta Electronics, Inc. Transistor with a gate metal layer having varying width
CN110168936B (zh) * 2016-11-24 2023-06-09 威电科技有限公司 晶体管单元
US9899484B1 (en) 2016-12-30 2018-02-20 Texas Instruments Incorporated Transistor with source field plates under gate runner layers
CN107240605A (zh) * 2017-06-23 2017-10-10 北京华进创威电子有限公司 一种GaN MIS沟道HEMT器件及制备方法
JP7147703B2 (ja) * 2019-07-16 2022-10-05 株式会社デンソー 半導体装置
CN110649096B (zh) * 2019-10-08 2021-06-04 电子科技大学 一种高压n沟道HEMT器件
KR20220006402A (ko) * 2020-07-08 2022-01-17 삼성전자주식회사 고전자 이동도 트랜지스터
US11515235B2 (en) * 2020-10-30 2022-11-29 Gan Systems Inc. Device topology for lateral power transistors with low common source inductance
US11527460B2 (en) * 2020-10-30 2022-12-13 Gan Systems Inc. Device topologies for high current lateral power semiconductor devices
EP4207283A1 (en) * 2021-12-31 2023-07-05 Nexperia B.V. A semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02102546A (ja) * 1988-10-12 1990-04-16 Mitsubishi Electric Corp GaAs半導体装置の製造方法
JP2602360B2 (ja) * 1990-11-16 1997-04-23 富士通株式会社 電界効果型半導体装置
CN102097467A (zh) * 2009-12-10 2011-06-15 三垦电气株式会社 化合物半导体装置及其制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7166867B2 (en) * 2003-12-05 2007-01-23 International Rectifier Corporation III-nitride device with improved layout geometry
JP5300238B2 (ja) 2006-12-19 2013-09-25 パナソニック株式会社 窒化物半導体装置
US7767589B2 (en) * 2007-02-07 2010-08-03 Raytheon Company Passivation layer for a circuit device and method of manufacture
JP5530682B2 (ja) * 2009-09-03 2014-06-25 パナソニック株式会社 窒化物半導体装置
JP5618571B2 (ja) * 2010-03-02 2014-11-05 パナソニック株式会社 電界効果トランジスタ
JP5457292B2 (ja) * 2010-07-12 2014-04-02 パナソニック株式会社 窒化物半導体装置
JP2012023212A (ja) * 2010-07-14 2012-02-02 Sumitomo Electric Ind Ltd 半導体装置
JP6018360B2 (ja) * 2010-12-02 2016-11-02 富士通株式会社 化合物半導体装置及びその製造方法
US9406673B2 (en) * 2013-12-23 2016-08-02 Infineon Technologies Austria Ag Semiconductor component with transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02102546A (ja) * 1988-10-12 1990-04-16 Mitsubishi Electric Corp GaAs半導体装置の製造方法
JP2602360B2 (ja) * 1990-11-16 1997-04-23 富士通株式会社 電界効果型半導体装置
CN102097467A (zh) * 2009-12-10 2011-06-15 三垦电气株式会社 化合物半导体装置及其制造方法

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