CN105336764A - 半导体器件和制造方法 - Google Patents

半导体器件和制造方法 Download PDF

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CN105336764A
CN105336764A CN201510469712.2A CN201510469712A CN105336764A CN 105336764 A CN105336764 A CN 105336764A CN 201510469712 A CN201510469712 A CN 201510469712A CN 105336764 A CN105336764 A CN 105336764A
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nitride
carbide
semiconductor
semiconductor device
semiconductor body
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CN105336764B (zh
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U.格拉泽
P.伊尔西格勒
H-J.舒尔策
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Infineon Technologies AG
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Abstract

本发明涉及半导体器件和制造方法。半导体器件包括从第一表面延伸到半导体主体中的沟槽。三元碳化物和三元氮化物的至少一个在沟槽中。

Description

半导体器件和制造方法
背景技术
半导体器件的电特性被多个器件部分影响。在半导体器件（例如二极管或晶体管，例如绝缘栅场效应晶体管（IGFET），诸如金属氧化物半导体场效应晶体管（MOSFET）、绝缘栅双极晶体管（IGBT）、结场效应晶体管（JFET）、双极结晶体管（BJT））的负载端子之间的电阻由例如半导体块、触头和布线确定。最小化电阻允许在半导体器件中的电阻损耗的减小。
提供使得能够实现改进的电特性的半导体器件和制造方法是期望的。
发明内容
根据半导体器件的实施例，半导体器件包括从第一表面延伸到半导体主体中的沟槽。三元碳化物和三元氮化物的至少一个在沟槽中。
根据半导体器件的另一实施例，半导体器件包括具有相对的第一和第二表面的半导体主体。氮化物和碳化物中的至少一个被掩埋在半导体主体中。半导体主体的第二部分在第一表面与氮化物和碳化物的至少一个之间。半导体主体的第一部分在第二表面与氮化物和氮化物的至少一个之间。氮化物和碳化物的至少一个的熔点大于900℃。
根据制造半导体的方法的实施例，该方法在半导体主体的第二部分上形成氮化物和碳化物的至少一个。该方法还包括通过在第二部分上和在氮化物和碳化物的至少一个上经由外延生长形成半导体主体的第一部分来将氮化物和碳化物的至少一个掩埋在半导体主体中。
本领域中的技术人员在阅读下面的详细描述时并在观看附图时将认识到附加的特征和优点。
附图说明
附图被包括以提供对本发明的进一步理解并被合并在本说明书中且构成本说明书的一部分。附图图示本发明的实施例并与描述一起用于解释本发明的原理。本发明的其它实施例和预期优点将容易被认识到，因为它们通过参考下面的详细描述变得更好理解。
图1是用于图示包括包含在沟槽中的三元碳化物和三元氮化物的至少一个的结构的半导体器件的半导体主体的示意性横截面视图。
图2A到2I和图3A到3C图示图1的结构的不同实施例。
图4、5A和5B是用于图示包括掩埋在半导体主体中的碳化物和氮化物的至少一个的半导体器件的半导体主体的示意性横截面视图。
图6、7A和7B是用于图示包括三元碳化物和三元氮化物的至少一个的横向和垂直二极管的半导体主体的示意性横截面视图。
图8是用于图示包括三元碳化物和三元氮化物的至少一个的npn双极结晶体管（BJT）的半导体主体的示意性横截面视图。
图9A和9B是用于图示制造包括掩埋在半导体主体中的碳化物和氮化物的至少一个的半导体器件的方法的半导体主体的示意性横截面视图。
具体实施方式
在下面的详细描述中，参考形成其一部分的附图，且其中作为例证示出本公开内容可被实践的特定实施例。应理解，可利用其它实施例且可做出结构或逻辑改变而不偏离本发明的范围。例如，对一个实施例图示或描述的特征可在其它实施例上或结合其它实施例来使用以产出另外的实施例。意图是本公开内容包括这样的修改和变化。使用不应被解释为限制所附权利要求的范围的特定语言描述了示例。附图并不按比例且仅为了例证性目的。为了清楚起见，相同的元件在不同的附图中由对应的参考符号表示，如果不是另有规定。
术语“具有”、“包含”、“包括”、“包括了”等是开放的，且术语指示所陈述的结构、元件或特征的存在，但不排除附加的元件或特征的存在。冠词“一”、“一个”和“该”意在包括复数以及单数，除非上下文清楚地另有指示。
术语“电连接”描述在电连接的元件之间的永久低欧姆连接，例如在所关注的元件之间的直接接触或经由金属和/或高掺杂半导体的低欧姆连接。术语“电耦合”包括，适合于信号传输的一个或多个（多个）中间元件可存在于电耦合的元件，例如暂时提供在第一状态中的低欧姆连接和在第二状态中的高欧姆电解耦的元件之间。
附图通过指示紧接于掺杂类型“n”或“p”的“-”或“+”而图示相对掺杂浓度。例如，“n-”意指比“n”掺杂区的掺杂浓度低的掺杂浓度，而“n+”掺杂区具有比“n”掺杂区的掺杂浓度高的掺杂浓度。相同的相对掺杂浓度的掺杂区并不一定具有相同的绝对掺杂浓度。例如，两个不同的“n”掺杂区可具有相同或不同的绝对掺杂浓度。
在下面的描述中使用的术语“晶片”、“衬底”、“半导体主体”或“半导体衬底”可包括具有半导体表面的任何基于半导体的结构。晶片和结构应被理解为包括硅、绝缘体上硅（SOI）、蓝宝石上硅（SOS）、掺杂和非掺杂半导体、由基本半导体基础支持的硅的外延层和其它半导体结构。半导体不需要是基于硅的。半导体也可以是硅锗（SiGe）、锗（Ge）或砷化镓（GaAs）。根据其它实施例，碳化硅（SiC）或氮化镓（GaN）可形成半导体衬底材料。
如在这个说明书中使用的术语“水平”意在描述基本上平行于半导体衬底或半导体主体的第一或主表面的取向。这可例如是晶片或管芯的表面。
如在这个说明书中使用的术语“垂直”意在描述基本上布置成垂直于半导体衬底或半导体主体的第一表面、即平行于该第一表面的法线方向的取向。
在这个说明书中，半导体衬底或半导体主体的第二表面被考虑为由下或背侧表面形成，而第一表面被考虑为由半导体衬底的上、前或主表面形成。如在本说明书中使用的术语“在…上方”和“在…下方”因此描述结构特征对另一结构特征的相对位置。
在这个说明书中，n掺杂被称为第一导电类型，而p掺杂被称为第二导电类型。可替换地，半导体器件可被形成有相反的掺杂关系，使得第一导电类型可以是p掺杂的，而第二导电类型可以是n掺杂的。
在本说明书中描述的特定实施例涉及而不限于半导体器件，特别是场效应半导体晶体管、二极管、双极晶体管和ESD保护器件。在这个说明书内，术语“半导体器件”和“半导体部件”同义地被使用。半导体器件一般包括场效应或晶体管结构。场效应结构可以是具有形成在第一导电类型的漂移区和第二导电类型的主体区之间的主体二极管的pn结的MOSFET或IGBT结构。半导体器件一般是具有两个负载金属化的垂直半导体器件，例如MOSFET的源极金属化和漏极金属化，其彼此相对地布置且与相应的接触区处于低电阻接触中。场效应结构也可由JFET结构形成。
作为示例，半导体器件是具有有源区域的功率半导体器件，有源区域具有例如用于携带和/或控制在两个负载金属化之间的负载电流的多个IGBT单元或MOSFET单元。此外，功率半导体器件一般具有外围区域，其具有当从上方看时至少部分地围绕有源区域的至少一个边缘终止结构。
如在本说明书中使用的术语“功率半导体器件”意在描述具有高电压和/或高电流开关能力的在单个芯片上的半导体器件。换句话说，功率半导体器件意图针对一般在10安培到几KA范围内的高电流。在这个说明书内，术语“功率半导体器件”和“功率半导体部件”同义地被使用。
如在本说明书中使用的术语“场效应”意在描述第一导电类型的导电“沟道”的电场居间形成和/或在第一导电类型的两个区之间的沟道的导电性和/或形状的控制。导电沟道可在布置在第一导电类型的两个区之间的第二导电类型的半导体区，一般是第二导电类型的主体区中被形成和/或控制。由于场效应，穿过沟道区的单极电流路径在分别在MOSFET结构和IGBT结构中的第一导电类型的源极区或发射极区与第一导电类型的漂移区之间被形成和/或控制。漂移区可分别与第一导电类型的较高掺杂漏极区或第二导电类型的较高掺杂集电极区接触。漏极区或集电极区与漏极或集电极电极处于低电阻电接触中。源极区或发射极区与源极或发射极电极处于低电阻电接触中。在JFET结构中，沟道区一般由布置在第二导电类型的主体区和栅极区之间的第一导电类型的漂移区的一部分形成，并可通过改变在栅极区和沟道区之间形成的耗尽层的宽度来控制。
在本说明书的上下文中，术语“MOS”（金属氧化物半导体）应被理解为包括更一般的术语“MIS”（金属绝缘体半导体）。例如，术语MOSFET（金属氧化物半导体场效应晶体管）应被理解为包括具有不是氧化物的栅极绝缘体的FET，即术语MOSFET分别在IGFET（绝缘栅场效应晶体管）和MISFET（金属绝缘体半导体场效应晶体管）的更一般的术语意义中被使用。
在本说明书的上下文中，术语“栅电极”意在描述配置成形成和/或控制沟道区的电极。
作为示例，栅电极被实现为沟槽-栅电极，即作为布置在从主表面延伸到半导体衬底或主体中的沟槽中的栅电极。栅电极也可被实现为平面栅电极。
当沟槽-栅电极当从上方看时形成例如跳棋盘的形式的二维晶格时，功率场效应半导体器件的有源区域的单位单元在水平横截面中可包括沟槽-栅电极和台面的周围部分。
可替换地，功率场效应半导体器件的有源区域的单位单元当从上方看时可在水平横截面中包括沟槽-栅电极和两个邻接的台面的相应部分。在这些实施例中，沟槽-栅电极、台面和单位单元可形成相应的一维晶格。
在图1中图示根据实施例的半导体器件100的半导体主体105的示意性横截面视图。
半导体器件100包括从第一表面107，例如与例如背表面的第二表面108相对的前表面延伸到半导体主体105中的沟槽106。在沟槽中的结构111包括三元碳化物和三元氮化物的至少一个。
根据实施例，三元碳化物和三元氮化物的至少一个是AxByRz，A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一；B是Al、Si、P、S、Ga、Ge、As、Cd、In、Sn、Te和Pb之一；R是C和N之一；以及[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。[3,1,2]的示例是Ti3AlC2、Ti3GeC2、Ti3SiC2。[4,1,3]的示例是Ti4AlN3。
根据另一实施例，可选的接触层112被布置在三元碳化物和三元氮化物的至少一个与半导体主体105之间。接触层可以是硅化物或高掺杂半导体，例如p+掺杂或n+掺杂层。接触层112可被布置在三元碳化物和三元氮化物的至少一个与半导体主体105之间电接触界面处，并可在电接触界面之外缺乏。
根据另一实施例，光接触层112可被布置在三元碳化物和三元氮化物的至少一个与半导体主体105（例如侧壁和/或底侧）之间的接触界面的一部分处。
根据在图2A的示意性横截面视图中图示的实施例，三元碳化物和三元氮化物的至少一个113完全填充沟槽106。
根据在图2B的示意性横截面视图中图示的另一实施例，电介质层115被布置在三元碳化物和三元氮化物的至少一个113与沟槽106的侧壁之间。电介质层提供在三元碳化物和三元氮化物的至少一个113与半导体主体105之间的横向电隔离。电介质115可以是氧化物（例如氧化硅）和/或氮化物（例如氮化硅），并可包括配置成提供电隔离的任何其它（多个）电介质材料。三元碳化物和三元氮化物的至少一个113在沟槽106的底侧处邻接半导体主体105。
根据在图2C的示意性横截面视图中图示的另一实施例，电介质层115被布置在三元碳化物和三元氮化物的至少一个113的底侧与半导体主体105之间。电介质115考虑到三元碳化物和三元氮化物的至少一个113到底侧的电隔离。与半导体主体105的电接触通过沟槽105的侧壁来实现，其例如由可选的接触层112支持。
根据在图2D的示意性横截面视图中图示的另一实施例，三元碳化物和三元氮化物的至少一个113被布置在沟槽106的底部分处。电介质115被布置在三元碳化物和三元氮化物的至少一个113上。因此，电介质115被布置在第一表面107与三元碳化物和三元氮化物的至少一个113之间。电介质115考虑到三元碳化物和三元氮化物的至少一个113到第一表面107的电隔离。与半导体主体105的电接触通过沟槽106的侧壁来实现，其例如由可选的接触层112支持。
在图2E到2I中图示在沟槽106中的三元碳化物和三元氮化物的至少一个113的布置的另外的实施例。未加衬里或填充有三元碳化物和三元氮化物的至少一个113的沟槽的部分包括充填物118，其包括一个或多个（多个）导电或绝缘材料及其组合。
在图2A到2I中所示的实施例中，三元碳化物和三元氮化物的至少一个113可提供与在半导体主体105中形成的任何半导体区的电接触。
根据图3A所示的实施例，半导体区是从第一表面107延伸到半导体主体105中的掺杂阱区117。与图3A所示的实施例的掺杂阱区117的电接触由如图2A所示的三元碳化物和三元氮化物的至少一个113的布置提供。电接触也可由如图2B到2I中的任何一个所示的三元碳化物和三元氮化物的至少一个113的布置中的任何一个提供。
根据图3B所示的实施例，与掺杂阱区117的电接触由多个结构111实现，结构111中的每一个包括如图2A到2I中的任何一个所示的三元碳化物和三元氮化物的至少一个113。
根据图3C所示的另一实施例，半导体区是掩埋在第一表面107之下的半导体主体105中的掺杂掩埋层119。与掺杂掩埋层119的电接触由结构111实现，结构111包括如图2A到2I中的任何一个所示的三元碳化物和三元氮化物的至少一个113。
可以从例如单晶半导体材料，例如硅（Si）、碳化硅（SiC）、锗（Ge）、硅锗（SiGe）、氮化镓（GaN）或砷化镓（GaAs）提供半导体主体105。
根据实施例，半导体器件100是分立半导体器件。根据另一实施例，半导体器件100是集成电路。不同于由在单个半导体主体上制造和互连的几个到数十亿个有源器件组成的集成电路（IC），分立半导体器件是在半导体主体中的单个晶体管或单个二极管，而没有与其互连的任何其它有源半导体元件。虽然无源部件，例如电阻器、电容器和电感器可在半导体主体中和/或上形成，分立半导体器件被规定为执行示例性电子功能。虽然分立半导体器件可包括大量晶体管单元，分立半导体器件被规定为执行示例性电子功能且不可分成在本身中起作用的分开的部件，如对于集成电路典型的。
半导体器件100可包括垂直半导体器件和横向半导体器件中的至少一个，例如IGFET，诸如包括超结和非超结IGFET的金属氧化物半导体场效应晶体管（MOSFET）、IGBT、静电放电（ESD）保护器件、二极管、双极晶体管。
关于图1到3C描述的实施例考虑到多个技术益处。由于包括三元碳化物和/或氮化物的结构111的热稳定性，可在结构111的形成之后执行需要高温的工艺，从而改进前道工序（FEOL）处理的灵活性。而且，结构111考虑到在半导体主体105之上的布线区域和在半导体主体105中的半导体区（例如掺杂阱区或掩埋层）之间的互连的电阻的减小。因为结构111考虑到半导体主体105的较大深度的横向电流密度的均匀化，半导体主体105的有源区域可以被更有效地使用。此外，结构111允许省去耐久的热工艺，例如诸如半导体区（诸如n掺杂下沉区）的向外扩散工艺。
在图4中图示半导体器件150的另一实施例。半导体器件150包括具有相对的第一和第二表面107、108的半导体主体105。氮化物和碳化物的至少一个155被掩埋在半导体主体105中。半导体主体105的第二部分1052在第一表面107与氮化物和碳化物的至少一个155之间。半导体主体105的第一部分1051在第二表面108与氮化物和碳化物的至少一个155之间。氮化物和碳化物的至少一个155的熔点大于900℃。
根据实施例，氮化物和碳化物的至少一个155是二元或三元化合物。
根据实施例，碳化物和氮化物的至少一个155是AxByRz，A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一；B是Al、Si、P、S、Ga、Ge、As、Cd、In、Sn、Te和Pb之一；R是C和N之一；以及[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。根据另一实施例，碳化物和氮化物的至少一个155包括TaN和/或TaC和/或W、Ti、Mo、Co的其它碳化物。
根据另一实施例，碳化物和氮化物的至少一个155的电导率大于3x106S/m。
根据另一实施例，碳化物和氮化物的至少一个155是掩埋在半导体主体105中的电布线。类似于图2A到2I所示的实施例，光接触层和/或电介质可被布置在电布线和半导体主体105之间。
根据实施例，碳化物和氮化物的至少一个是横向布置在晶体管单元阵列和结终止区域之间的过渡区域中的重组结构。
根据图5A所示的实施例，碳化物和氮化物的至少一个155是垂直地布置在第一表面107处的高掺杂发射极区160和第一部分1051中的漂移区163之间的重组结构。例如，掺杂发射极区160可以是半导体器件，例如二极管、晶体管或寄生晶体管，例如IGBT、IGFET、JFET或BJT的部分。这考虑到对于改进器件鲁棒性可能有益的迁移因子的减小。
根据图5B所示的实施例，碳化物和氮化物的至少一个155是横向布置在第一半导体器件的第一有源区域166和第二半导体器件的第二有源区域167之间的重组结构。重组结构允许减小在第一和第二半导体器件的一个中由从第一和第二半导体器件的另一个注入到半导体主体105中的少数载流子引起的故障。
在图6中的半导体主体105的示意性横截面视图中图示包括图1的结构111的横向二极管201的示例。半导体主体105包括在半导体衬底171和半导体层172（例如外延半导体层）之间的掩埋层119。器件隔离由深沟槽隔离（DTI）180实现。
横向二极管201的阳极端子A经由与图2F所示的结构类似的第一结构1111电耦合到阳极区205。
横向二极管201的阴极端子C经由与图2F所示的结构类似的第二结构1112电耦合到阴极区206。
因为第一和第二结构1111、1112考虑到阳极和阴极区205、206的深部分的低欧姆连接，二极管电流可相对于阳极/阴极区205、206的深度均匀地流动。通过省略在三元碳化物和三元氮化物的至少一个113的底侧处的接触层112可减小或抑制垂直二极管电流部件的影响。
在图7A中的半导体主体105的示意性横截面视图中图示包括图1的结构111的垂直二极管202的第一示例。半导体主体105包括在半导体衬底171和半导体层172（例如外延半导体层）之间的掩埋层119。器件隔离由深沟槽隔离（DTI）180实现。
垂直二极管202的阳极端子A经由三元碳化物和三元氮化物的至少一个113和接触层112电耦合到阳极区205。
垂直二极管202的阴极端子C经由三元碳化物和三元氮化物的至少一个113和接触层112电耦合到阴极区的n掺杂下沉部207。
在图7B中的半导体主体105的示意性横截面视图中图示没有n掺杂下沉部207但包括图1的结构111的垂直二极管203的第二示例。不同于在图7A中所示的示例中，阴极端子经由三元碳化物和三元氮化物的至少一个113和接触层112电连接到掩埋层119。此外，阳极区205经由多个的三元碳化物和三元氮化物的至少一个113电连接到阳极端子A，类似于图3B所示的实施例。因为图7B所示的示例允许省去n掺杂下沉部207，制造n掺杂下沉部207的工艺成本可被避免。
在图8中的半导体主体105的示意性横截面视图中图示包括图1的结构111的npn双极结晶体管（BJT）204的示例。
npnBJT204的发射极端子e经由三元碳化物和三元氮化物的至少一个113和接触层112电耦合到n掺杂发射极区230。同样，npnBJT204的集电极端子c经由三元碳化物和三元氮化物的至少一个113和接触层112电耦合到n掺杂集电极区231。n掺杂发射极区230和n掺杂集电极区231在构成电耦合到基极端子b的npnBJT的基极的p阱区233中形成。
因为可一直到三元碳化物和三元氮化物的至少一个113的底侧达到与发射极区和集电极区230、231的低欧姆电接触，在发射极和集电极之间的横向电流流动的横截面可被增加，从而改进在发射极和集电极之间的电流流动。
在图6、7A、7B中的横向和垂直二极管的示例和双极晶体管可作为静电放电（ESD）保护器件被利用。
图9A和9B指的是制造半导体器件的方法。
图9A的示意性横截面视图图示半导体主体105的第一部分1051。氮化物和碳化物的至少一个155在半导体主体105的第一部分1051上形成。
参考图9B的示意性横截面视图，通过在第一部分1051上和在氮化物和碳化物的至少一个155上经由外延生长形成半导体主体105的第二部分1052来将氮化物和碳化物的至少一个155掩埋在半导体主体105中。根据一个实施例，通过选择性外延生长或外延横向过生长而形成第二部分1052。
根据实施例，碳化物和氮化物的至少一个的电导率被设置为大于3x106S/m。
根据另一实施例，沟槽193从第二部分1052的第一表面107表面被刻蚀到半导体主体105中一直到氮化物和碳化物的至少一个155。用（多个）导电材料填充沟槽193考虑到在氮化物和碳化物的至少一个155和在半导体主体105上方的布线区域之间的电互连。
根据实施例，碳化物和氮化物的至少一个155是AxByRz，A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一；B是Al、Si、P、S、Ga、Ge、As、Cd、In、Sn、Te和Pb之一；R是C和N之一；以及[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。
根据另一实施例，碳化物和氮化物的至少一个155的电导率大于3x106S/m。
根据另一实施例，碳化物和氮化物的至少一个155是掩埋在半导体主体105中的电布线。
虽然在本文图示和描述了特定的实施例，本领域中的普通技术人员将认识到，多种替换和/或等效实现可代替所示和所述的特定实施例，而不偏离本发明的范围。这个申请旨在涵盖本文讨论的特定实施例的任何改编或变化。因此，意图是本发明仅由权利要求及其等效形式限制。

Claims (20)

1.一种半导体器件，包括：
从第一表面延伸到半导体主体中的沟槽；以及
在所述沟槽中的三元碳化物和三元氮化物的至少一个。
2.如权利要求1所述的半导体器件，其中所述三元碳化物和所述三元氮化物的所述至少一个是AxByRz，其中A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一，其中B是Al、Si、P、S、Ga、Ge、As、Cd、In、Sn、Te和Pb之一，其中R是C和N之一，以及其中[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。
3.如权利要求1所述的半导体器件，其中所述三元碳化物和所述三元氮化物的所述至少一个完全填充所述沟槽。
4.如权利要求1所述的半导体器件，还包括在所述三元碳化物的所述至少一个与所述半导体主体之间的电介质。
5.如权利要求1所述的半导体器件，其中所述沟槽是包括所述三元碳化物和所述三元氮化物的所述至少一个作为电耦合到所述半导体主体的导电充填物的接触沟槽。
6.如权利要求5所述的半导体器件，还包括接触层，所述接触层包括在所述三元碳化物和所述三元氮化物的所述至少一个与半导体主体之间的硅化物和高掺杂半导体材料的至少一个。
7.一种半导体器件，包括：
具有相对的第一表面和第二表面的半导体主体；以及
被掩埋在所述半导体主体中的氮化物或碳化物的至少一个，其中所述半导体主体的第二部分在所述第一表面与所述氮化物和所述碳化物的所述至少一个之间，且所述半导体主体的第一部分在第二表面与所述氮化物和所述氮化物的所述至少一个之间，
其中所述氮化物和所述碳化物的所述至少一个的熔点大于900℃。
8.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个是二元或三元化合物。
9.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个是AxByRz，其中A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一，其中B是Al、Si、P、S、Ga、Ge、As、Cd、In、Sn、Te和Pb之一，其中R是C和N之一，以及其中[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。
10.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个的电导率大于3x106S/m。
11.如权利要求10所述的半导体器件，还包括掩埋在所述半导体主体中的电布线，所述电布线包括所述碳化物和所述氮化物的所述至少一个。
12.如权利要求11所述的半导体器件，还包括在所述电布线和所述半导体主体之间的接触层和电介质的至少一个。
13.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个是垂直地布置在所述第一表面处的高掺杂发射极区和漂移区之间的重组结构。
14.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个是横向布置在第一半导体元件的第一有源区域和第二半导体元件的第二有源区域之间的重组结构。
15.如权利要求7所述的半导体器件，其中所述碳化物和所述氮化物的所述至少一个是横向布置在晶体管单元阵列和结终止区域之间的过渡区域中的重组结构。
16.一种制造半导体的方法，所述方法包括：
在半导体主体的第一部分上形成氮化物和碳化物的至少一个；以及
通过在所述第一部分上和在所述氮化物和所述碳化物的所述至少一个上经由外延生长形成所述半导体主体的第二部分来将所述氮化物和所述碳化物的所述至少一个掩埋在所述半导体主体中。
17.如权利要求16所述的方法，其中所述第二部分通过选择性外延生长或外延横向过生长来形成。
18.如权利要求16所述的方法，其中所述碳化物和所述氮化物的所述至少一个的电导率大于3x106S/m。
19.如权利要求18所述的方法，还包括将沟槽从所述第二部分的表面刻蚀到所述半导体主体中一直到所述氮化物和所述碳化物的所述至少一个。
20.如权利要求16所述的方法，其中所述碳化物和所述氮化物的所述至少一个是AxByRz，其中A是Sc、Ti、Cr、V、Zr、Nb、Mo、Hf和Ta之一，其中B是Al、Si、P、S、Ga和Ge之一，其中R是C和N之一，以及其中[x,y,z]是[2,1,1]、[3,1,2]、[4,1,3]之一。
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