CN105322934A - 智能半导体开关 - Google Patents

智能半导体开关 Download PDF

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CN105322934A
CN105322934A CN201510409533.XA CN201510409533A CN105322934A CN 105322934 A CN105322934 A CN 105322934A CN 201510409533 A CN201510409533 A CN 201510409533A CN 105322934 A CN105322934 A CN 105322934A
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transistor
substrate
well area
semiconductor device
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CN105322934B (zh
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D·I·莫海
A·芬尼
A·阿波斯托尔
A·V·丹奇维
A·科布扎鲁
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Infineon Technologies AG
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Abstract

本公开涉及智能半导体开关。一种半导体器件包括半导体衬底，半导体衬底包括垂直晶体管并且具有第一类型的掺杂剂。晶体管的每个晶体管单元具有形成在衬底中的体区域并且具有第二类型的掺杂剂。体区域与衬底形成第一pn结。第一阱区域形成在衬底中并且具有第二类型的掺杂剂，从而与衬底形成第二pn结。开关将该第一阱区域连接至体区域。第二阱区域形成在衬底中并且具有第二类型的掺杂剂以与衬底形成第三pn结。检测电路集成在第二阱区域中并且用于检测第一pn结是否被反向偏置。开关将第一阱区域与晶体管单元的体区域连接或断开，并且当第一pn结被反向偏置时，开关被断开，并且当第一pn结未被反向偏置时，开关被闭合。

Description

智能半导体开关
技术领域
本公开涉及集成电子电路器件的领域，具体地涉及一种包括集成在一个半导体裸片中的MOS晶体管和附加电路的集成电子电路器件。
背景技术
许多功率半导体开关与附加的低功率模拟和数字电路组合在单个半导体芯片中。附加电路可以附加地包括，尤其，用于生成驱动器信号以激活和去激活功率半导体开关的驱动器电路、用于处理诸如芯片温度、输出电流之类的所测量的信号的传感器和测量电路以及用于与诸如微控制器等其他器件进行通信的电路。功率半导体开关经常被实现为垂直晶体管，诸如垂直MOSFET或者IGBT。垂直晶体管通常在半导体芯片的相对侧(顶侧和底侧)上具有功率电极(例如，在MOSFET的情况下，漏极电极和源极栅极，或者在IGBT的情况下，集电极电极和发射极电极)。
在这样的具有垂直功率晶体管的智能半导体开关中，衬底通常电连接至功率半导体开关的一个负载电流端子(例如，漏极端子、集电极端子)。例如，如果功率半导体开关是垂直MOS晶体管，则MOS晶体管的漏极电极被电连接至半导体衬底，并且因此晶体管的漏极电势也限定了衬底的电势。所提及的附加的模拟和数字电路也集成在半导体衬底中，其中电路部件通过pn结隔离而与周围衬底隔离。例如，衬底可以是n型掺杂的，并且所提及的附加电路可以被实现在形成于n型掺杂衬底(n衬底)内的p型掺杂阱(p阱)内。所得到的在n衬底和p阱之间的pn结在集成电路的操作期间被反向偏置，并且因此pn结将p阱中的电路部件与周围的n衬底电隔离。
发明内容
在此公开了一种半导体器件。根据第一示例，该器件包括掺杂有第一类型的掺杂剂的半导体衬底。由一个或多个晶体管单元组成的垂直晶体管形成在衬底中，并且每个晶体管单元具有形成在衬底中并且掺杂有第二类型的掺杂剂的体区域。体区域与周围的衬底形成第一pn结。至少第一阱区域形成在衬底中并掺杂有第二类型的掺杂剂以与衬底形成第二pn结。该第一阱区域经由半导体开关电连接至垂直晶体管的体区域。第二阱区域形成在衬底中并掺杂有第二类型的掺杂剂以与衬底形成第三pn结，并且检测电路至少部分地集成在第二阱区域中，并且被配置成用来检测第一pn结是否被反向偏置。半导体开关被配置成将晶体管单元的第一阱区域与体区域电连接或断开，其中当第一pn结被反向偏置时，该开关被驱动以断开，并且当第一pn结不被反向偏置时，该开关被驱动以闭合。
附图说明
参考下面的附图及描述可以更好地理解技术。附图中的部件不一定成比例；相反地，重点放在图示技术的原理上。而且，在附图中，相同的附图标记指代对应的部分。在附图中：
图1图示了作为用于开关电感负载的低侧开关的功率MOS晶体管的基本配置；
图2图示了在一个半导体芯片中的功率MOS晶体管和附加低功率电路的一个示例实施方式；
图3图示了根据一个实施例的包括通过pn结隔离与衬底隔离的垂直功率MOS晶体管和附加低功率电路的半导体器件；
图4图示了表示具有用于将p阱与功率晶体管的单元阵列去耦合的附加电路的图3的结构的电路图；
图5更详细地图示了图3的器件。
具体实施方式
图1图示了被配置成开关电感负载L的低侧半导体开关的基本应用。在本示例中，功率MOSFETT1被用作半导体开关。MOSFETT1与诸如栅极驱动器电路10之类的另外的模拟和数字电路一起集成在半导体芯片中。栅极驱动器电路10接收逻辑信号SIN，并被配置成生成用于将半导体开关接通和关断的对应的驱动器信号。在本示例中，驱动器电路10连接至MOSFETT1的栅极，并且生成合适的栅极电压或栅极电流作为驱动信号以激活或者去激活MOSFETT1的MOS沟道。当使用低侧开关时，MOSFETT1连接在第一供电节点和输出节点之间。第一供电节点通常为提供有地电势VGND的接地端子GND。输出节点通常连接至半导体芯片的相应的外部输出端子OUT。负载L连接在输出端子OUT和提供有供电电压VDD的第二供电端子SUP之间。供电电压VDD也可以用于提供集成在芯片中的另外的电路，诸如栅极驱动器10。然而，不同的电压供电也可以用于该目的。
当MOSFETT1激活时，输出端子OUT处的电压VOUT近似等于地电势VGND，并且跨负载L的电压降近似等于VDD。在正常操作下，MOSFETT1的本征反向二极管DR被反向偏置并且阻断。然而，在一些情况下，输出电压VOUT可以被迫为负值(相对于地电势VGND)，并且因此反向二极管DR可以变为(至少暂时地)正向偏置且导通。这样的情况可以是，尤其，由于静电放电(ESD)所致的供电端子处的干扰、与电感负载组合的供电电压的损耗等。虽然反向二极管的正向偏置对于MOSFETT1本身不一定成问题，但是它可以不利地影响集成在半导体芯片中的另外的(低功率)电路的操作。这些不利影响是在单个半导体芯片中包括垂直功率MOSFET和另外的(模拟和数字)电路的“智能功率开关”的特定设计的结果。
图2是半导体芯片的截面图，并且示意性地图示了包括垂直功率MOSFET以及另外的模拟和/或数字电路的智能功率开关的一个示例实施方式。这样的另外的电路可以包括，尤其，用于生成用于MOSFET的栅极信号的栅极驱动器电路、用于与外部控制器通信的通信电路、用于测量和处理表示待测物理参数(例如，温度、负载电流)的信号的测量电路等。半导体器件(例如，智能功率开关)包括半导体(硅)衬底10，半导体衬底10可以包括布置在其上的单晶硅外延层11。衬底10和外延层11掺杂有第一类型的掺杂剂。在本示例中，使用n型掺杂剂(例如，磷、砷等)。衬底10和外延层11一起被称为半导体本体1或者简单地称为芯片。几个掺杂阱区域12、22形成在半导体本体中。阱区域邻接半导体本体的顶表面并且在垂直方向上延伸至半导体本体1中。阱区域掺杂有第二类型的掺杂剂。在本示例中，使用p型掺杂剂(例如，硼、铝等)。p型掺杂阱区域也被称为p阱，其可以通过例如扩散或离子注入的方式形成。
多个p阱12形成由多个晶体管单元组成的(n沟道)MOSFETT1的体区域。p阱12和n型掺杂半导体本体形成第一pn结J1，第一pn结J1可以被视为MOSFETT1的本征反向二极管DR(参见图1)。应当注意的是，图2图示了截面，其中p阱12(体区域)在所描绘的截面平面中看起来是分离的。然而，p阱可以在另一截面平面中连贯地连接在一起使得形成一个连贯的体区域。类似地，单独的晶体管单元的漏极区域可以是由衬底10形成的一个连贯的漏极区域。然而，由多个(连贯的或不连贯的)晶体管单元组成的垂直晶体管是众所周知的，并且因此此处不再进一步讨论。
至少一个源极区域13被嵌入在p阱12中的至少一个p阱中。源极区域13掺杂有第一类型的掺杂剂。在本示例中，源极区域13被n型掺杂以形成n沟道MOSFET。如上文关于p阱12所提及的，源极区域13在所描绘的截面中看起来是分离的，但是可以在另一截面平面中连贯地连接在一起以便有效地形成一个连贯的源区域。然而，也不一定是这种情况。也可以在每个p阱12中嵌入体接触区域14。体接触区域14掺杂有与p阱相同类型的掺杂剂，但是通常施加更高的掺杂浓度以允许p阱12与布置在半导体本体的顶表面上的源极电极16之间的欧姆接触。源极区域13与周围的p阱13形成第二pn结J2，然而第二pn结J2通常通过布置在半导体本体的顶表面上并且直接将源极区域13和仅具有可忽略的欧姆电阻的体连接区域14连接的源极电极16短路。外延层11形成MOSFETT1的(n型掺杂)漂移区域，而衬底10形成MOSFETT1的漏极区域。通常，漂移区域中的掺杂浓度比漏极区域(衬底10)中的掺杂浓度低得多。每个晶体管单元的源极区域可以全部连接至MOSFETT1的外部源极端子。在本示例中，公共源极端子为接地端子GND。漏极区域(即，衬底10)连接至输出端子OUT(也参见图1)。
栅极电极15可以布置在半导体本体1的顶表面上。然而，栅极电极15与周围的半导体材料隔离。通常，氧化硅被用作绝缘材料。栅极电极15邻近体区域12的将源极区域13与漂移区域(形成在外延层11中)分离的部分布置。当栅极电极15被充电时，在体区域12中沿着栅极电极15生成导电沟道。在本示例中，栅极电极15形成在半导体本体的顶表面上，并且在被耗尽之前，沟道电流在垂直方向上基本平行于顶表面流向漏极电极。备选地，栅极电极也可以被布置在沟槽中。然而，沟槽晶体管众所周知并且因此本文不再进一步讨论。在本示例中，仅仅图示了一个晶体管单元。然而，功率MOSFET可以由多个(多达几千个)并联连接的(连贯的或不连贯的)晶体管单元组成。
如上文所提及的，另一个p阱22形成在半导体本体1中。如形成晶体管单元的体区域的p阱12，p阱22邻接半导体本体1的顶表面并且在垂直方向上延伸至半导体本体中。p阱22围闭另外的电路，例如，模拟和数字电路，另外的电路使用由p阱22与周围的n型掺杂的半导体本体1之间的pn结J2形成的隔离而被隔离。与体区域12类似，p阱22可以使用掺杂剂的扩散或离子注入形成。在其他电路部件之中，至少p型重掺杂阱接触区域24和n型掺杂供电接触区域23被嵌入在p阱22中。为了确保在正常操作期间pn结J2被反向偏置并因此操作为pn结隔离，阱接触区域24电连接至另外的p阱12(体区域)并且因此电连接至MOSFETT1的源极电极，而衬底10与漏极电极连接。由于在正常操作期间MOSFETT1的漏极电势高于源极电势，所以pn结J2通常被反向偏置并且将嵌入在p阱22中的电路与周围的n型掺杂半导体本体1隔离。供电接触区域23连接至提供供电电压的供电节点SUPINT，在本示例中为内部供电电压VDDint。阱接触区域24电连接至接地端子GND并且因此提供有地电势VGND。
图2的示例还图示了包括电阻器RESD、第一ESD保护电路31和第二ESD保护电路32的ESD保护结构。电阻器RESD连接在供电端子SUP与内部供电节点SUPINT之间；第一ESD电路31连接在供电端子SUP与地之间，而第二ESD电路32连接在内部供电节点SUP’与地之间。在图4中，栅极驱动器30也被符号化。栅极驱动器根据输入信号SIN生成提供至栅极电极15的栅极信号。栅极驱动器30可以集成在p阱22中并且提供有内部供电电压VDD。
如从图2中可以看出的，当输出电压VOUT为负时，pn结J1变为正向偏置，这可以由如上文所讨论的各种效应引起。作为结果，MOSFETT1的反向二极管DR变为正向偏置(并且因此导通)，并且电流从体区域12流至周围的外延层11中。类似地，pn结J2变为正向偏置(并且因此导通)，并且电流从p阱22流至外延层11中。然而，pn结J2是寄生双极结型晶体管(BJT)Q1的基极-发射极二极管，寄生双极结型晶体管(BJT)Q1由n型掺杂外延层11(发射极)、p阱22(基极)和嵌入在p阱22中的n型掺杂供电接触区域23(集电极)形成。因此，经过pn结J2的电流可以看成是激活寄生BJTQ1的基极电流。当激活时，BJTQ1具有例如约0.5V的集电极-发射极饱和电压VCE-sat。因此，假设输出电压VOUT(MOSFETT1的漏极电压)近似为-1.5V，并且供电端子SUP处的供电电压VDD为5.5V，则导致跨电阻器RESD的6.5V的电压降，对于RESD＝200欧姆，这将经过芯片的电流限制为32.5毫安。内部供电电压VDDint骤降至-1V。作为结果，栅极驱动器可能不能生成栅极信号以接通功率MOSFETT1；此外存储在驻留于p阱22中的电路中的所有数字信息可能丢失。如此，在这样的反向电流和负输出电压的情况下，包括芯片的器件可能不能工作。甚至pn结J1和J2的瞬时正向偏置可以导致嵌入在p阱22中的电路的重置。
例如，在一些情况下，形成所提及的pn结隔离的pn结可以变为正向偏置，这使得pn结隔离失效。作为结果，电流可以穿过n衬底与p阱之间的pn结，这可以对实现在所影响的p阱中的电路的操作产生负面影响。pn结隔离的所提及的正向偏置可以在各种情况下发生。例如，当利用低侧n沟道MOSFET开关电感负载时，漏极电极的电势相对于源极电极的电势可以变为负。负漏极电势导致负衬底电势，因此使得n衬底与其中形成的p阱之间的pn结隔离正向偏置。由于接地线中的电压降所致的地电势的偏移，类似的问题可以发生。此外，供电线中的干扰(例如，由于静电放电，ESD)也可以导致所提及的pn结隔离的正向偏置。
为了避免上文所讨论的问题，可以使用开关SW1将p阱12(体区域)与p阱22之间的连接中断。图3中图示了这种情况，除了p阱22(见图2)与功率晶体管T1的晶体管单元阵列的p阱12在横向上间隔开以及在p阱22与功率晶体管T1(即一个或多个p阱12)的一个或多个单元(单元阵列)之间形成另外的p阱42以外，图3与图2基本相同。另外的p阱42包括横向n沟道MOS晶体管(形成所提及的开关SW1)，横向n沟道MOS晶体管被配置成将p阱22(其中集成了低功率电路和逻辑电路)与形成功率晶体管T1的晶体管单元的体区域的p阱12连接(和断开)。横向MOS晶体管的体区域由p阱42形成，并且n区域41和n区域43分别形成晶体管的源极和漏极。p阱42还包括重掺杂体接触区域44，重掺杂体接触区域44经由低电阻电流路径(例如，金属或多晶硅)与源极区域电连接以有效地将MOS晶体管的源极和体短路。p阱可以进一步包括经由电阻器Rx耦合至外部供电端子SUP的n型掺杂区域46。与p阱22类似，p阱42和周围的n型掺杂硅(衬底10的外延层11)形成另一pn结J3。MOS晶体管(开关SW1)的栅极电极45布置在半导体本体的顶表面上，并且例如通过栅极氧化物层(图3中未示出)与其隔离。栅极信号SREV被提供给栅极电极45以根据栅极信号SREV接通和关断MOS晶体管。MOS晶体管(开关SW1)将在下文更加详细地讨论。
MOS晶体管的漏极区域43电连接至邻近的p阱22的阱接触区域24，并且MOS晶体管的源极区域41电连接至功率晶体管T1的体区域12，并且也因此电连接至接地端子GND。作为结果，p阱42中的MOS晶体管(开关SW1)被配置成根据栅极信号SREV将p阱22与功率晶体管T1的体区域连接或断开。
在一些示例中，开关SW1可以用于，一检测到反向导通(即，pn结J1(即二极管DR)的正向偏置)，就将p阱22(低功率和逻辑电路驻留在其中)与功率MOS晶体管T1的p型掺杂体区域断开。p阱42、包括在其中的n型掺杂区域46和电阻器RX一起被用作传感器电路以检测半导体器件的所提及的反向导通状态。与p阱22中的寄生双极晶体管Q1类似，p阱42中形成另外的寄生双极晶体管Q2。衬底10(外延层11)形成n型掺杂的发射极、p阱42形成p型掺杂的基极并且n型掺杂区域46形成双极晶体管Q2的集电极。图4图示了表示图3所示的器件的右部的电路图。
图4是表示图3的一部分的等效电路图，并且图示了功率MOS晶体管T1和反向二极管DR，反向二极管DR与MOS晶体管T1的漏极-源极电流路径并联连接。功率MOS晶体管T1的源极端子连接至接地端子GND，并且功率MOS晶体管T1的漏极端子连接至输出端子VOUT。图4还图示了p阱42中存在的寄生双极晶体管Q2。双极晶体管Q2的基极-发射极二极管(由pn结J2形成)也与功率MOS晶体管T1的漏极-源极电流路径并联连接。双极晶体管Q2的集电极(参见图3，n型掺杂区域46)经由电阻器RX连接至供电端子SUP。双极晶体管Q2的集电极处的电压用VX表示(也参见图3)。
当功率MOS晶体管T1的漏极电压(即输出电压VOUT)变为负并且因此反向二极管DR(pn结J1)变为正向偏置时，寄生双极晶体管Q2的基极-发射极二极管将一直被正向偏置，并且集电极电压VX将(从近似VDD)降低至接近输出电压VOUT。例如，VOUT＝-1.5V，VX＝-1V。因此，双极晶体管Q2的集电极处的所提及的电压摆幅指示器件的反向导通状态。因此，双极晶体管Q2和电阻器RX可以视为用于检测pn结J1和J2的反向偏置的检测电路(的一部分)。为了将p阱22与p阱12断开，使用电压VX生成用于断开开关SW1的栅极信号SREV(参见图3)。例如，电压VX可以施加至施密特触发器ST(具有迟滞的比较器)的输入，施密特触发器生成栅极信号SREV作为输出。当电压VX靠近VDD时，栅极信号SREV将呈现高电平以闭合开关SW1，并且当电压VX靠近VOUT(指示反向导通)时，栅极信号SREV将呈现低电平以断开开关SW1。由于迟滞，可以避免开关SW1的反复切换(toggling)。
此外，电压VX可以施加给另外的比较器OA的输入，比较器OA配置成将电压VX与参考电压VREF进行比较。当电压VX降低至参考电压VREF之下时，比较器输出将切换至高电平，高电平用于在反向导通期间将功率晶体管T1的激活以便减少反向二极管DR中的损耗。比较器OA的输出覆盖栅极驱动器30的输出。
图5图示了与图3本质上相同的器件，并且附加地图示了图4所示的施密特触发器ST和比较器OA。
虽然技术已经关于一个或者多个实施方式进行说明和描述，但是在不脱离所附权利要求书的精神和范围的情况下可以对所说明的示例做出变更和/或修改。特别是关于由上述部件或结构(组件、器件、电路、系统等)所执行的各种功能，用于描述这样的部件的术语(包括对“装置”的参考)旨在对应于执行所描述的部件的指定功能的任何部件或者结构(例如，功能上等价)，即便在结构上不等价于执行本文所说明的示例实施方式中的功能的所公开的结构，除非另外指明。另外，虽然特定特征可能已经关于若干实施方式中的一个实施方式被公开，但是如可能对于任何给定或者特定应用所期望且有利的，这样的特征可以与其他实施方式中的一个或者多个其他特征组合。此外，就详细描述或者权利要求书中使用术语“包含了”、“包含”、“具有了”、“具有”、“含有”或其变形而言，这样的术语以类似于术语“包括”的方式旨在是包括性的。

Claims (12)

1.一种半导体器件，包括：
半导体衬底，掺杂有第一类型的掺杂剂；
垂直晶体管，由一个或者多个晶体管单元组成，每个晶体管单元具有形成在所述衬底中并且掺杂有第二类型的掺杂剂的体区域；所述体区域与周围的衬底形成第一pn结；
至少一个第一阱区域，形成在所述衬底中并且掺杂有第二类型的掺杂剂以与所述衬底形成第二pn结，所述第一阱区域经由半导体开关电连接至所述垂直晶体管的所述体区域；
第二阱区域，形成在所述衬底中并且掺杂有第二类型的掺杂剂以与所述衬底形成第三pn结；
以及检测电路，至少部分地集成在所述第二阱区域中并且被配置成检测所述第一pn结是否被反向偏置，
其中所述半导体开关被配置成将所述第一阱区域与所述晶体管单元的所述体区域电连接或断开，其中当所述第一pn结被反向偏置时，所述开关被驱动以断开，并且当所述第一pn结不被反向偏置时，所述开关被驱动以闭合。
2.根据权利要求1所述的半导体器件，
其中所述半导体开关包括另外的MOS晶体管，所述另外的MOS晶体管是集成在所述第二阱区域中的横向晶体管；
其中所述第二阱区域电耦合至所述垂直晶体管的所述体区域。
3.根据权利要求2所述的半导体器件，
其中所述第二阱区域是所述另外的MOS晶体管的体区域。
4.根据权利要求2所述的半导体器件，
其中所述检测电路被配置成根据所述第一pn结是否被反向偏置来生成用于激活或者去激活所述另外的MOS晶体管的栅极信号。
5.根据权利要求1所述的半导体器件，
其中所述第二阱区域包括集电极区域，所述集电极区域掺杂有所述第一类型的掺杂剂以形成双极晶体管；所述第二阱区域为所述双极晶体管的基极，并且所述半导体衬底为所述双极晶体管的发射极。
6.根据权利要求5所述的半导体器件，其中所述双极晶体管的所述集电极区域经由电阻器耦合至供电电势。
7.根据权利要求1所述的半导体器件，
其中所述第一阱区域包括如下各项中的至少一项：模拟电路、数字逻辑电路、栅极驱动器电路、通信电路，上述电路通过由所述第二pn结提供的pn结隔离而与所述衬底隔离。
8.根据权利要求5所述的半导体器件，其中所述集电极区域连接至触发电路的输入，所述触发电路被配置成生成提供至所述半导体开关的驱动器信号。
9.根据权利要求5所述的半导体器件，其中所述集电极区域连接至比较器的输入，所述比较器被配置成当所述集电极区域处的电压降低至参考电压之下时生成用于激活所述垂直晶体管的所述晶体管单元的输出。
10.根据权利要求1所述的半导体器件，其中所述第一阱区域和所述第二阱区域在横向方向上间隔开，因此通过掺杂有第一类型的掺杂剂的所述衬底分离。
11.根据权利要求1所述的半导体器件，其中所述垂直晶体管由多个晶体管单元组成；所述晶体管单元的所述体区域彼此电连接。
12.根据权利要求11所述的半导体器件，其中所述晶体管单元的所述体区域连贯地连接在一起。
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