CN105322925B - A kind of hysteresis circuitry and its working method - Google Patents
A kind of hysteresis circuitry and its working method Download PDFInfo
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- CN105322925B CN105322925B CN201510130225.3A CN201510130225A CN105322925B CN 105322925 B CN105322925 B CN 105322925B CN 201510130225 A CN201510130225 A CN 201510130225A CN 105322925 B CN105322925 B CN 105322925B
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Abstract
The embodiment of the present invention provides a kind of hysteresis circuitry, and the hysteresis circuitry includes the first input voltage Vref, the second input voltage Vin, the hysteresis circuitry further include: first switch voltage Vo, second switch voltage Vob, first resistor R1, second resistance R2, input are to pipe and switching tube；The first input voltage VrefWith the second input voltage VinFirst resistor R1, second resistance R2 are accessed to pipe by input；Both ends of the both ends of the switching tube respectively with the second resistance R2 are attached；The grid of the first switch voltage Vo, second switch voltage Vob connection switch pipe.The embodiment of the present invention also provides a kind of working method of hysteresis circuitry.
Description
Technical field
The present invention relates to field of analog integrated circuit more particularly to a kind of hysteresis circuitries and its working method.
Background technique
Present inventor at least has found exist in the related technology during realizing the embodiment of the present application technical solution
Following technical problem:
In practical applications, the problem of process corner, the variation of temperature, the variation of resistance value all can generate shadow to comparator
It rings, so that comparator works in noise circumstance, if comparator is sufficiently fast and the amplitude of noise is sufficiently large, output end
There can be noise.Therefore we need a kind of comparator of band sluggishness, and hysteresis range stablize it is adjustable, not by ambient temperature etc. because
The interference of element.
The sluggish circuit design of formation more commonly used at present includes: that one is the sides that positive feedback is used outside comparator
Formula forms sluggishness, and one is sluggishness is formed by the way of positive feedback inside comparator, there are also one is comparators by changing
Become the reference voltage of input terminal to form sluggishness.Wherein, but requirement of the first comparator to gain is very high, and application range has
Limit.It is that the sluggish width of comparator is unable to flexible modulation in second.The third comparator needs to generate two benchmark, circuit cost
Greatly, and reference voltage is once set arbitrarily to change, sluggish not flexible.
Therefore, it is necessary to propose a kind of improved hysteresis circuitry to overcome the above problem.
Summary of the invention
In view of this, height can be generated the main purpose of the present invention is to provide a kind of hysteresis circuitry and its working method
The amount of hysteresis of precision, and amount of hysteresis is not influenced by factors such as technological temperatures.
In order to achieve the above objectives, the technical solution of the embodiment of the present invention is achieved in that
The embodiment of the invention provides a kind of hysteresis circuitry, the hysteresis circuitry includes the first input voltage Vref, and second
Input voltage Vin, the hysteresis circuitry further include: and first switch voltage Vo, second switch voltage Vob, first resistor R1, second
Resistance R2, input are to pipe and switching tube；
The first input voltage VrefWith the second input voltage VinFirst resistor R1, the second electricity are accessed to pipe by input
Hinder R2；
Both ends of the both ends of the switching tube respectively with the second resistance R2 are attached；
The first switch voltage Vo, second switch voltage Vob connect the grid of the switching tube.
In above scheme, the input constitutes Guan You tetra- PMOS transistor mp4 and the 5th PMOS transistor mp5, institute
State the first input voltage VrefFirst resistor R1, the second input voltage V are accessed by the 4th PMOS transistor mp4inPass through
Five PMOS transistor mp5 access second resistance R2.
In above scheme, the first load of drain electrode connection of the 4th PMOS transistor mp4, the 5th PMOS transistor
The drain electrode of mp5 is connected to the second load；Wherein, first load constitutes current mirror with second load.
In above scheme, the switching tube is made of the 6th PMOS transistor mp6 and third NMOS transistor mn3.
In above scheme, the drain electrode of the source electrode of the 6th PMOS transistor mp6 and the third NMOS transistor mn3 connect
It is connected to one end that the second resistance R2 is connect with the first resistor R1, the drain electrode of the 6th PMOS transistor mp6 and institute
The source electrode for stating third NMOS transistor mn3 is connected to the other end of the second resistance R2.
The embodiment of the invention provides a kind of working method of hysteresis circuitry, the working method is applied to claim 1
To hysteresis circuitry described in any one of 5 claims, the working method includes: the first input voltage VrefWith second
Input voltage VinFirst resistor R1, second resistance R2 are accessed to pipe by input；
As the second input voltage VinGreater than the first voltage Vref, and when switching tube conducting, described second is defeated
Enter voltage VinWith the first voltage VrefHysteresis voltage VT1For VT1=Vin-Vref=Ib·R1；
As the second input voltage VinLess than the first voltage Vref, and when switching tube disconnection, described second is defeated
Enter voltage VinWith the first voltage VrefHysteresis voltage VT2For VT2=Vin-Vref=Ib·(R1-R2)；
Wherein, IbFor the half of the tail current of input hysteresis circuitry.
In above scheme, the working method further include:
When the first switch voltage Vo is low level, and the second switch voltage Vob is high level, the switching tube
Closure；
When the first switch voltage Vo is high level, and the second switch voltage Vob is low level, the switching tube
It disconnects.
The embodiment of the present invention provides a kind of hysteresis circuitry and its working method, and the hysteresis circuitry includes the first input voltage
Vref, the second input voltage Vin, the hysteresis circuitry further include: first switch voltage Vo, second switch voltage Vob, first resistor
R1, second resistance R2, input are to pipe and switching tube；The first input voltage VrefWith the second input voltage VinPass through input pair
Pipe accesses first resistor R1, second resistance R2；Both ends of the both ends of the switching tube respectively with the second resistance R2 are connected
It connects；The first switch voltage Vo, second switch voltage Vob connect the grid of the switching tube.Overcome as a result, in the prior art
Method by changing reference voltage generates sluggishness, and the precision for providing a kind of amount of hysteresis is very high, not by temperature, process corner
It influences, the free controllable hysteresis circuitry of adjustable extent, while having saved area.
Detailed description of the invention
Fig. 1 is a kind of circuit diagram of hysteresis circuitry provided in an embodiment of the present invention；
Fig. 2 is using a kind of circuit diagram of the comparator of hysteresis circuitry provided in an embodiment of the present invention；
Fig. 3 is a kind of retarding window schematic diagram of hysteresis circuitry provided in an embodiment of the present invention；
Fig. 4 is the circuit diagram provided in an embodiment of the present invention for generating reference current generating circuit.
Specific embodiment
In embodiments of the present invention, the first input voltage VrefWith the second input voltage VinPipe is accessed by input
First resistor R1, second resistance R2；Both ends of the both ends of the switching tube respectively with the second resistance R2 are attached；It is described
The grid of first switch voltage Vo, second switch voltage Vob connection switch pipe.
Below by drawings and the specific embodiments, the present invention is further elaborated.
Fig. 1 is a kind of circuit diagram of hysteresis circuitry provided in an embodiment of the present invention, the structure institute in dotted line as shown in figure 1
Show, the hysteresis circuitry includes the first input voltage Vref, the second input voltage Vin, first switch voltage Vo, second switch voltage
Vob, first resistor R1, second resistance R2, input are to pipe and switching tube；The first input voltage VrefWith the second input voltage
VinFirst resistor R1, second resistance R2 are accessed to pipe by input；The both ends of the switching tube respectively with the second resistance R2
Both ends be attached；The grid of the first switch voltage Vo, second switch voltage Vob connection switch pipe.
Wherein, the input constitutes Guan You tetra- PMOS transistor mp4 and the 5th PMOS transistor mp5, and described first
Input voltage VrefFirst resistor R1 is accessed by the 4th PMOS transistor mp4, second input voltage vin passes through the 5th
PMOS transistor mp5 accesses second resistance R2.The first load of drain electrode connection of the 4th PMOS transistor mp4, the described 5th
The drain electrode of PMOS transistor mp5 is connected to the second load；Wherein, first load constitutes current mirror with second load.
The switching tube is made of the 6th PMOS transistor mp6 and third NMOS transistor mn3.The 6th PMOS transistor mp6's
The drain electrode of source electrode and the third NMOS transistor mn3 are connected to the second resistance R2 is connect with the first resistor R1 one
End, the drain electrode of the 6th PMOS transistor mp6 and the third NMOS transistor mn3 source electrode are connected to the second resistance R2
The other end.
The embodiment of the present invention also provides a kind of working method of above-mentioned hysteresis circuitry, and the working method is for above-mentioned slow
Stagnant circuit, the working method include: the first input voltage VrefWith the second input voltage VinBy input to pipe access first
Resistance R1, second resistance R2；As the second input voltage VinGreater than the first voltage Vref, and when switching tube conducting,
The second input voltage VinWith the first voltage VrefHysteresis voltage VT1For VT1=Vin-Vref=Ib·R1；When described
Two input voltage VinLess than the first voltage Vref, and when switching tube disconnection, the second input voltage VinWith it is described
First voltage VrefHysteresis voltage VT2For VT2=Vin-Vref=Ib·(R1-R2)；Wherein, IbFor the tail electricity for inputting hysteresis circuitry
The half of stream.
The working method further include: when the first switch voltage Vo is low level, the second switch voltage Vob is
When high level, the switching tube closure；When the first switch voltage Vo is high level, the second switch voltage Vob is low
When level, the switching tube is disconnected.
Hysteresis circuitry provided in an embodiment of the present invention and its working method are further elaborated below with reference to Fig. 1.
In hysteresis circuitry shown in Fig. 1, the first input voltage VrefFor benchmark voltage, the second input voltage VinIt is one
Variable voltage, the first input voltage VrefWith the second input voltage VinIt is separately input to constitute and input to the mp4 and mp5 of pipe
Grid, wherein equal (W/L) p4=(W/L) p5 of the breadth length ratio of mp4 and mp5, the hysteresis circuitry is to the first input voltage VrefWith
Second input voltage VinIt is compared.
In Fig. 1, between first resistor R1 connecting node A and node C, second resistance R2 be connected to node B and node C it
Between.Wherein, R1 is greater than R2, and first resistor R1 is consistent with the type of second resistance R2.6th PMOS transistor mp6 and third
NMOS transistor mn3 constitutes the switching tube of hysteresis circuitry, and the grid of mp6 is controlled by first switch signal Vo, when first switch is believed
When number Vo is low level, mp6 closure；When first switch signal Vo is high level, mp6 is disconnected, and the grid of mn3 is by second switch
Signal Vob control, when second switch signal Vob is high level, mn3 closure, when second switch signal Vob is low level,
Mn3 is disconnected.
Below by taking hysteresis circuitry shown in FIG. 1 is applied in comparator circuit shown in Fig. 2 as an example, to the embodiment of the present invention
The hysteresis circuitry of offer is further elaborated.
Here, in the hysteresis circuitry shown in FIG. 1 comparator circuit shown in Fig. 2 as sluggish unit application, in Fig. 1
Tail current is the electric current of the second PMOS transistor mp2 in Fig. 2, the load in Fig. 1 be the 4th NMOS transistor mn4 in Fig. 2 and
5th NMOS transistor mn5.
As shown in Fig. 2, the first NMOS transistor mn1 and the second NMOS transistor mn2 constitutes the 1:1 current mirror of nmos,
Mp1, mp2, mp3 constitute pmos current mirror, ratio 1:2:1, the 4th NMOS transistor mn4 and the 5th NMOS transistor mn5 structure
It is the active load of sluggish unit at 1:1 current mirror.
In Fig. 2,
Imp2=2Imp1=2Imn2=2Imn1=2Ib (1)
Wherein, Imp2For the electric current of mp2, Imp1For the electric current of mp1, IbFor the input current of comparator.
Here, transistor mn1/mn2, transistor mp1/mp2/mp3 and transistor mn4/mn5 constitute first order comparator,
Transistor mn6 and mp3 constitute second level comparator, and comparator primary output signal is VD, signal VDAfter level-one phase inverter
Signal is signal VE, signal VEIt is signal V using the signal after level-one phase inverterF.Signal VFFor the comparator Jing Guo shaping
Output.
In comparator shown in Fig. 2, as the second input voltage VinValue from be greater than the first input voltage VrefValue start
When slowly reducing, the output of comparator is converted from high to low；At this point, first switch signal Vo be it is low, second switch signal Vob is
Closure, second resistance R2 short circuit, using composition input when equilibrium state to the 4th of pipe is connected in the switching tube that height, mn3 and mp6 are constituted
PMOS transistor mp4 and the flowed through electric current of the 5th PMOS transistor mp5 are equal, are all the electric current I of mp2mp2Half, by formula
It (1) is all Ib known to.
Because
Wherein, VsgFor source-grid voltage of PMOS transistor, VthIt is the threshold voltage of PMOS transistor, here,β is transconductance parameters, μpIt is electron mobility, CoxIt is the gate oxide capacitance of unit area, W/L is transistor
Breadth length ratio.Wherein μp,CoxIt is constant.
Due to the V of mp4 and mp5thEqual, β value is equal, therefore, the source mp4-grid voltage Vsg(mp4)With the source mp5-grid electricity
Press Vsg(mp5)There are relationships:
Vsg(mp4)=Vsg(mp5) (3)
That is VA-Vref=VC-Vin (4)
Wherein, VAFor the voltage at node A, VCFor the voltage at node C.
Then as the second input voltage VinGreater than the first input voltage VrefWhen hysteresis voltage VT1Are as follows:
VT1=Vin-Vref=VC-VA=Ib·R1 (5)
As the second input voltage VinValue from less than the first input voltage VrefValue when slowly increasing, comparator output from
It is low to be converted to height；At this point, first switch signal Vo is height, second switch signal Vob is low, then mn3 and mp6 switch disconnection, the
Two resistance R2 access hysteresis circuitry, equal using the electric current that the mp4 and mp5 of pipe are flowed through in composition input when equilibrium state, same root
Formula (3) are then released according to formula (2),
It can be obtained according to formula (3):
VA-Vref=VB-Vin(6) here, VBFor the voltage at node B.
Then as the second input voltage VinLess than the first input voltage VrefWhen hysteresis voltage VT2For
VT2=Vin-Vref=VB-VA=(VC-Ib·R2)-(VC-Ib·R1)=Ib·(R1-R2) (7)
Wherein, in the course of work of the comparator, the retarding window of hysteresis circuitry is as shown in figure 3, in the second input electricity
Press VinValue from be greater than the first input voltage VrefValue start during slowly reducing, as the second input voltage VinEqual to VT1
When, the output of comparator is low.In the second input voltage VinValue from less than the first input voltage VrefValue start slowly to increase
During, as the second input voltage VinEqual to VT2When, the output of hysteresis circuitry is height.Here, first as reference voltage
Input voltage VrefValue be located at VT1And VT2Between.
In practical applications, as the first input voltage VrefValue be located at VT1And VT2When intermediate, hysteresis circuitry is bilateral slow
It is stagnant, in addition, the first input voltage VrefValue also can be equal to VT2Or it is equal to VT1, to realize unilateral hysteresis.
In embodiments of the present invention, reference current I in a kind of generation Fig. 2 is providedbReference current generating circuit circuit
Figure, as shown in figure 4, being mainly made of a buffer buffer and resistance, the structure of the reference current generating circuit such as Fig. 4
It is shown.
Reference voltage vref_1p2v from bandgap by buffer output signal the first offset signal vb and
An output end of second offset signal vb1, buffer is sequentially connected to the 41st PMOS transistor mp41 and the 42nd
The another output of PMOS transistor mp42, buffer are sequentially connected to the 43rd PMOS transistor mp43 and the 44th
PMOS transistor mp44, wherein mp41/mp42/mp43/mp44 constitutes cascade cascode current mirror.The grid of mp41 with
The collocation structure that the 5th resistance R5 and capacitor C, the 5th resistance R5 and capacitor C constitute buffer is connected between the drain electrode of mp43.
In addition, the drain electrode of mp43 is additionally coupled to 3rd resistor R3, the 4th resistance R4 and trims electricity for constitute the resistance unit trimmed
It hinders the first Rtrim1, second trim resistance Rtrim2, R3, R4, Rtrim1 and Rtrim2 constitute resistance unit.
Here, the working method of the circuit specifically:
The input terminal of Buffer is separately connected Vref_1p2v and Vp, is 1.2V reference voltage Vref_ from bandgap
1p2v acts on the grid of mp41 and mp42 by the offset signal of buffer output signal two vb and vb1, vb, and vb1 is acted on
The grid of mp43 and mp44.In order to guarantee that enough phase field degree, the 5th resistance R5 and capacitor C constitute the compensation knot of buffer
Structure.
3rd resistor R3, the 4th resistance R4, first trim resistance Rtrim1 and second and trim resistance Rtrim2 composition resistance
Unit, wherein Rtrim1 and Rtrim2 is respectively in the upper surface of signal Vp and lower EDS maps, respectively by I2C signal set's<7:0>
Signal and reverse signal control in the same direction.Rtrim1, Rtrim2 are the stability in order to guarantee output voltage Vref_2p3v, can be with
Realize that in a certain range two-way trims.Mp41/mp42/mp43/mp44 constitutes cascode current mirror.Proportionate relationship is K:
1。
Here, K value is proportionality coefficient, and size is determined by the power consumption and area of circuit, and the value range of K can be 1 to 10
Between.
The electric current I of Mp431Are as follows:
Wherein, 1.2 be Vref_1p2v value.
Then
Here.The type of R3, R4 in Fig. 4 are identical with the resistance type of R1, R2 in Fig. 1.Therefore, pass through formula (9)
Formula (5) and (7), which can be released, to be had:
In actual use, identical with the resistance type of R1, R2 in Fig. 1 due to R3, R4, Rtrim, Rtrim2, resistance
Process corner variation cancel out each other, such VT1And VT2Variation influenced very little by the variation of temperature, technique, precision is very high.It is sluggish
The variation of amount can realize that adjustable extent freedom degree is big by changing the size of resistance.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.Therefore, protection scope of the present invention should be based on the protection scope of the described claims.
Claims (6)
1. a kind of hysteresis circuitry, the hysteresis circuitry includes the first input voltage Vref, the second input voltage Vin, which is characterized in that
The hysteresis circuitry further include: first switch voltage Vo, second switch voltage Vob, first resistor R1, second resistance R2, input
To pipe and switching tube, the input constitutes Guan You tetra- PMOS transistor mp4 and the 5th PMOS transistor mp5, the switch
Guan You six PMOS transistor mp6 and third NMOS transistor mn3 are constituted；
The first input voltage VrefWith the second input voltage VinFirst resistor R1, second resistance R2 are accessed to pipe by input；
Both ends of the both ends of the switching tube respectively with the second resistance R2 are attached；
The first switch voltage Vo, second switch voltage Vob connect the grid of the switching tube.
2. hysteresis circuitry according to claim 1, which is characterized in that the first input voltage VrefPass through the 4th PMOS
Transistor mp4 accesses first resistor R1, the second input voltage VinSecond resistance is accessed by the 5th PMOS transistor mp5
R2。
3. hysteresis circuitry according to claim 2, which is characterized in that the drain electrode of the 4th PMOS transistor mp4 connects
First load, the drain electrode of the 5th PMOS transistor mp5 are connected to the second load；Wherein, first load and described the
Two loads constitute current mirror.
4. hysteresis circuitry according to claim 1, which is characterized in that the source electrode of the 6th PMOS transistor mp6 and institute
The drain electrode for stating third NMOS transistor mn3 is connected to one end that the second resistance R2 is connect with the first resistor R1, described
The drain electrode of 6th PMOS transistor mp6 and the source electrode of the third NMOS transistor mn3 are connected to the another of the second resistance R2
One end.
5. a kind of working method of hysteresis circuitry, which is characterized in that the working method is applied to any in Claims 1-4
Hysteresis circuitry described in item claim, the working method includes: the first input voltage VrefWith the second input voltage Vin
First resistor R1, second resistance R2 are accessed to pipe by input；
As the second input voltage VinGreater than the first voltage Vref, and when switching tube conducting, the second input electricity
Press VinWith the first voltage VrefHysteresis voltage VT1For VT1=Vin-Vref=Ib·R1；
As the second input voltage VinLess than the first voltage Vref, and when switching tube disconnection, the second input electricity
Press VinWith the first voltage VrefHysteresis voltage VT2For VT2=Vin-Vref=Ib·(R1-R2)；
Wherein, IbFor the half of the tail current of input hysteresis circuitry.
6. working method according to claim 5, which is characterized in that the working method further include:
When the first switch voltage Vo is low level, and the second switch voltage Vob is high level, the switching tube is closed
It closes；
When the first switch voltage Vo is high level, and the second switch voltage Vob is low level, the switching tube is disconnected
It opens.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013884A (en) * | 2006-11-24 | 2007-08-08 | 华中科技大学 | Unilateral hysteresis comparator |
| CN201011715Y (en) * | 2006-11-24 | 2008-01-23 | 华中科技大学 | Delay Comparator |
| CN103199846A (en) * | 2013-03-26 | 2013-07-10 | 浙江工业大学 | Complementary metal-oxide-semiconductor transistor (CMOS) delaying over-temperature protective circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6894552B2 (en) * | 2003-02-28 | 2005-05-17 | Teradyne, Inc. | Low-jitter delay cell |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013884A (en) * | 2006-11-24 | 2007-08-08 | 华中科技大学 | Unilateral hysteresis comparator |
| CN201011715Y (en) * | 2006-11-24 | 2008-01-23 | 华中科技大学 | Delay Comparator |
| CN103199846A (en) * | 2013-03-26 | 2013-07-10 | 浙江工业大学 | Complementary metal-oxide-semiconductor transistor (CMOS) delaying over-temperature protective circuit |
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