CN201011715Y

CN201011715Y - Delay Comparator

Info

Publication number: CN201011715Y
Application number: CNU200620157551XU
Authority: CN
Inventors: 邹雪城; 刘政林; 郑朝霞; 尹璐; 田欢; 骞海荣; 王潇; 涂熙
Original assignee: Huazhong University of Science and Technology
Current assignee: Huazhong University of Science and Technology
Priority date: 2006-11-24
Filing date: 2006-11-24
Publication date: 2008-01-23
Anticipated expiration: 2016-11-24

Abstract

The utility model discloses a hysteresis comparator, and the circuit is designed for the protection circuit or the detection circuit in a low voltage and low power chip, which comprises a current source I1, two input MOS tubes, three load MOS tubes and a hysteresis adjuster for adjusting the threshold of the comparator. When the input MOS tube is an NMOS tube, the load MOS tube uses a PMOS tube, and vice versa. Moreover, the single side threshold of the circuit is not relative to the parameters of the circuit components, namely, the single side threshold can be determined accurately only by fixing an input of the comparator; having a hysteresis circuit of the hysteresis comparator formed asymmetric positive and negative feedback circuits, the circuit can generate the threshold voltages and completes the comparing function. Besides, the circuit is a comparatively separate part, which is further provided with appropriate positive and negative feedback branches, an output branch, and an MOS tube and a resistance providing static protection effect.

Description

Hysteresis comparator

Technical Field

The utility model belongs to the analog integrated circuit field relates to a hysteresis comparator, especially is suitable for and uses in the integrated circuit chip.

Background

In the application field of integrated chip, in order to ensure the reliability of chip under normal and abnormal use condition, its control circuit should include protection and detection circuit. The protection circuit has the functions of self protection and load protection, and once a fault occurs, the chip circuit stops working of the comparator. The detection circuit detects different working states of the circuit, so that the chip can make appropriate response aiming at different working states.

A conventional hysteretic comparator with internal positive feedback is shown in fig. 1. The comparator is used for realizing hysteresis at the input stage of a high-gain open-loop comparator by using internal positive feedback. The comparator is composed of a differential input pair consisting of N-channel MOS transistors N1 and N2; diode-connected P-channel MOS transistors P1 and P2 as load; the constant current source I1 is used as a current source and forms a positive feedback loop with the internal P-channel MOS transistors P3 and P4 to form a hysteresis comparator.

The circuit has two feedback paths in common, the first feedback path is series current feedback through a common source node of the transistors N1 and N2, and the feedback path is negative feedback; the second is parallel voltage feedback connecting the P3 and P4 source-drains, and this feedback path is positive feedback. When the positive feedback coefficient is smaller than the negative feedback coefficient, the whole circuit shows negative feedback and loses the hysteresis effect; when the positive feedback coefficient is larger than the negative feedback coefficient, the whole circuit will exhibit positive feedback, and at the same time hysteresis will occur in the voltage transmission curve.

The comparator has the advantages that the four tubes of the decision stage are symmetrical pairwise, namely the width-length ratios of P1 and P2 are the same, and the width-length ratios of P3 and P4 are the same, so that the threshold voltages of the comparator are symmetrically distributed relative to the input reference voltage; in practice, particularly under low voltage and low power consumption conditions, it may be required that the threshold voltage of the comparator is not necessarily symmetrical with respect to the reference voltage. Secondly, the positive threshold and the negative threshold of the comparator shown in fig. 1 are both related to the width-to-length ratio of the device, and are affected by the process and the temperature, and in practice, the positive/negative threshold of the comparator and the reference voltage may be required to be completely the same and have a certain hysteresis effect. Therefore, a one-sided hysteretic comparator is required.

Disclosure of Invention

An object of the utility model is to provide a hysteresis comparator, this comparator has the hysteresis function of high accuracy unilateral.

The utility model provides a hysteresis comparator, it includes NMOS pipe N1 and N2, PMOS pipe P1, P2, P5 and hysteresis regulator, wherein, the hysteresis regulator comprises PMOS pipe P6 for adjust the threshold value of comparator; the NMOS transistors N1 and N2 are symmetrical, the width-to-length ratios of the PMOS transistors P1, P2 and P5 are equal, and the width-to-length ratio of the PMOS transistor P6 is larger than that of the PMOS transistor P1; NMOS tube N1 tube grid as positive input end V _in1 The grid of N2 NMOS transistor is used as negative input end V _in2 The sources of the current sources are connected, and the current sources are connected with the positive end of a tail current source I1, and the negative end of the current source I1 is grounded; the drain electrode of the NMOS tube N1 is connected with the drain electrode of the PMOS tube P1 and is connected with the drain electrode of a PMOS tube P6 in the hysteresis regulator; the drain electrode of the PMOS pipe P1 is connected with the grid electrode to form diode connection; the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and is connected to the drain electrode of the PMOS tube P5; the drain electrode of the PMOS tube P2 is connected with the grid electrode thereof, the grid electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P5, and the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P2; the source electrodes of the PMOS tubes P1, P2, P5 and P6 are connected and are connected with a power supply V _DD (ii) a Negative output end V of PMOS pipe P6 _O1 A positive output end V of the PMOS tube is led out from the drain electrode of the NMOS tube N1 _O2 And the drain electrode of the NMOS tube N2 is led out.

The utility model discloses a hysteresis comparator circuit is improved by the comparator that inside positive feedback realized hysteresis and is formed, and the positive feedback return circuit by asymmetric structure constitutes this hysteresis comparator circuit's threshold voltage and produces the part, adds the output stage circuit that provides corresponding output voltage swing and reasonable output resistance again, has constituteed the core part of this hysteresis comparator circuit jointly. By adjusting the threshold voltage regulator, a fixed threshold voltage can be realized _ref And another effect that the threshold voltage can be adjusted. Thus can beRealize hysteresis voltages V of different magnitudes _HYS 。

When all the parameters of the hysteresis comparison circuit are set, the circuit can work in the chip under the condition of low-voltage power supply. For example, when the hysteresis comparison circuit is applied to a switching power supply management chip, the output voltage is detected in the soft start process, and when the output voltage is lower than the set overturning threshold value of the circuit, the circuit outputs a corresponding control signal to enable the circuit to be continuously in the soft start stage; when the output voltage is higher than the set overturning threshold value of the circuit, the circuit outputs a corresponding control signal to enable the circuit to be in a normal working stage. The utility model provides a hysteresis comparator can also work in low voltage protection module, when output voltage is less than the upset threshold value that this circuit set for, most module in the chip will be turn-offed to the corresponding control signal of circuit output to play the guard action. Since the negative threshold in the circuit is only related to the input voltage, the single-side threshold can be accurately determined without being influenced by the circuit device process. And the other threshold voltage is only determined by the width-to-length ratio of the feedback tube, so that the hysteresis quantity of the hysteresis circuit can be accurately controlled to be about 10 mV. The circuit is added with a positive feedback loop to enable the circuit to have an acceleration effect, the gain of the comparator is increased, and the precision can reach 0.2uV. The circuit reduces static power consumption in the circuit, and is about 50uW approximately. The circuit can work in low-voltage low-power consumption mode, and is suitable for being integrated with and used by a chip.

Drawings

FIG. 1 is a schematic circuit diagram of a conventional hysteresis comparator circuit;

FIG. 2 is a schematic diagram of the circuit of the present invention with adjustable threshold for the hysteresis comparator with NMOS input;

FIG. 3 is a schematic diagram of a hysteresis comparator circuit corresponding to FIG. 2 using PMOS inputs;

fig. 4 is a circuit diagram corresponding to one embodiment of fig. 3.

Detailed Description

The following description will be made by way of typical application examples in conjunction with the accompanying drawings.

The utility model discloses hysteresis comparator includes current source I1, two input MOS pipes, three load MOS pipe and hysteresis regulator 11, and wherein hysteresis regulator 11 is used for adjusting the threshold value of comparator. When the input MOS tube is an NMOS tube, the load MOS tube adopts a PMOS tube; when the input MOS tube is a PMOS tube, the load MOS tube adopts an NMOS tube.

When the input MOS transistor is an NMOS transistor, the load MOS transistor is a PMOS transistor, and the hysteresis regulator 11 is implemented by using a PMOS transistor P6, the specific structure of the circuit is shown in fig. 2. The NMOS transistors N1 and N2 in the circuit are completely symmetrical. Width to length ratio (W/L) of P1, P2, P5 _P1 、(W/L) _P2 、(W/L) _P5 Equal, i.e. (W/L) _P1 ＝(W/L) _P2 ＝(W/L) _P5 = A; and the aspect ratio (W/L) of the hysteresis modulator P6 _P6 Greater than the width-to-length ratio of P1, P2, P5, i.e. (W/L) _P6 And = B > A, and A and B are constants.

The specific working principle of the implementation circuit of the present invention is described in detail as follows. The circuit can generate the effect of unilateral hysteresis through the action of the hysteresis regulator. V _in1 Is the positive terminal of the comparator, V _in2 Being the negative terminal of the comparator. When V is _in1 Is far less than V _in2 While, the NMOS tube N1 is cut offStopping, and stopping the PMOS tubes P1 and P5 at the moment; due to V _in2 The NMOS tube N2 is conducted due to the large size, and the current of the tail current source I1 completely flows through the N2 tube. The PMOS tube P6 and the PMOS tube P5 are in a deep triode state, and no current flows through.

V _in1 Gradually increases and approaches a positive threshold value V _TH+ In time, N1 is in saturation conduction, and the P6 of the PMOS tube of the hysteresis regulator is in linear conduction. When the current i of the NMOS transistor N1 _N1 With the current i on the hysteretic regulator P6 _P6 When the currents are equal, the comparator reaches its positive flip threshold V _TH+ . When i is _N1 ＝i _P6 When the comparator reaches its positive flip threshold V _TH+ 。

The PMOS transistors P6 and P2 form a current mirror structure, and it can be known from the characteristics of the current mirror structure circuit that the current flowing through the MOS transistor in the saturation state is proportional to the width-to-length ratio thereof, that is:

is (W/L) _p6 /(W/L) _p2 = c, c is constant and less than 1

The total current passing through the NMOS transistors N1 and N2 should be equal to the current I of the tail current source I1 ₁ The same is that:

i _N2 +i _N1 ＝i ₁ (2)

from the above analysis, it can be derived that the forward hysteresis V of the comparator _TH+ Comprises the following steps:

wherein beta is ₁ ＝μ _n C _ox (W/L) _N1

From equation (3), it can be known that the forward threshold of the comparator has a close relationship with the parameter c, the width-to-length ratios of P1, P2, and P5 are fixed in the design, and the magnitude of the tail current is known, so long as the width-to-length ratio of P6 in the hysteresis modulator 11 is adjusted to determine the hysteresis amount of the hysteresis comparator.

When V is _in1 Is far greater than V _in2 When the delay time is up, the NMOS transistor N2 is cut off, and at the time, the PMOS transistor P2 and the P6 of the hysteresis modulator 11 are cut off; due to V _in1 The NMOS tube N1 is conducted due to the large size, and the current of the tail current source I1 completely flows through the N1 tube. Meanwhile, the PMOS tube P5 is in a deep triode state, and no current flows through.

V _in2 Gradually increases and approaches a negative threshold value V _TH- When the voltage is applied, N2 is saturated and conducted, and the PMOS tube P5 is in linear conduction. When the current of NMOS transistor N2 is equal to the current of PMOS transistor P5, the comparator reaches its negative flip threshold V _TH- . I.e. when i _N2 ＝i _P5 When the comparator reaches its negative roll-over threshold V _TH- 。

The PMOS transistors P1 and P5 have a current mirror structure, and it can be known from the characteristics of the current mirror structure circuit that the current flowing through the MOS transistor in the saturation state is proportional to the width-to-length ratio thereof, that is:

the current i flowing through the PMOS tube P1 _P1 And the current i flowing through the NMOS transistor N1 _N1 Equal current i flowing through PMOS transistor P5 _P5 And the current i flowing through the NMOS transistor N2 _N2 Equal, and the total current through NMOS transistors N2 and N1 should be the same as tail current source I1 current I1, i.e.:

i _N2 +i _N1 ＝i ₁ (5)

from the above analysis it can be derived that the negative threshold calculation of the hysteresis comparator yields:

V _TH -＝V _in2 (6)

positive threshold V of hysteresis comparator _TH+ ＝V _in2 + α, negative threshold V _TH- ＝V _in2 (ii) a Therefore, the whole circuit achieves the effect of one-sided hysteresis, and the hysteresis amount is alpha.

V _in1 Can also be used as the negative input terminal of the comparator, V _in2 Can also be used as the input positive terminal of the comparator. At this time, V _O1 Is the positive output terminal of the comparator, V _O2 Is the negative terminal of the comparator output. Similarly, the positive threshold of the comparator at this time is the positive threshold V of the hysteresis comparator _TH+ Comprises the following steps:

V _TH+ ＝V _in2 (7)

negative threshold V of hysteresis comparator _TH- Comprises the following steps:

wherein c = (W/L) _P6 /(W/L) _P2 ，β ₁ ＝μ _n C _ox (W/L) _N1

Negative threshold V of hysteresis comparator _TH- ＝V _in2 + α, negative threshold V _TH ＝V _in2 (ii) a Therefore, the whole circuit achieves the effect of single-side hysteresis, and the hysteresis amount is alpha.

When the input MOS transistor is a PMOS transistor and the load MOS transistor is an NMOS transistor, the hysteresis regulator 11 is composed of an NMOS transistor N6, and the circuit diagram of the present invention is shown in fig. 3. In the circuit, PMOS tubes P9 and P10 are symmetrical, the width-to-length ratios of NMOS tubes N3, N4 and N5 are equal, and the width-to-length ratio of NMOS tube N6 is greater than that of NMOS tube N3. Except that the positive terminal of the current source I1 is connected to the power supply V _DD And the sources of all the NMOS tubes are connected together and grounded. The circuit of the configuration shown in fig. 3 operates on the same principle and the positive and negative threshold calculations as the circuit of fig. 2.

Fig. 4 shows a typical circuit diagram of a hysteresis comparator circuit built around the hysteresis comparator 1 of the present invention as shown in fig. 3. The tail current source P7 is shown biased by pin 7 input VB 1. Since the power consumption in the circuit is mainly determined by the tail current source P11, the magnitude of this bias VB1 directly determines the power consumption of the circuit. The current source should be sized on the order of nanoamps to reduce the power consumption of the hysteresis comparator circuit. The magnitude of the tail current that can be allocated to the branch can therefore be estimated from the power that the chip allows to be allocated to the module.

The width-to-length ratio of the NMOS transistor N6 is determined by the hysteresis. Compared with the width-length ratio of the NMOS load N4, the larger the width-length ratio of the NMOS transistor N6 is, the larger the hysteresis is. When designing the circuit, selecting proper lag can determine the width-to-length ratio of N6.

Input voltage V in core circuit _in1 From V _IN Instead, V _in2 By V in the circuit _ref Instead. The threshold voltage V of the comparator _TH And V _ref It is related. Selecting a suitable V _ref Not only with respect to the level to be compared in the chip, but also to enable the comparator to function properly. V _ref The PMOS input P2 is normally turned on and operates in the saturation region.

In order to make the core circuit fig. 3 provide reasonable output voltage swing and output resistance, the hysteresis comparator circuit adds an output stage, which is composed of NMOS transistors N7 and N8 and PMOS transistors P12 and P13. In addition, a device 2 Schmitt trigger is added in the circuit for waveform shaping, and the device 2 consists of PMOS tubes P14 and P15 and NMOS tubes N9 and N10. The addition of the inverter INV1 in fig. 4 increases the output driving capability of the circuit.

If V _IN The terminal is a PAD of the chip, so that the resistor R1, the PMOS transistors P17 and P18 and the NMOS transistor N12 shown in fig. 3 are required to complete the ESD protection function; if not, these four elements may be eliminated. At the same time V _ref A first-order filter circuit 4 is added at one end, the circuit 4 consists of a resistor R2 and an NMOS tube capacitor N13, and V is eliminated _ref The noise of (2).

Next, the operation of the hysteresis comparator circuit shown in fig. 4 will be described.

When the tail current source P11 is properly biased VB1, the circuit starts to operate normally. When V is _IN When the voltage is gradually reduced from high, the input pipe P9 is turned off, and the load pipes N3 and N5 are cut off; input tube P2 is conducted and tail current I _P11 The current passes through the input PMOS tube P10 completely, the load tube N4 is conducted at the moment, the corresponding current mirror load N6 is in a deep linear region, and no current flows. V _O1 The output is low potential, and N7 is turned off; while the core electricityThe other end of the way outputs V _O2 The differential outputs high potential, and N8 is conducted. The output of OUT1 is low potential, and then passes through a Schmitt trigger and an inverter INV1 and then goes to V _OUT Is at a low potential.

With V _IN The voltage is gradually reduced, and the input PMOS pipe P9 is gradually conducted. When the current through the input tube P1 is equal to the current of the NMOS tube N6, V _IN Reaches a negative threshold value V _TH- Since the aspect ratio of N6 is different from that of N4, a hysteresis effect is caused. At this time, the current of the input tube P10 is equal to the current of the diode-connected NMOS tube N4, and no current passes through the NMOS load tubes N3 and N5.

When V is _IN Input less than negative threshold voltage V _TH- The output V of the core circuit _O1 The high potential is input to the grid electrode of an NMOS tube N7 of the output stage, and the N7 is conducted; and the core circuit differential output V _O2 The low potential is input to the grid electrode of the NMOS tube N8 of the output stage, and the N8 is turned off. Through the conversion of PMOS current mirror load P12 and P13 from double-end to single-end, the N8 drain outputs OUT1, OUT1 are high potential. The output OUT1 passes through a Schmitt trigger and an inverter V _OUT Is at a high potential.

On the contrary, when V _IN When the current reaches a positive threshold value, the current of the P9 tube is equal to the current of the NMOS tube N3, the current of the input tube P10 is equal to the current of the N5, and the width-length ratios of the N3 and the N5 of the NMOS load current mirror structure in the design are the same. So that the positive threshold voltage of the circuit is equal to V _ref The same is true. The whole circuit completes the single-side hysteresis effect.

Claims

1. A hysteretic comparator, characterized by: the delay circuit comprises NMOS (N-channel metal oxide semiconductor) tubes N1 and N2, PMOS (P-channel metal oxide semiconductor) tubes P1, P2 and P5 and a delay regulator (11), wherein the delay regulator (11) is composed of a PMOS tube P6 and is used for regulating the threshold value of a comparator; the NMOS transistors N1 and N2 are symmetrical, the width-to-length ratios of the PMOS transistors P1, P2 and P5 are equal, and the width-to-length ratio of the PMOS transistor P6 is greater than that of the PMOS transistor P1;

n1 tube grid of NMOS tube as positive input end V _in1 The grid of N2 transistor of NMOS transistor is used asNegative input terminal V _in2 The sources of the current sources are connected, and the current sources are connected with the positive end of a tail current source I1, and the negative end of the current source I1 is grounded; the drain electrode of the NMOS tube N1 is connected with the drain electrode of the PMOS tube P1 and is connected to the drain electrode of a PMOS tube P6 in the hysteresis regulator (11); the drain electrode of the PMOS pipe P1 is connected with the grid electrode to form diode connection; the drain electrode of the NMOS tube N2 is connected with the drain electrode of the PMOS tube P2 and is connected to the drain electrode of the PMOS tube P5; the drain electrode of the PMOS tube P2 is connected with the grid electrode thereof, the grid electrode of the PMOS tube P1 is connected with the grid electrode of the PMOS tube P5, and the grid electrode of the PMOS tube P6 is connected with the grid electrode of the PMOS tube P2; the source electrodes of the PMOS tubes P1, P2, P5 and P6 are connected and are connected with a power supply V _DD (ii) a Negative output end V of PMOS (P-channel metal oxide semiconductor) pipe P6 _O1 The positive output end V of the PMOS tube is led out from the drain electrode of the NMOS tube N1 _O2 And the drain electrode of the N2 tube of the NMOS tube is led out.