CN105321987B - 包含硫族原子的半导体器件和制造方法 - Google Patents

包含硫族原子的半导体器件和制造方法 Download PDF

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CN105321987B
CN105321987B CN201510370090.8A CN201510370090A CN105321987B CN 105321987 B CN105321987 B CN 105321987B CN 201510370090 A CN201510370090 A CN 201510370090A CN 105321987 B CN105321987 B CN 105321987B
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G·施密特
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Infineon Technologies AG
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Abstract

本发明的各个实施例涉及包含硫族原子的半导体器件和制造方法。半导体器件包括具有第一表面和平行于该第一表面的第二表面的单晶半导体本体。该半导体本体包含磷族原子和/或氢原子的本底掺杂和硫族原子。硫族原子的浓度至少为1E12cm‑3。硫族原子与本底掺杂的原子之比在1:9至9:1范围内。

Description

包含硫族原子的半导体器件和制造方法
技术领域
本发明总体上涉及半导体器件，并且具体地涉及包含硫族原子的半导体器件和制造方法。
背景技术
通常，用于生产功率半导体器件诸如功率半导体二极管和IGBT(绝缘栅极双极晶体管)的半导体晶片从按悬浮区工艺(floating zone process)(Fz晶片)生长的硅锭获得。按直拉工艺(Czochralski process)(Cz晶片)从熔炉中的熔融原料直拉的硅棒获得的半导体晶片比较廉价并且可以具有更大的直径。然而，在拉晶工艺期间的分凝效应导致掺杂剂浓度沿着硅棒的纵轴发生显著的轴向变化。另外，在从硅棒获得的Cz晶片中，掺杂物质的径向波动(条纹)导致比电阻发生显著的径向变化。初始本底掺杂的较高变化使得从这种半导体晶体来制造半导体器件(例如，功率半导体器件)复杂化。期望以更具成本效益的方式来制造半导体器件。
发明内容
根据一个实施例，半导体器件包括具有第一表面和平行于该第一表面的第二表面的单晶半导体本体。该半导体本体包含磷族(pnictogen)原子的本底掺杂和硫族(chalcogen)原子。硫族原子的浓度为至少5E12cm-3。硫族原子与本底掺杂的磷族原子之比在1:9至9:1范围内。
在一个实施例中，硫族原子与磷族原子的所述比率在5:5至6:4范围内。
根据一种制造半导体器件的方法，将硫族原子注入到包含磷族原子的单晶半导体衬底中。硫族原子的浓度为至少1E12cm-3。硫族原子与磷族原子之总比在1:9至9:1范围内。
根据另一实施例，半导体器件包括具有第一表面和平行于该第一表面的第二表面的单晶半导体本体。该半导体本体包含磷族原子和/或氢原子的本底掺杂和硫族原子。硫族原子的浓度为至少5E12cm-3。硫族原子与本底掺杂的原子之比在1:9至9:1范围内。
本领域的技术人员通过阅读以下详细说明和对应附图会认识到附加的特征和优点。
附图说明
所附附图被包含进来以提供对本发明的进一步理解，并且包含在本说明书中并且构成本说明书的一部分。附图图示了本发明的实施例，并同说明书一起用于阐释本发明的原理。本发明的其他实施例和多种预期优点将由于通过参考以下详细说明而变得更充分理解而更容易理解。
图1A是根据与半导体二极管有关的一个实施例的包含磷族原子的近似均匀的本底掺杂和硫族原子的半导体器件的部分的示意性截面图。
图1B是示出了在图1A的半导体器件中的竖直掺杂剂分布的示意图。
图1C是示出了在图1A的半导体二极管中和在参考器件中的电场分布的示意图。
图2是示出了在制造图1A的半导体器件的工艺中在半导体衬底中的竖直杂质分布的示意图，用于图示硫族分布的细节。
图3A是根据与IGBT有关的一个实施例的包含磷族原子的近似均匀的本底掺杂和硫族原子的半导体器件的部分的示意性截面图。
图3B是根据与双极晶体管有关的一个实施例的包含磷族原子的近似均匀的本底掺杂和硫族原子的半导体器件的部分的示意性截面图。
图4是用于图示制造根据另一实施例的半导体器件的方法的原理流程图。
具体实施方式
在以下详细说明中，对对应附图进行参考，对应附图构成本详细说明的一部分，并且以图示的方式在其中示出了可以实践本发明的具体实施例。应理解，可以使用其他实施例，而且在不背离本发明的范围的情况下可以作出结构上或者逻辑上的改变。例如，针对一个实施例图示或描述的特征可以用于其他实施例，或者与其他实施例结合以产生另一实施例。本发明意在包括这类修改和变形。使用特定语言对示例进行描述，该特定语言不应解释为对所附权利要求书的范围进行限制。附图未按比例绘制，并且仅用作图示之目的。为清楚起见，如果没有另行说明，那么在不同附图中通过相应的附图标记表示相同的元件。
术语“具有”、“含有”、“包含”、“包括”等是开放性术语，并且这些术语表示存在规定结构、元件或者特征，但是不排除附加的元件或者特征。“一”、“一个”和“该”旨在包括复数形式和单数形式，除非上下文另外明确指示。
术语“电连接”描述了在电连接的元件之间的永久低欧姆连接，例如在相关元件之间的直接接触、或者经由金属和/或高掺杂半导体的低欧姆连接。术语“电耦合”包括，在电耦合的元件之间可以设置适用于信号传输的一个或者多个中间元件，例如，可控制为在第一状态下暂时提供低欧姆连接并且在第二状态下暂时提供高欧姆电解耦的元件。
附图通过在掺杂类型“n”或者“p”旁标注“-”或者“+”来图示相对掺杂浓度。例如，“n-”指低于“n”掺杂区域的掺杂浓度的掺杂浓度，而“n+”掺杂区域具有比“n”掺杂区域的掺杂浓度更高的掺杂浓度。相对掺杂浓度相同的掺杂区域并不一定具有相同的绝对掺杂浓度。例如，两个“n”掺杂的不同区域可以具有相同或者不同的绝对掺杂浓度。
虽然此处图示并且描述了特定实施例，但是本领域的技术人员要理解，在不背离本发明的范围下，可以用各种可替代的和/或等效的实施方式取代示出并且描述的特定实施例。本申请意在涵盖此处论述的各种具体实施例的任何改动或者变型。因此，本发明旨在仅仅受权利要求书及其等同物限制。
根据实施例的半导体器件可以是半导体二极管、IGFET(绝缘栅极场效应晶体管)、IGBT(绝缘栅极双极晶体管)例如RC-IGBT(反向导通型IGBT)、BJT(双极结型晶体管)、晶闸管、GTO(栅极关断晶闸管)或者辐射探测器。
在图1A中的半导体器件500为半导体二极管，例如，具有大于100mA(例如，大于1A或者大于10A)的标称正向电流IF的功率半导体二极管。
单晶半导体材料，例如硅(Si)、碳化硅(SiC)、锗(Ge)、锗硅晶体(SiGe)、氮化镓(GaN)、砷化镓(GaAs)或者其他AIIIBV半导体，形成半导体本体100，该半导体本体100具有：在正侧处的第一表面101，其可以是近似平面的，或者其可以由跨共面表面部分的平面所限定；以及在与正侧相对的背侧处的平面的第二表面102，其平行于该第一表面101。
在第一与第二表面101、102之间的最小距离取决于半导体器件500被指定的电压阻断能力。例如，当半导体器件500被指定为大约1200V的阻断电压时，在第一与第二表面101、102之间的距离可以在90μm至200μm范围内。与具有更高阻断能力的半导体器件有关的其他实施例可以提供具有几百μm厚度的半导体本体100。具有更低阻断能力的半导体器件可以具有从35μm至90μm的厚度。
在平行于第一表面101的平面中，半导体本体100可以具有矩形形状，其中边缘长度在数毫米范围内。平行于第一表面101的方向是水平方向，而垂直于第一表面101的方向是竖直方向。在第一与第二距离之间的距离为至少30μm，例如，至少100μm，或者至少120μm。
半导体本体100包括：第一负载接触层110，其与在正侧处的第一负载电极310欧姆接触；以及第二负载接触层130，其与在背侧处的第二负载电极320欧姆接触。第一负载电极310形成或者电连接至第一负载端子L1。第二负载电极320形成或者电连接至第二负载端子L2。第一和第二负载接触区域110、130具有相反的导电类型。根据图示的实施例，第一负载接触层110为p导电，而第二负载接触层130为n导电。
半导体器件500进一步包括第二负载接触区域130的导电类型的基础区域120。基础区域120可以包括具有至少1E13cm-3并且至多1E17cm-3的有效掺杂剂浓度的轻掺杂漂移区域121。漂移区域121的掺杂可以对应于半导体本体100的初始总本底掺杂。漂移区域121和第一负载接触层110可以形成pn结。基础区域120可以进一步包括夹设在漂移区域121与第二负载接触层130之间的场停止层128，其中在场停止层128中的平均杂质浓度与在漂移区域121中的有效掺杂剂浓度的至少二倍一样高，例如，十倍。
根据其他实施例，基础区域120可以进一步包括：补偿结构诸如超结结构，其用于在漂移区域121中的较高掺杂剂浓度下增加电压阻断能力；阻挡层，其用于增加在基础区域120的面向正侧之侧处的等离子密度，从而使反掺杂区域和/或另外的掺杂层浮置。
半导体本体100包括硫族原子，即，在元素周期表的第16族(“氧族元素”)中的化学元素的原子，诸如硫(S)、硒(Se)和碲(Te)。
在半导体本体中的平均硫族浓度可以在1E12cm-3至1E16cm-3之间，例如，在1E13cm-3至1E14cm-3范围内。根据一个实施例，硫族原子可以为硒原子，其中至少百分之一，例如百分之三、百分之五、或者百分之十的硒原子在取代晶格结点上是电活性的，并且在半导体器件500的操作模式中用作双重施主。
半导体本体100进一步包括磷族原子的近似均匀的本底掺杂，即，在元素周期表的第15族(“氮族元素(nitrogen family)”，前一族V)中的化学元素的原子，诸如磷(P)、砷(As)和锑(Sb)。磷族原子基本上均匀地分布在整个半导体本体100中，其中均匀本底掺杂的浓度与平均值的偏差不超过8％，例如不超过5％，并且其中半导体本体100从具有至多15％的均匀本底掺杂的晶片间偏差的特定晶片获得。
硫族原子与基本均匀本底掺杂的磷族原子之总比在1:9至9:1范围内。换言之，初始总本底掺杂的硫族部分在大约10At％至大约90At％范围内。硫族原子和均匀磷族本底掺杂限定了初始总本底掺杂。
总硫族含量通过注入引起，其中与目标注入剂量的偏差至多为±5％，其中通过在半导体本体100的正侧处的第一表面101注入硫族原子，并且硫族浓度随着与第一表面101的距离增加而逐渐降低。在通常用于制造半导体器件的工艺期间的可用热预算下，硫族浓度的掺杂梯度在与第一表面101相距大于60μm的距离处显著地下降。
相反地，均匀本底掺杂的磷族原子是在原始半导体锭的晶体生长期间包含进去的。并非沿着竖直方向的浓度降地，均匀本底掺杂可以显著地偏离目标值。通常，在Cz晶片中，磷含量与平均值或者目标值的最大偏差为±15％。
半导体本体100可以包括包含掺杂剂(例如，除了均匀磷族本底掺杂之外的磷族原子)的另外的掺杂区域。例如，除了硫族掺杂剂和均匀磷族本底掺杂之外，场停止层128可以包含以在1E14cm-3至1E18cm-3之间的第一主掺杂剂浓度下通过第二表面102从背侧注入的第一主掺杂剂，例如氢原子。第二负载接触层130可以包含第二主掺杂剂，例如磷原子。第二主掺杂剂浓度确保与第二负载电极320的欧姆接触，并且例如可以为至少1E18cm-3，或者至少5E19cm-3。
硫族和用于总本底掺杂的磷族的共掺杂使用了更严格的硫族注入规范，以获得具有严格限定的总本底掺杂剂量的半导体本体。共注入进一步使用了更均匀的本底磷族分布，以将总垂直掺杂剂梯度调整为更接近从Fz晶片获得的半导体本体的总竖直掺杂剂梯度。在最终的半导体器件500中，漂移区域121可以包含不大于由硫族原子和原始的近似均匀的磷族本底掺杂限定的初始总本底掺杂。
可以根据针对相关半导体器件的平均基础掺杂的比电阻所指定的容差，来选择磷族本底掺杂。
例如，用于硒原子的注入工艺被指定具有至少±5％的最大偏差，以及具有均匀磷本底掺杂的Cz晶片的比电阻(ρ值)的最大偏差为±15％。具有200μm的竖直延伸(厚度)的半导体本体的半导体器件的目标规范可以限定比电阻为93Ωcm并且目标容差或者最大总偏差为±8％。由该目标容差导致硒含量是总本底掺杂的掺杂剂的至少53.9At％。针对给定的200μm的厚度，剩余的磷含量对应于用于原始Cz晶片的350Ωcm的ρ值。换言之，半导体本体包含大约3.4E11cm-2的硒剂量和大约2.5E11cm-2的磷剂量。在18At％的硒含量下，最大总偏差或者可实现的目标容差至多为12％。
根据其他实施例，半导体本体100包括部分地或者完全地取代均匀本底掺杂的磷族原子的氢原子。
图1B示出了针对图1A的半导体器件500的竖直掺杂分布，其中在漂移区域121中的掺杂浓度对应于，在注入用作阳极层的第一负载接触层110、场停止区域128、和用作阴极层的第二负载接触层130之前，在整个半导体本体100中的总本底掺杂剂浓度。
均匀分布415对应于具有均匀磷本底浓度和93Ωcm的ρ值的第一参考器件。
硒浓度410指不具有硅锭的磷族本底掺杂的第二参考器件。硒原子从正侧注入。然后，对半导体本体100加热，从而硒原子扩散到第二表面102的方位中，其中辅助杂质例如磷原子可以通过生成硅的自间隙(self-interstitial)来促进硒原子的扩散。随着热预算的增加，硒浓度410变平。通常适用于半导体器件500的热预算导致在与第一表面101相距超过或等于大约60μm的距离处的硒浓度的显著下降。为了在超过与第一表面101相距大于70μm的距离处也使硒浓度410显著地变平，要求显著的热预算。
有效施主分布411图示了由于在第二参考器件的耗尽区域中的硒原子的双电离所引起的施主电荷的浓度梯度。
共掺杂分布420对应于在图1A的半导体器件500中的硒原子和磷原子的总浓度。总本底掺杂的硒含量为54At％。总本底的磷含量对应于350Ωcm的ρ值。考虑到硒作为双重施主的特性，有效共掺杂分布421对应于在耗尽区域中的有效施主浓度。在超出70μm的、硒浓度410显著地下降至值之处，共掺杂偏移了一定距离。
在第一负载接触区域110与场停止层128之间的总距离对应于半导体器件500的反向电压阻断能力，其中大约8μm至12μm的层厚度可以对应于大约100V的电压阻断能力。实施例允许从Cz晶片提供具有与从Fz晶片获得的半导体器件相似的掺杂剂分布的半导体器件，甚至用于阻断超过1000V的电压。另外，硫族剂量的微调可以补偿原始的Cz晶片和Fz晶片的ρ值的波动。
图1C示出了用于图1B的第一和第二参考器件和图1A的半导体器件500的电场分布。场分布515对应于在漂移区域121中具有恒定净掺杂分布的第一参考器件的场分布，这是因为其对于通过Fz晶片生产的半导体器件是典型的。场分布510对应于在漂移区域121中的掺杂剂排他地提供自硒原子的第二参考器件。场分布520对应于在1700V的标称阻断电压下包含完全离子化的54At％的硒和46At％的磷原子的共掺杂实施例。
相对于第二参考器件，磷和硒的共掺杂使在至第一负载接触区域110的pn结处和在至场停止层128的pn结处的电场强度显著地降低。与线性场分布515的偏差越小，半导体器件越薄，以及针对ρ值的可接受偏差越大。具有在漂移区域121的中央区域中的浓度最大值的硒浓度的剩余曲率倾向于降低开关损失，以及数值模拟指示可以显著地改进开关的软度(softness)。
图2图示了在制造半导体器件(例如，具有大约600V的阻断电压的半导体二极管)期间的掺杂分布。
在15keV至500keV范围内的注入能量下，以在1E13cm-2至1E15cm-2范围内的剂量，通过半导体衬底100a的第一表面101注入硒原子。用作辅助杂质源的辅助层，可以形成在第一表面101上。该辅助层可以是在包含PH3(磷烷)或者POCl3(三氯氧磷)的气氛中形成的磷酸玻璃。在第一热处理期间，注入的硒原子从注入层扩散出来，其中辅助层的辅助杂质在一定程度上置换了半导体的晶格的原子，从而在半导体衬底100a的半导体晶体中生成半导体间隙。该自间隙通过将注入的硒原子从其晶格点击出并且取代注入的硒原子，来促进注入的硒原子的扩散。去除辅助层。第一硒掺杂分布431图示了在去除辅助层之后并且在大于900℃且小于1100℃的温度下持续了至少20分钟的第一热处理之后的半导体衬底100a中的硒分布。
在制造半导体器件期间进行的进一步的高温处理(例如，热氧化物的形成)使硒浓度分布变平，如第二硒掺杂分布432指示的。进一步的热处理可以进一步地使硒浓度分布变平，如第三硒掺杂分布433指示的。在从背侧将半导体衬底100a减薄至具有高达800V的阻断电压的半导体器件的半导体本体100的大约60μm至80μm的厚度的之后，由此产生的漂移区域121展现出近似均匀的硒浓度。掺杂剂分布433图示了半导体二极管的总掺杂分布，该半导体二极管具有p导电第一负载接触层110、n导电漂移区域121、通过质子注入而产生的n导电场停止层128、和通过从减薄的半导体衬底100a的背侧表面进行磷注入而产生的n导电第二负载接触层130。
为了实现用于阻断超过1200V的电压的均匀掺杂漂移区域，必须施加显著更高的热预算，这通常会增加滑移线密度(slip line density)和生产成本。实施例在显著减少的消耗的情况下，实现了相似的效果。
图3A示出了半导体器件500诸如IGFET、IGBT例如RC-IGBT、BJT、晶闸管、或者GTO。关于半导体本体100的一般性特征，参考对图1A至图1C的半导体器件500的说明。夹设在基础区域120与第二负载电极320之间的第二负载接触层130针对IGFET可以是n导电层、针对非反向导通型IGBT可以是p导电层、或者针对半导体器件500是RC-IGBT的情况下可以是包含n导电区域和p导电区域两者的层。
替代图1A的第一负载接触层110，半导体器件500包括晶体管单元TC，该晶体管单元TC可以是具有n导电源极区域和使该源极区域与漂移区域121分离的p导电本体区域的IGFET单元。源极区域可以电连接或耦合至第一负载电极，该第一负载电极可以设置在半导体器件500的正侧和/或设置于第一负载端子L1处。
晶体管单元TC的栅极电极可以电连接或耦合至栅极端子G，并且可以通过栅极电介质电容耦合至本体区域。受到施加至栅极端子G的电压的影响，反型沟道形成在本体区域中并且通过晶体管单元TC提供电子流，从而使得电子在半导体器件500的第一状态下通过晶体管单元TC进入漂移区域121，该第一状态可以对应于IGBT的晶体管模式或者IGFET的导电模式。
除了源极区域之外，本体区域也电连接或耦合至第一负载端子L1，其中本体区域可以在半导体器件500的第二状态下将空穴注入到漂移区域121中，其中举例而言，该第二状态可以对应于例如RC-IGBT的反向导通模式。
晶体管单元TC可以是具有布置在半导体本体100的轮廓外部的平面栅极结构、或者具有延伸到半导体本体100中的沟槽栅极结构的沟槽栅极单元。例如，晶体管单元TC的源极区域和本体区域可以形成在由沟槽栅极结构分隔开的半导体台面结构中。在漂移区域121中的掺杂剂含量可以对应于包括均匀分布的磷族原子和具有如在前述附图中描述的略弯曲或者倾斜的掺杂分布的硫族原子的总本底掺杂。
在图3B中，半导体器件500为包括与漂移区域121一起形成pn结的p掺杂基极层116的BJT。发射极区域110与基极层116一起形成另外的pn结。基极连接结构330与基极层116形成欧姆接触并且电连接或耦合至栅极端子G。第一负载电极310与发射极区域110形成欧姆接触并且电连接至发射极端子E。第二负载电极320与用作集电极区域的第二负载接触层130形成欧姆接触并且电连接至半导体器件500的集电极端子C。
图4示出了制造半导体器件的方法。按直拉工艺获得半导体晶片，其中半导体晶片包含至少1E13cm-3(502)的磷族本底掺杂。将硫族原子注入到半导体晶片中(504)，其中硫族原子与磷族本底掺杂的磷族原子之比在1:9至9:1范围内。
可以提供辅助杂质，以便增加间隙半导体原子的密度。对半导体晶片加热，从而使得硫族原子更深地扩散到半导体衬底中，其中辅助杂质通过增加在半导体衬底中的间隙原子的密度来帮助扩散。在热处理之前，可以形成包含并且提供辅助杂质的辅助层；并且在热处理之后，可以去除该辅助层。辅助杂质可以为磷原子。半导体晶片可以为单晶硅晶片。注入的硫族可以为硒。
虽然此处图示并且描述了特定实施例，但是本领域的技术人员要理解，在不背离本发明的范围下，可以用多种替代和/或等效实施方式取代所示出并且描述的特定实施例。该申请意在涵盖此处论述的具体实施例的任何改动或者变型。因此，本发明旨在仅仅受权利要求书及其等同物限制。

Claims (18)

1.一种半导体器件，包括：
单晶半导体本体，具有第一表面和与所述第一表面平行的第二表面，所述半导体本体包含：磷族原子的本底掺杂、和硫族原子，
其中磷族原子的浓度为至少1E12cm-3，并且硫族原子与所述本底掺杂的磷族原子的比率在1:9至9:1范围内；并且
其中所述半导体本体包括漂移区域，所述漂移区域与所述第一表面平行地延伸、并且与所述第一表面和所述第二表面两者间隔开，其中在所述漂移区域中的有效掺杂剂浓度由在所述半导体本体中的所述磷族原子的本底掺杂和所述硫族原子限定。
2.根据权利要求1所述的半导体器件，其中
所述半导体本体具有与所述第一表面垂直的至少50μm的竖直延伸。
3.根据权利要求1所述的半导体器件，其中
硫族原子与磷族原子的所述比率在5:5至6:4范围内。
4.根据权利要求1所述的半导体器件，其中
电活性硫族浓度大于1E12cm-3。
5.根据权利要求1所述的半导体器件，其中
硫族为硒。
6.根据权利要求1所述的半导体器件，其中
磷族为磷。
7.根据权利要求1所述的半导体器件，其中
所述半导体本体为硅晶体。
8.根据权利要求1所述的半导体器件，进一步包括：
场停止层，在所述漂移区域与所述第二表面之间，所述场停止层进一步包含：第一主掺杂剂，为第一主掺杂剂浓度，所述第一主掺杂剂浓度高达在所述漂移区域中的所述有效掺杂剂浓度的至少两倍。
9.根据权利要求1所述的半导体器件，进一步包括：
负载接触层，与所述第二表面直接邻接，所述负载接触层进一步包含第二主掺杂剂、并且与直接邻接所述负载接触层的包含金属的负载电极形成欧姆接触。
10.根据权利要求1所述的半导体器件，其中
磷族原子的所述本底掺杂变化不超过5％。
11.根据权利要求1所述的半导体器件，其中
在所述第一表面与所述第二表面之间的距离至少为120μm。
12.一种制造半导体器件的方法，所述方法包括：
从包含均匀分布的磷族原子的单晶半导体晶片的正侧，将硫族原子注入到所述半导体晶片中，
其中在所述半导体晶片中，硫族原子与磷族原子的比率在1:9至9:1范围内。
13.根据权利要求12所述的方法，进一步包括：
在注入硫族原子之后、在第一次将所述半导体晶片加热到至少900℃之前，在所述半导体晶片的所述正侧处设置用于辅助杂质的源，以便增加间隙半导体原子的密度。
14.根据权利要求13所述的方法，其中：
所述辅助杂质为磷原子。
15.根据权利要求14所述的方法，进一步包括：
在第一次将所述半导体晶片加热到至少900℃之后，去除辅助层，所述辅助层用作用于所述辅助杂质的所述源。
16.根据权利要求12所述的方法，其中：
所述半导体晶片从单晶硅锭获得，所述单晶硅锭通过直拉工艺从包含所述磷族原子的原材料形成。
17.根据权利要求12所述的方法，其中：
硫族为硒。
18.一种半导体器件，包括：
单晶半导体本体，具有第一表面和与所述第一表面平行的第二表面，所述半导体本体包含：磷族原子和/或氢原子的本底掺杂、和硫族原子，
其中硫族原子的浓度为至少1E12cm-3，并且硫族原子与所述本底掺杂的原子的比率在1:9至9:1范围内；并且
其中所述半导体本体包括漂移区域，所述漂移区域与所述第一表面平行地延伸、并且与所述第一表面和所述第二表面两者间隔开，其中在所述漂移区域中的有效掺杂剂浓度由在所述半导体本体中的本底掺杂和所述硫族原子限定。
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