CN105161605B - A kind of GaN base LED core piece preparation method of achievable efficient encapsulation - Google Patents
A kind of GaN base LED core piece preparation method of achievable efficient encapsulation Download PDFInfo
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- CN105161605B CN105161605B CN201510428655.3A CN201510428655A CN105161605B CN 105161605 B CN105161605 B CN 105161605B CN 201510428655 A CN201510428655 A CN 201510428655A CN 105161605 B CN105161605 B CN 105161605B
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- 238000005538 encapsulation Methods 0.000 title claims abstract description 18
- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 238000002955 isolation Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 238000001039 wet etching Methods 0.000 claims abstract description 7
- 238000001465 metallisation Methods 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 41
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 238000005520 cutting process Methods 0.000 claims description 4
- 239000000945 filler Substances 0.000 claims description 4
- 150000002739 metals Chemical class 0.000 claims description 4
- 238000002161 passivation Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000001704 evaporation Methods 0.000 claims description 3
- 239000011241 protective layer Substances 0.000 claims description 3
- 230000005611 electricity Effects 0.000 claims description 2
- 210000004027 cell Anatomy 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 7
- 239000011324 bead Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012536 packaging technology Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000003466 welding Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000010923 batch production Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000008358 core component Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000009931 harmful effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000011835 investigation Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/52—Encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/9205—Intermediate bonding steps, i.e. partial connection of the semiconductor or solid-state body during the connecting process
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
Abstract
A kind of GaN base LED core piece preparation method of achievable efficient encapsulation, comprises the following steps：（1）Epitaxial wafer is prepared, one layer of transparent conductive layer is deposited on epitaxial wafer surface；(2) P electrode and N electrode are made；Retain the photoresist mask in P electrode and N electrode, wouldn't remove；(3) epitaxial wafer is cut, forms single chip unit, be cut at substrate, make to form isolation channel between adjacent chips unit；(4) SiO is deposited on the epitaxial wafer surface with isolation channel2, utilize the photoresist mask on wet etching removal chip electrode surface；(5) metallization connection is carried out to chip unit；(6) required to cut out required LED chip according to encapsulation.The present invention is gone here and there and connected in advance from LED chip manufacturing process, is then packaged processing procedure again；Corresponding chip can be cut out according to demand, is directly packaged, and have the characteristics that encapsulation process is easy to operate, packaging efficiency is high, cost is low, properties of product are stable, luminous efficiency is high, good reliability.
Description
Technical field
The present invention relates to a kind of preparation method of GaN base LED chip, belong to LED chip preparing technical field.
Background technology
Core component of the LED chip as semiconductor lighting, in face of increasingly serious Market Situation, how to improve core
Piece luminous power, lifting packaging efficiency, reduction packaging cost etc. propose higher requirement to the preparation method of LED chip.
It is well known that, it is necessary to be packaged into LED lamp bead to chip after the completion of the production and processing of LED chip.Current LED in the markets
The chip of presentation is to draw to be cleaved into junior unit independent one by one after complete epitaxial wafer disk progress tube core technique is completed,
Each unit be a LEDs chip, often there is a positive pole, a negative pole on chips, is needed each LED chip list during encapsulation
Member is all placed on a LED support admittedly, is reused special bonding equipment and go here and there and connect the required lamp bead of composition.
When being packaged batch production, this single independent chip unit easily causes following drawback：1. single chip
Luminous power is relatively low, needs multiple chips unit to carry out connection in series-parallel can be only achieved required brightness or power；2. plurality of LEDs chip list
Member, which will be put on LED support, to cause efficiency to substantially reduce；3. carrying out die bond to every chips in encapsulation process, not only cause
The waste of raw material, it is also easy to the problems such as crooked chip, deviation of die bond position occur；4. gone here and there simultaneously using bonding equipment
During connection, because single chip is independent, it is necessary to the number of welding will certainly increase, simultaneously because position deviation of die bond etc. is held
Phenomena such as easily causing solder joint loosely, so as to cause defective products to increase；If 5. it is connected, as long as there is a chips list
The whole cluster of lamps, ornamental pearl that first failure welding is possible to cause to be attached thereto does not work, difficult to also increasing investigation during its fault detect
Degree；6. this lamp bead finished product reliability for encapsulating out single LEDs chip connection in series-parallel cannot guarantee that.It is a variety of more than to lack
Point, unavoidably encapsulation enterprise can be given to cause the harmful effects such as low operating efficiency, cost increase, fraction defective height.
Disclosed in Chinese patent literature CN200910263933《Multi-chip integrated LED electrically connects method》Propose one kind
It is arranged in by mxn LEDs chips with rectangular mode on substrate and forms multi-chip integrated LED, all positive poles of first row LED chip
Connecting substrate positive pole, all negative pole connecting substrate negative poles of last row LED chip, netted company is used between all LED chips
Connect mode to connect with wire, when the invention can ensure that short circuit or open circuit fault occur for any one LEDs chip on substrate, do not work
LED chip minimum number, and the LED chip damaged does not interfere with the normal luminous of other LED chips, reliable so as to improve
Property.
But the complex manufacturing of the above method, production efficiency is not high, causes its cost price higher, in addition, should
The problems such as shared dispensing of existing packaging technology is abnormal, chip pendulum is askew, chip collapses also be present in method.
The content of the invention
For low production efficiency of the existing single LEDs chip in the presence of process of manufacture is encapsulated, fraction defective it is high, can
The deficiencies of by property difference, the present invention provide that a kind of luminous power is strong, packaging efficiency is high, high yield rate, good reliability, packaging cost are low
Realize the GaN base LED core piece preparation method of efficient encapsulation.
The GaN base LED core piece preparation method of the achievable efficient encapsulation of the present invention, comprises the following steps：
(1) epitaxial wafer is prepared；
In Grown epitaxial layer, epitaxial wafer is formed；Epitaxial layer is followed successively by GaN layer, N-type GaN layer, quantum from the bottom to top
Trap active area and p-type GaN layer；One layer of ITO (tin indium oxide) transparency conducting layer is deposited on epitaxial wafer surface；
The thickness of transparent conductive layer is 2000-2500 angstroms.
(2) P electrode and N electrode are made；
Mask is done using photoresist, P electrode figure and N electrode figure are made on epitaxial wafer surface；Removed with wet etching
Photoresist mask outside electrode pattern, the ohmic contact layer that annealing forms P electrode is carried out to transparent conductive layer；In N electrode
Etching removes p-type GaN layer and Quantum well active district on figure, exposes N-type GaN layer, forms N electrode, retains P electrode and N electricity
Photoresist mask on extremely, wouldn't be removed；
(3) epitaxial wafer is cut, forms single chip unit, be cut at substrate, made between adjacent chips unit
Form isolation channel；
(4) deposited by metal-organic chemical vapor deposition equipment method (PECVD) on the epitaxial wafer surface with isolation channel
SiO2, using the protective layer as chip unit surface, chip unit side wall passivation layer and isolation channel in filler, utilize
Wet etching removes the photoresist mask on chip electrode surface；
(5) in chip unit surface evaporated metal layer, metallization connection is carried out to chip unit, removes what need not be connected
Part metals, the electrode of adjacent chips unit in each column is set to be connected, often the electrode of the upper adjacent chips unit of row is carried out and connected；
The metal level of evaporation is Au, Cr and Ni hybrid metal of 10000-15000 angstroms of thickness.
(6) require that (voltage, power, brightness etc.) cuts out required LED chip according to encapsulation.
The LED chip cut out obtains series chip to be longitudinally cutting, and transverse cuts obtain parallel chip.
The present invention is gone here and there and connected in advance from LED chip manufacturing process, is then packaged processing procedure again；Can be according to visitor
Family cuts out corresponding chip to the demand of voltage, power, brightness etc., is directly packaged, without again entering single chip
Row dispensing, die bond, bonding wire, finally connection in series-parallel connects again；The present invention reduces by 60% from the holistic cost of extension, chip to LED lamp bead
More than, solve the problems such as packaging efficiency is low, cost is high, output capacity is low, fault rate is high, while ensure that product reliability,
Solves the problems such as dispensing of existing packaging technology, chip pendulum is askew, chip collapses.Compared with prior art, the present invention has envelope
Fill the features such as process operation is convenient, packaging efficiency is high, cost is low, properties of product are stable, luminous efficiency is high, good reliability.
Brief description of the drawings
Fig. 1 be related in the present invention can efficient encapsulation GaN base LED chip structural representation.
Fig. 2 is Fig. 1 top view.
Fig. 3 is the schematic diagram of longitudinally cutting obtained series chip.
Fig. 4 is the schematic diagram for the parallel chip that transverse cuts obtain.
In figure：1.P electrodes；2.N electrodes；3. metallized conductive layer；4. passivation layer；5. filler；6. substrate；7. chip list
Member；8. isolation channel；9. the metal level in isolation channel；10. parallel connection LED chip；11. series LED chip.
Embodiment
The GaN base LED core piece preparation method of the achievable efficient encapsulation of the present invention, comprises the following steps：
(1) epitaxial wafer is prepared
As shown in figure 1, in the growing epitaxial layers of substrate 6, epitaxial wafer disk is formed；Epitaxial layer is followed successively by GaN from lower to upper
Layer, N-type GaN layer, Quantum well active district and p-type GaN layer；In order to effectively activate the activity of impurity in p-type GaN layer,
The transparent conductive layer that a layer thickness is 2000-2500 angstroms is deposited using evaporation of metal platform for epitaxial wafer surface.
(2) P electrode and N electrode are made
Mask is done using photoresist, P electrode figure and N electrode figure are made on epitaxial wafer surface；Removed with wet etching
Photoresist mask outside electrode pattern, the ohmic contact layer that annealing forms P electrode is carried out to ITO；Utilized on N electrode figure
ICP etching technics removes p-type GaN layer and Quantum well active district, and etching depth is 11000-13500 angstroms, exposes N-type GaN layer
N electrode 2 is formed, now retains P, the photoresist mask in N electrode, wouldn't remove.
(3) as shown in Fig. 2 being cut to epitaxial wafer, it is cut at substrate 6, forms single chip unit, adjacent chips
Isolation channel 8 is formed between unit, forms the epitaxial wafer with isolation channel 8.
(4) metal-organic chemical vapor deposition equipment method is passed through in the epitaxial wafer surface with isolation channel 8 made of step (3)
(PECVD) SiO is deposited2, in the passivation layer 4 of protective layer, chip unit side wall in this, as chip unit surface, isolation channel 8
Filler 5, utilize wet etching to remove the photoresist mask on chip electrode surface.
(5) metallization connection is carried out to chip unit 7, connected mode is as shown in Figure 2；One is deposited on the surface of chip unit 7
Thickness degree is 10000-15000 angstroms of Au/Cr/Ni hybrid metals, turns into and leads the metallization that the progress connection in series-parallel of all electrodes connects
Electric layer 3.The P electrode of adjacent chips unit 7 and N electrode in each column or row are attached using photoetching process, is retained simultaneously
The often metal level 9 in capable or each column chip chamber isolation channel, removes other part metals that need not be connected.Make adjacent core in each column
The electrode of blade unit is connected, and often the electrode of the upper adjacent chips unit of row is carried out and connected.
(6) it is longitudinally cutting on the basis of step (5) to obtain series chip 10, as shown in Figure 3；Transverse cuts obtain parallel connection
Chip 11, as shown in Figure 4.
Claims (4)
1. a kind of GaN base LED core piece preparation method of achievable efficient encapsulation, it is characterized in that, comprise the following steps：
(1) epitaxial wafer is prepared；
In Grown epitaxial layer, epitaxial wafer is formed；Epitaxial layer is followed successively by GaN layer, N-type GaN layer, SQW from the bottom to top to be had
Source region and p-type GaN layer；One layer of transparent conductive layer is deposited on epitaxial wafer surface；
(2) P electrode and N electrode are made；
Mask is done using photoresist, P electrode figure and N electrode figure are made on epitaxial wafer surface；Electrode is removed with wet etching
Photoresist mask outside figure, the ohmic contact layer that annealing forms P electrode is carried out to ITO；Mask is done using photoresist, is prepared
P, n-electrode figure etches on N electrode figure removes p-type GaN layer and Quantum well active district, exposes N-type GaN layer, forms N electricity
Pole, retain the photoresist mask in P electrode and N electrode, wouldn't remove；
(3) epitaxial wafer is cut, forms single chip unit, be cut at substrate, make to be formed between adjacent chips unit
Isolation channel；
(4) SiO is deposited on the epitaxial wafer surface with isolation channel by metal-organic chemical vapor deposition equipment method2, to be used as chip
Filler in the protective layer of cell surface, the passivation layer and isolation channel of chip unit side wall, goes to decore using wet etching
The photoresist mask on plate electrode surface；
(5) in chip unit surface evaporated metal layer, metallization connection is carried out to chip unit, removes the part that need not be connected
Metal, the electrode of adjacent chips unit in each column is set to be connected, often the electrode of the upper adjacent chips unit of row is carried out and connected；
(6) required to cut out required LED chip according to encapsulation.
2. the GaN base LED core piece preparation method of achievable efficient encapsulation according to claim 1, it is characterized in that, the step
Suddenly the thickness of transparent conductive layer is 2000-2500 angstroms in (1).
3. the GaN base LED core piece preparation method of efficient encapsulation can be realized according to claim 1, it is characterized in that, the step
(5) metal level of evaporation is the Au/Cr/Ni hybrid metals of 10000-15000 angstroms of thickness in.
4. the GaN base LED core piece preparation method of efficient encapsulation can be realized according to claim 1, it is characterized in that, the step
(6) LED chip cut out in obtains series chip to be longitudinally cutting, and transverse cuts obtain parallel chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510428655.3A CN105161605B (en) | 2015-07-21 | 2015-07-21 | A kind of GaN base LED core piece preparation method of achievable efficient encapsulation |
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| CN201510428655.3A CN105161605B (en) | 2015-07-21 | 2015-07-21 | A kind of GaN base LED core piece preparation method of achievable efficient encapsulation |
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| CN105161605A CN105161605A (en) | 2015-12-16 |
| CN105161605B true CN105161605B (en) | 2017-11-24 |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105720145B (en) * | 2016-03-25 | 2018-06-05 | 山东浪潮华光光电子股份有限公司 | A kind of preparation method of multi-chip parallel connection illumination module |
| CN111312867B (en) * | 2020-02-21 | 2023-12-15 | 湘能华磊光电股份有限公司 | Preparation method of single-chip white light LED |
| CN112885932B (en) * | 2021-01-19 | 2023-07-04 | 江西锐芯微电子科技有限公司 | Manufacturing method of miniature LED display chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376735A (en) * | 2010-08-13 | 2012-03-14 | 大连美明外延片科技有限公司 | Integrated light-emitting diode array chip and production method thereof |
| CN103219286A (en) * | 2012-11-16 | 2013-07-24 | 映瑞光电科技(上海)有限公司 | LED (light emitting diode) display screen and manufacture method thereof |
| CN103456864A (en) * | 2013-08-29 | 2013-12-18 | 刘晶 | Light-emitting diode chip manufacturing method, chip and light emitting-diode |
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- 2015-07-21 CN CN201510428655.3A patent/CN105161605B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102376735A (en) * | 2010-08-13 | 2012-03-14 | 大连美明外延片科技有限公司 | Integrated light-emitting diode array chip and production method thereof |
| CN103219286A (en) * | 2012-11-16 | 2013-07-24 | 映瑞光电科技(上海)有限公司 | LED (light emitting diode) display screen and manufacture method thereof |
| CN103456864A (en) * | 2013-08-29 | 2013-12-18 | 刘晶 | Light-emitting diode chip manufacturing method, chip and light emitting-diode |
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