CN103219352B - LED combination chip of array architecture and preparation method thereof - Google Patents
LED combination chip of array architecture and preparation method thereof Download PDFInfo
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Abstract
The invention provides a kind of LED combination chip with array architecture and preparation method thereof, this combined chip is comprised and being connected by array architecture wiring is some GaN base LED chips of one single core grain; Each GaN base LED chip comprises from top to bottom successively: epitaxial wafer, dielectric isolation layer, transparency conducting layer, P-type electrode and P type pad, N-type electrode and N-type pad and passivation layer.The present invention is the device that traditional GaN base light-emitting diode combines with IC circuit, and integrated by multiple traditional GaN base LED chip unit array, chip unit forms one single core grain, and the quantity of user's packaging and routing greatly reduces, and reduces encapsulation difficulty.Further, combined chip of the present invention, with the type of drive work of big current small voltage, is not only alleviated the stress because thermal mismatching and lattice mismatch cause, and is increased light extraction efficiency due to increasing of sidewall area, thus improves luminous efficiency.
Description
Technical field
The present invention relates to light-emitting diode (LED) devices field, especially, LED combination chip relating to a kind of array architecture and preparation method thereof.
Background technology
Along with rise and the continuous maturation of third generation semiconductor technology, semiconductor lighting is little with energy consumption, pollution-free, high brightness, the advantages such as long-life, becomes the focus that people pay close attention to, has also driven the flourish of whole industry upper, middle and lower reaches industry.GaN base LED chip is semiconductor lighting " power ", and performance is increased dramatically in recent years, and production cost also constantly reduces, and comes into huge numbers of families make outstanding contributions for semiconductor lighting.
In semiconductor illumination technique, the manufacture of GaN base blue-light LED chip and the rear blue-ray LED excitated fluorescent powder of encapsulation obtain the core technology that white light is its illumination, and reducing chip manufacturing and packaging cost and technology difficulty is one of key factor of universal semiconductor lighting.
Conventional power type LED lamp bead (as 1W, 3W, 5W, 10W etc.) adopts many power-type chips be encapsulated in the support itself with circuit structure with suitable series and parallel form and obtain mostly, the final drive current of this mode is little, but the voltage at lamp pearl two ends is high, and require very high to encapsulation technology, during connection in series-parallel, routing is many, not only technique is complicated, and reliability is difficult to ensure, and cost is relatively high.
Summary of the invention
The object of the invention is LED combination chip providing a kind of array architecture and preparation method thereof, to solve the routing complexity of current multi-chip lamp pearl, the technical problem of complex manufacturing technology.
For achieving the above object, the invention provides a kind of LED combination chip of array architecture, comprising:
By some the GaN base LED chips that array architecture wiring connection is one single core grain;
Each GaN base LED chip comprises from top to bottom successively:
-substrate;
-N-type GaN layer, described N-type GaN layer growth is on substrate;
-active area quantum well layer, described active area quantum well layer comprises some to InGaN/GaN trap base structure, grows in N-type GaN layer;
-P type GaN layer, described P type GaN layer growth is on the quantum well layer of active area;
-dielectric isolation layer, this separator is produced on N-type GaN layer and P type GaN layer;
-transparency conducting layer, this transparency conducting layer is produced on P type GaN layer and dielectric isolation layer;
-P-type electrode and P type pad, this P-type electrode is laid on transparency conducting layer and dielectric isolation layer, and P type pad and P-type electrode line link together;
-N-type electrode and N-type pad, this N-type electrode is laid in N-type GaN layer, and under the quantum well layer of active area, N-type pad and N-type electrode line link together; And
-passivation layer, this passivation layer is produced on P-type electrode line, N-type electrode line, transparency conducting layer.
Preferably, described array is square formation, circle, triangle or five-pointed star shape.
Preferably, described combined chip surface arranges the binding site of packaging and routing.
Preferably, described substrate is Sapphire Substrate, silicon carbide substrates or silicon substrate.
Make a method for the LED combination chip of above-mentioned array architecture, comprise step:
A, get the epitaxial wafer that comprises GaN base LED epitaxial structure, its epitaxial slice structure comprises substrate, N-type GaN layer, active area quantum well layer, P type GaN layer from bottom to up successively;
The luminous zone table top on B, step processing epitaxial wafer surface of being removed photoresist by photoetching, dry etching, cleaning, exposes N-type GaN layer and groove;
C, deposition dielectric isolation layer, dielectric isolation layer is transparent within the scope of 440-720nm, by photoetching, etch, the cleaning step that removes photoresist makes luminous zone mesa edge and for the equal coated insulation separator in position of cloth P-type electrode line;
D, deposit transparent conductive layer; By photoetching, etch step, the conductive layer material in N-type electrode district and groove is removed;
E, transparency conducting layer and P type GaN to be annealed, form ohmic contact; P, N-type electrode and pad and electrode wires is made by modes such as photoetching, deposition, stripping or etchings; P, N-type electrode metal and GaN semiconductor are annealed;
By ion source assisted or plasma enhanced chemical vapor deposition method deposit passivation layer after F, cleaning, and through photoetching, etch, the steps such as cleaning of removing photoresist expose electrode pad.
Preferably, dry etch step described in step B is reactive ion etching step or sense coupling step.
Preferably, dielectric isolation layer described in step C is silicon nitride, silica, silicon oxynitride, aluminium oxide.
Preferably, etching described in step C or step D is dry etching, or wet etching.
Preferably, transparency conducting layer described in step D is any one in tin indium oxide, nickel oxide gold or doping zinc-oxide.
The present invention has following beneficial effect:
1, routing difficulty is reduced: the present invention is the device that traditional GaN base light-emitting diode combines with IC circuit, the combined chip integrated by multiple traditional GaN base LED chip unit array, these chip units form one single core grain, only need at the surperficial routing of single core grain when user encapsulates, the number of times of client's routing can be greatly reduced, reduce encapsulation difficulty; These chip units connect into array format with metal wire, increase reliability;
2, luminous efficiency is improved: by large-area chip separation is become several fritters, with the type of drive work of big current small voltage, not only alleviate the stress because thermal mismatching and lattice mismatch cause, and increase light extraction efficiency due to increasing of sidewall area, thus improve luminous efficiency;
3, the present invention makes simply, and yield is high, can work under low voltage and high current, has the advantages that uniformity of luminance is good, product reliability is high.
Except object described above, feature and advantage, the present invention also has other object, feature and advantage.Below with reference to figure, the present invention is further detailed explanation.
Accompanying drawing explanation
The accompanying drawing forming a application's part is used to provide a further understanding of the present invention, and schematic description and description of the present invention, for explaining the present invention, does not form inappropriate limitation of the present invention.In the accompanying drawings:
Fig. 1 is the cross-sectional view of the preferred embodiment of the present invention;
Wherein, 1, substrate; 2, N-GaN layer; 3, Quantum well active district; 4, P-GaN layer; 5, dielectric isolation layer; 6, transparency conducting layer; 7, P-type electrode line; 8, passivation layer.
Embodiment
Below in conjunction with accompanying drawing, embodiments of the invention are described in detail, but the multitude of different ways that the present invention can limit according to claim and cover is implemented.
See Fig. 1, the present invention is array type large power GaN base LED combination chip, comprises that to be connected by array architecture wiring be some GaN base LED chips of one single core grain.Array can be square formation, circle, triangle, five-pointed star or polygonal shape, does not affect the realization of the present embodiment.
Every GaN base LED chip comprises from bottom to up successively:
-substrate 1, the material of substrate 1 can be sapphire (Al2O3), silicon carbide substrates or silicon substrate, has made periodic pattern (PSS) above it by the mode of dry etching;
-N-type GaN layer 2, the growth of this N-type GaN layer is on substrate 1;
-active area quantum well layer 3, this active area quantum well layer comprises multipair InGaN/GaN trap and builds structure, grows in N-type GaN layer 2;
-P type GaN layer 4, the growth of this P type GaN layer is on active area quantum well layer 3;
-dielectric isolation layer 5, this separator 5 is produced on N-type GaN layer 2 and P type GaN layer 4;
-transparency conducting layer 6, this transparency conducting layer 6 is produced on P type GaN layer 4 and dielectric isolation layer 5;
-P-type electrode 7 and P type pad, this P-type electrode 7 is laid on transparency conducting layer 6 and dielectric isolation layer 5, and P type pad and P-type electrode line 7 link together;
-N-type electrode and N-type pad, this N-type electrode is laid on N-type GaN2, and under the quantum well layer of active area, N-type pad and N-type electrode line link together; And
-passivation layer 8, this passivation layer 8 is produced on P-type electrode line 7, N-type electrode line, transparency conducting layer 6;
The manufacture method of above-mentioned array type large power GaN base LED combination chip comprises the following steps:
Get the epitaxial wafer that comprises GaN base LED epitaxial structure, its epitaxial slice structure comprises substrate, N-type GaN layer, active area quantum well layer, P type GaN layer from bottom to up successively.
Produce the luminous zone table top of all chip units that single core grain comprises by photoetching, dry etching, the cleaning step such as to remove photoresist, expose N-type GaN layer and groove; Wherein dry etching can be reactive ion etching (RIE), also can be inductively coupled plasma (ICP) etching etc.
Dielectric isolation layer is deposited by ion source assisted or plasma enhanced chemical vapor deposition method (PECVD) after cleaning, dielectric isolation layer is transparent within the scope of 440-720nm, and through photoetching, etch, the steps such as cleaning of removing photoresist make luminous zone mesa edge and for the equal coated insulation separator in position of cloth P-type electrode line; Wherein the material of dielectric isolation layer can be silicon nitride, silica, silicon oxynitride or aluminium oxide, and the mode of etching can be dry etching, also can be wet etching.
Deposit transparent conductive layer, and by the step such as photoetching, etching, the conductive layer material in N-type electrode district and groove is removed; Wherein transparency conducting layer 6 can be tin indium oxide (ITO), and also can be nickel oxide gold or doping zinc-oxide etc., the mode of etching can be dry etching, also can be wet etching; The mode of deposition can be common vapor deposition, also can be sputtering (Sputter) deposition.
Transparency conducting layer and P type GaN are annealed, forms ohmic contact; Wherein annealing way can be common furnace anneal, also can be short annealing (RTA) or electromagnetic wave annealing etc.
P, N-type electrode and pad and electrode wires is made by modes such as photoetching, deposition, stripping or etchings.
P, N-type electrode metal are annealed together with GaN semiconductor.
By ion source assisted or plasma enhanced chemical vapor deposition method (PECVD) deposit passivation layer after cleaning, and through photoetching, etch, the steps such as cleaning of removing photoresist expose electrode pad.
Be below two specific embodiments:
Embodiment one,
Be taken at the epitaxial wafer with GaN base LED chip construction of graphical sapphire substrate epitaxial growth;
By photoetching, respond to the luminous zone table top that the steps such as even summation plasma (ICP) etches, cleaning is removed photoresist produce all chip units that single core grain comprises, expose N-type GaN layer 2 and groove;
Use plasma enhanced chemical vapor deposition method (PECVD) to deposit dielectric isolation layer 5 after cleaning, dielectric isolation layer material is silica (SiO
2), and make luminous zone mesa edge and the equal coated insulation separator 5 in position for cloth P-type electrode line 7 through photoetching, wet etching, the steps such as cleaning of removing photoresist;
Deposit transparent conductive layer 6, and by the step such as photoetching, wet etching, the conductive layer material 6 in N-type electrode district and groove is removed; Wherein transparency conducting layer 6 material is tin indium oxide (ITO), and the mode of etching is wet etching; The mode of deposition is sputtering (Sputter) deposition;
Transparency conducting layer 6 and P type GaN layer 4 are annealed, forms ohmic contact; Wherein annealing way is short annealing (RTA);
P-type electrode, N-type electrode, P-type electrode pad, N-type electrode pad is made by modes such as negative-working photoresist, deposition, strippings, and P-type electrode line 7;
P, N-type electrode metal are annealed together with GaN semiconductor; Cleaning post plasma strengthens chemical vapour deposition technique (PECVD) deposit passivation layer 8, and the material of passivation layer 8 is silica (SiO
2), and through photoetching, etch, the steps such as cleaning of removing photoresist expose P, N-type electrode pad.
The size of an array type large power GaN base light-emitting diode chip for backlight unit is 45mil × 45mil, form array by 24 traditional GaN base LED chips to form, its 24 luminescence units are evenly luminous, and each side parameter such as its chip voltage, electric leakage, antistatic effect (ESD performance), reverse voltage, cut-in voltage all shows excellent, especially in luminous intensity, higher by 17.5% than single core grain luminous intensity of same area.And can learn from a mapping surveyed, produce comprehensive yield in its sheet and reach 91.72%.
Embodiment two,
Embodiment two implementation step and embodiment one similar, just dielectric isolation layer material is wherein silicon nitride (SiN), makes luminous zone mesa edge and the equal coated insulation separator 5 in position for cloth P-type electrode line 7 through photoetching, ICP etching, the steps such as cleaning of removing photoresist; Transparency conducting layer 6 material is nickel gold (NiAu), and the mode of etching is wet etching; The mode of deposition is ordinary electronic beam evaporation deposition; Anneal in transparency conducting layer 6 and P type GaN layer 4 in the lehr oxygen atmosphere, and the material of passivation layer 8 adopts silicon oxynitride (SiON).
The size of an array type large power GaN base light-emitting diode chip for backlight unit is 30mil × 30mil, form array by 18 traditional GaN base LED chips to form, its 18 luminescence units are evenly luminous, and each side parameter such as its chip voltage, electric leakage, antistatic effect (ESD performance), reverse voltage, cut-in voltage all shows excellent, especially in luminous intensity, higher by 10.5% than single core grain luminous intensity of same area.And can learn from a mapping surveyed, produce comprehensive yield in its sheet and reach 94.3%.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. make a method for the LED combination chip of array architecture, it is characterized in that, comprise step:
A, get the epitaxial wafer that comprises GaN base LED epitaxial structure, its epitaxial slice structure comprises substrate, N-type GaN layer, active area quantum well layer, P type GaN layer from bottom to up successively;
The luminous zone table top on B, step processing epitaxial wafer surface of being removed photoresist by photoetching, dry etching, cleaning, exposes N-type GaN layer and groove;
C, deposition dielectric isolation layer, dielectric isolation layer is transparent within the scope of 440-720nm, by photoetching, etch, the cleaning step that removes photoresist makes luminous zone mesa edge and for the equal coated insulation separator in position of cloth P-type electrode line;
D, deposit transparent conductive layer; By photoetching, etch step, the conductive layer material in N-type electrode district and groove is removed;
E, transparency conducting layer and P type GaN to be annealed, form ohmic contact; P, N-type electrode and pad and electrode wires is made by photoetching, deposition, stripping or etching mode; P, N-type electrode metal and GaN semiconductor are annealed;
By ion source assisted or plasma enhanced chemical vapor deposition method deposit passivation layer after F, cleaning, and through photoetching, etch, the cleaning step that removes photoresist exposes electrode pad.
2. a kind of method making the LED combination chip of array architecture according to claim 1, is characterized in that, dry etch step described in step B is reactive ion etching step or sense coupling step.
3. a kind of method making the LED combination chip of array architecture according to claim 1, it is characterized in that, dielectric isolation layer described in step C is silicon nitride, silica, silicon oxynitride, aluminium oxide.
4. a kind of method making the LED combination chip of array architecture according to claim 1, is characterized in that, etching described in step C or step D is dry etching, or wet etching.
5. a kind of method making the LED combination chip of array architecture according to claim 1, is characterized in that, transparency conducting layer described in step D be tin indium oxide, nickel oxide gold or doping zinc-oxide in any one.
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| CN103647010B (en) * | 2013-12-11 | 2016-08-31 | 湘能华磊光电股份有限公司 | A kind of preparation method of high-power LED chip |
| CN104022192B (en) * | 2014-06-16 | 2017-10-17 | 湘能华磊光电股份有限公司 | LED chips and preparation method thereof |
| CN104218133B (en) * | 2014-08-26 | 2017-04-26 | 华灿光电股份有限公司 | Light emitting diode chip and manufacturing method thereof |
| CN104362240B (en) * | 2014-10-31 | 2017-10-20 | 广东德力光电有限公司 | A kind of Al of LED chip2O3/ SiON passivation layer structures and its growing method |
| CN104733573B (en) * | 2015-03-31 | 2017-12-08 | 湘能华磊光电股份有限公司 | High-voltage LED and preparation method thereof |
| CN107482089A (en) * | 2017-08-08 | 2017-12-15 | 湘能华磊光电股份有限公司 | A kind of high brightness LED chip and preparation method thereof |
| CN107768490B (en) * | 2017-10-26 | 2020-07-10 | 江苏新广联半导体有限公司 | Preparation method for optimizing performance of GaN-based L ED chip |
| CN108615795B (en) * | 2018-03-27 | 2020-09-08 | 北京大学 | Method for realizing interconnection in micron LED chip |
| CN108598104A (en) * | 2018-06-25 | 2018-09-28 | 广东省半导体产业技术研究院 | A kind of micro- LED array of parallel connection and preparation method thereof |
| CN109166878A (en) * | 2018-09-29 | 2019-01-08 | 华南理工大学 | Nano-pore LED array chip and preparation method thereof with anti-reflection passivation layer |
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